CHAPTER 2 CIRCUIT ARCHITECTURE AND
2.3 SIMULATION RESULTS
2.3.2 SIMULATION RESULTS OF CURRENT-MATCH CHARGE
The current matches of charge pump type 2 improved result which shows in Fig.
2.34. In the waveforms, we can see the tail current of PMOS is 500uA and the tail current of NMOS is 500uA, and they are mirrored from 1/10 time of original current source. Fig. 2.35 show the sourcing and sinking current of charge pump type 2. In the waveforms, we find the sourcing current is 506uA and sinking current is 505uA when “UP pulse” and “DOWN pulse” are on at same time, the current mismatch variation just only 1uA .
Fig. 2.34 The simulation result of charge pump 2 tail current match waveforms
Fig. 2.35 The simulation result of current match charge pump type 2 Table 10 shows the simulation result of the rail-to-rail OP (OP1) for charge pump type 2. The results are to fit the application in charge pump type 2 output voltage with VCO input voltage. Fig. 2.36 show the distributed of gain and VCO input range.
Table 10 The simulation results of rail-to-rail OP for charge pump type 2
Rail-to-Rail OP1 Gain
0 20 40 60 80 100 120 140
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 VCO input Range (V)
Gain (dB)
Fig. 2.36 The gain distributed of rail-to-rail OP
Following table 11 compared the simulation result and layout area about charge pump type1 and type 2. The current match characteristic of charge pump is type 2 better than type 1.
Table 11 Compare the simulation results of charge pump type1 and type 2
2.3.3 Simulation results of frequency divider
Fig. 2.37 shows the simulation result of divide-by-2 and prescaler divider. In the waveforms, the ÷8/9 function work correctly.
Fig. 2.37 Prescaler (÷8/9) and ÷2 simulated results.
Fig. 2.38 shows the program and swallow counters simulation results. Those functions work correctly in channel 5.
Fig. 2.38 Program and swallow counter simulation results (channel 5).
2.3.4 Simulation results of PFD
The PFD simulation result is shown in Fig. 2.39. We can see the waveforms of 3rd and 4th work correctly when input clock is fast than feedback clock which UP pulse is generated or input clock slower than feedback clock which DOWN pulse is generated. The 6th waveform is “RFCK” signal which if “RFCK” is high then make
“up pulse” always low and “down pulse” always high. Opposite, the 7th waveform is
“RRCK” which if “RRCK” is high then make “up pulse” always high and “down pulse” always low. Those functions applied to test charge pump current is usefully.
Fig. 2.39 The simulation result of PFD function
Fig. 2.40 showing the “UP” and “DOWN” pulses turn on at the same time which has perfect layout match of delay time at two paths after post-simulation. And the zero dead zone delay is 0.5nS.
Fig. 2.40 The simulation result of PFD locks state
2.3.5 Simulation results of close loop synthesizer
Fig. 2.41 shows the settling time of close loop 1 (include charge pump type 1) of frequency synthesizer is smaller than 16uS (802.11a). Fig. 2.42 shows the synthesizer worked at channel 8, frequency is 5.32GHz.
Fig. 2.41 Settling time of close loop 1 simulation of the synthesizer
Fig. 2.42 Synthesizer loop 1 works at channel 8 that frequency is 5.32GHz.
Fig. 2.43 shows the settling time of close loop 2 (include charge pump type 2) of frequency synthesizer is small than 16uS (802.11a). Fig. 2.44 shows the synthesizer worked at channel 8, frequency is 5.32GHz.
Fig. 2.43 Settling time of close loop 2 simulation of the synthesizer
Fig. 2.44 Synthesizer loop 2 works at channel 8 that frequency is 5.32GHz.
2.4 Summary
Table 12 lists all characteristics about the simulation of frequency synthesizer in this work after added parasitical devices. Those data are measured after post-simulation. All properties close to IEEE 802.11a and have some perfect characteristics more than other structure of frequency synthesizer. The total chip area is smaller then 1 mm².
Table 12 The simulation results summary of frequency synthesizer
CHAPTER 3
EXPERIMENTAL RESULTS
This frequency synthesizer has been fabricated in TSMC 0.18um 1P6M RF CMOS process. There are two loops of synthesizer be measured, one loop collocated charge pump type 1 and another loop collocated charge pump type 2. External low pass filter connected different charge pump output point to make different loop. In this measurement results, all characteristics be compared about two different loops.
Anyways, the best performance of synthesizer apply with charge pump type 2 of loop, and the phase noise is -107.36dBc @ 1MHz offset, and spurious tones is -69.52dBc @ 10MHz. Whole chip power is 18.85mW for PFD, program and swallow counter work at 1.4V power supply and another block work at 1.8V. Total layout area is 0.97mm². The loop settling time is smaller than 16uS.
3.1 Chip on board testing and setup
Fig. 3.1 shows the testing board that includes one chip on main board and two DC boards. The main board includes main die, four phases of VCO output and low pass filter. One of the DC board includes low path filter for power supply, channel select of jumpers, band pass filter for input reference clock and variable resisters for bias current. And another DC board includes 1.8V regulators and batteries.
Fig. 3.2 shows the testing board function block. The battery and regulator can decrease the power noise and decrease the spurious tones effectively. In the testing function block which use an AWG to generate square waveform to input to the chip and use a spectrum analyzer to measure the chip output signals. Further to test the settling time and feedback clock use two scopes to do it.
Fig. 3.1 The photo of the testing board in this work
Fig. 3.2 The function block of the frequency synthesizer and testing environment Fig. 3.3 shows the photo of main die and describes all sub-block layout places.
In the photo, the main layout area consume at inductors of VCO.
Fig. 3.3 The photo of main die in this work
3.1.1 Measure result of VCO
Fig. 3.4 shows the turning range and output frequency of the VCO. There are three gain curves variation to describe the “pre-simulation”, “post-simulation” and
“measurement”. The testing curve of VCO gain is smaller then pre-simulation and post-simulation. From the testing curve to see the frequency is higher than post-simulation and frequency range is smaller than other. The Kvco decreases from 480 MHz in post-simulation to 450 MHz and the frequency range is 5.17 GHz ~ 5.62 GHz in measurement.
Fig. 3.4 The frequency and input turning range curves of VCO VCO Turning Range Compare
3.1.2 Measure result of frequency synthesizer
In this work, many factors make the spurious tones had large power level. The power supply generated while noise to effect power level of spurious tones is very serious. Another noise effect power level of spurious tones is charge pump current mismatch. So, we selected three dies to measure and compare the spurious tones of power level base on different charge pump type and different power source. In table 13, that shows the measurement results of the three chips. From those chips to see that chip 1 performance bad than other chips. Maybe chip 1 is a bad die in the edge of a wafer. But the three chips have same variation for different type of charge pump and different power supply source. Summary the results, the spurious tones power level of charge pump type 2 is smaller then charge pump type1 about 1.32dBc and the spurious tones power level of using battery added regulator is smaller then only using regulator about 0.81dBc. Fig. 3.5 shows frequency response of chip 3, which use charge pump type 2 and regulator with battery of power source. The power level of spurious tones is -69.52 dBc @ 10MHz
Table 13 The measurement results of spurious tones
Fig. 3.5 The power level of spurious tones is channel 7 for charge pump2 and the power source is battery with regulator
Fig. 3.6 The measurement result of feedback clock
Fig. 3.6 shows the reference clock and feedback clock in PLL locked state.
Ideally, the rising edge of reference clock with the rising edge of feedback clock active at same time in locked state, but the waveforms in Fig. 3.6 have some delay time between reference clock (AWG input) and feedback clock. Why? Because the feedback clock close to 10 MHz which need some buffer to drive the testing PAD for easy to test. In Fig. 3.6, the measurement results of reference clock and feedback clock are the same which close to 10 MHz. So, the loop is locked.
Table 14 shows the output range and current variation of charge pump type 1 and type 2. The charge pump type 2 has perfect current match but that has small output range and large power consumption and layout area.
Fig. 3.7 shows the settling time of synthesizer in close loop for charge pump type 2. The measurement probe of scope needs an active probe. The measurement result of the settling time is 13.5uS that use active probe to test. It meets the specification of IEEE 802.11a which is smaller than 16uS.
Fig. 3.8 shows the frequency synthesizer phase noise for charge pump type 2.
The measurement result of phase noise is -107.36 dBc @ 1MHz offset.
Table 14 The measurement results of charge pump type 1 and type 2
Fig. 3.7 The measurement result of settling time in close loop (charge pump type 2)
Fig. 3.8 The measurement result of phase noise in 1 MHz offset (charge pump type 2)
3.2 Comparison
Table 15 compares all characteristics in this work with another three papers of 5 GHz frequency synthesizer. In this work, the charge pump current is larger than other 10 time to get fast settling time in wide loop bandwidth. In [2], the loop bandwidth design in narrow band to get low spur power level, but it’s settling was too slow. In [1], the synthesizer never used current match charge pump and the spur power level was highest. Another to bring up in [1] is large layout area which used ILFD divider.
In [4], the synthesizer applied a current match charge pump to get low power level of spur. Anyway, this work performance meets IEEE.802.11a and has perfect current match structure of charge pump.
Table 15 Compare all characteristics of frequency synthesizer
3.3 Discussion
After designed and measured the frequency synthesizer, there are some functions which need to improve even more batter. So, in this section have some discussions to bring up.
(1) How does the synthesizer to solve the variation of the output range in charge pump type 2?
(2) In this work, the performance of spur level is smaller than [2]. Why?
(3) The power consumption still larger than [2].
(4) The charge pump type 2 still has some different about current mismatch in simulation and measurement.
In discussion (1), the charge pump type 2 could not work at wide output range for VCO. Because the MOS Vt has some variation which makes the NMOS working at triode region and lets output range of charge pump type 2 smaller than simulation results. The current mismatch makes the spur level increasing when output voltage is below 0.4V which shows in table 14. Using an active low pass filter can solve the problem [24], but the active low pass filter has larger layout size and power computation, so it need be design in off-chip. Fig. 3.9 shows the active low pass filter circuit. Anyway, the output voltage of charge pump has not varied, and the positive terminal is fixed at half of VDD or other optimum voltage for lower affect of channel length modulation about PMOS and NMOS. This way need an OP and passive devices of resisters and capacitors to combine an active low pass filter. In this application, using a National Semiconductor’s rail-to-rail OP “LMV931” can
prove the active low pass filter which let Vb = Vop to reduce the effect of channel length modulation. The measurement results are showing in table 16.
In discussion (2), the loop bandwidth was designed in 0.12 time of this work.
So, the [2] had perfect characteristic of spur level. But the design of [2] lost the settling time of condition which it can not apply in specification of IEEE.802.11a. If the circuit of low pass filter be merged in the chip, than it will need large layout area.
In discussion (3), the structure of divide-by-2 of TSPC is good chaise in application of high speed and low power consumption in [2]. But the structure has high/low duty cycle unbalance that duty cycle is 25% in worse case, and the single signal of structure difficult to work in quadrature phase output of VCO for low noise issue. Other brings up problem of TSPC structure could not work to 5.5 GHz at simulation in TSMC process. So, this work chooses another structure of divide-by-2 is Pseudo-NMOS gate.
Fig. 3.9 The active low pass filter apply in charge pump output
Table 16 Measurement results of synthesizer using active low pass filter
In discussion (4), the process variation makes a little current mismatch in charge pump type 2 UP/DOWN current at simulation and measurement. In Fig. 3.10 and Fig.
3.11 show the simulation results of process variation makes threshold voltage Vt has some variation which makes current mismatch in charge pump type 2. If Vt has variation -4% then current has variation from 500uA to 502.5uA and current
mismatch is 0.49%. But the current mismatch effect the spur level is too small which can ignore it.
Charge pump type 2 current variation
496.7 497.4 498.2 498.6
499.5 500 500.6 501.2 501.9 502.5503.1
492
Fig. 3.10 The variations of charge pump current and Vt
Charge pump type 2 current mismatch
Fig. 3.11 The current mismatch with Vt variation
CHAPTER 4
CONCLUSIONS AND FURTURE WORKS
4.1 Conclusions
A low spurious tone of 5 GHz CMOS frequency synthesizer for wireless LAN transceivers has been presented. The synthesizer integrated in a 0.18um CMOS technology consumes only 18.8mW in 1.8V/1.4V power supply. This work includes a quadrature VCO and Pseudo-NMOS of divide-by-two latch. All chip layout area smaller than 1mm². The PLL working frequency reaches 5.628GHz and loop phase noise is -107dBc at 1 MHz offset. The close loop of settling time is 13.5uS to meet specification of IEEE.802.11A.
Two perfect current matches of charge pump circuits are implemented and compared in this work. One is a current-steering of charge pump and another is a new current-switching of charge pump. Compare the measurement results of those two types of charge pump circuits to found the new current-switching has perfect current match characteristic more than current-switching charge pump. The spurious tones of new current-switching charge pump circuit can be suppressed to -69.52 dBc at 10 MHz offset. The new charge pump circuit can effectively suppress the spurious tones successfully.
4.2 Future works
Although the new charge pump can suppress the spurious tones effectively. But some application of wide input range of VCO can not work correctly. And the total power consumption still large more, because large part of power dominate at divide-by-two block. Another bring up problem is chip integration of SOC; this work could not merge low pass filter circuit in chip. So, some future works is list following:
(1) Re-design the chip working on low power supply to reach low power consumption; maybe the power supply is lower than 1V.
(2) Use active low pass filter to apply in wide input range of VCO to decrease the effect of channel length modulation.
(3) Develop another structure of divider for lower power and high speed application.
(4) Merge low pass filter circuit to reach real SOC.
REFERENCE
[1] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS Frequency Synthesizer With an Injected-Locked Frequency Divider for a 5-GHz Wieless LAN
Receiver＂ IEEE J. Solid-State Circuits, vol. 35, NO. 5, pp. 780-787,May 2000.
[2] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider＂
IEEE J. Solid-State Circuits, vol. 39, NO. 2, pp. 378-383, Feb 2004.
[3] Nagendra Krishnapura and Peter R. Kinget, “A 5.3-GHz Programmable Divider for HiPerLAN in 0.25um CMOS＂ IEEE J. Solid-State Circuits, vol.
35, NO. 7, pp. 1019-1024, Jul 2000.
[4] Chih-Ming Hung and Kenneth K. O, “A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop＂ IEEE J. Solid-State Circuits, vol. 37, NO. 4,
pp.521-525, APR 2002.
[5] Chung-Chih Su “The Design of a Low-Spurious-Tones CMOS Frequency Synthesizer for 2.GHz Transceiver” A thesis Submitted to Degree Program of Electrical Engineering and Computer Science College of Electrical Engineering and Computer Science National Chiao Tung University, July 2002
[6] Li Lin, Luns Tee, Pual R. Gray “A 1.4GHz Differential Low-Noise CMOS Frequency using a Wideband PLL Architecture,” ISSCC Digest Technical Papers
[7] U. Rohed, Digital PLL Frequency Synthesizer: Theory and Design. Englewood Cliffs, NJ: Prentice-Hall 1983
[8] J. Craninckx and M. S. J. steyaert, “A 1.75GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7um CMOS,” IEEE J. Solid-State Circuits, vol.
31, no. 7, pp. 890-897, July 1996.
[9] J. Yuan and C. Svensson. “High-speed CMOS circuit technique”, IEEE J.
Solid-State Circuits, vol. 24, pp. 62-70, Feb, 1989.
[10] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-Based RF IC’s” in Symp. VLSI circuit Dig, 1997, pp. 85-86.
[11] C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S. Wong, “A physical model for planar spiral inductors on silicon” in IEDM Tech. Dig., 1996, pp. 6.5.1-6.5.4 [12] M. Rofougaran, A. Rofougran, J. Rael, and A. A. Abidi, “A 900-MHz CMOS
LC- oscillator with quadrature outputs,” in Proc. 26th Eur. Solid-State Circuit Conf., New York, NY, 1996, p. 392.
[13] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators, “IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998.
[14] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators, ” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
[15] Christopher Lam and Behzad Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4um CMOS Technology,” IEEE J. Solid-State Circuits, Vol.
35, pp. 788-794, May 2000.
[16] Joonsuk Lee and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, Vol.
35, pp. 1137-1145, Aug 2000.
[17] Jae-Shin Lee, Min-Sun Keel, Shin-II Lim and Suki Kim, “Charge pump with
perfect current matching characteristics in phase-locked loops,”
ELECTRONICS LETTERS, 9th , Vol. 36 pp. 1907-1908, No. 23 Nov 2000.
[18] Thomas H. Lee, Member, IEEE, Hirad Samavati, and Hamid R. Rategh,
“5-GHz CMOS Wireless LANs,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 268-280, NO. 1, Jan 2002.
[19] M. Johnson and E. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223. Oct.
1988.
[20] Salvatore Levantino, Carlo Samori, Andrea Bonfanti, Sander L. J. Gierkink, Andera L. Lacaita, and Vito Boccuzzi, “Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion,” IEEE J. Solid-State Circuits, vol. 37, NO. 8, pp. 1003-1011.
Aug. 2002.
[21] Pietro Andreani, Andrea Bonfanti, Luca Rmano, and Carlo Samori, “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, NO. 12, pp. 1737-1747. Dec. 2002.
[22] P. van de Ven, J. van der Tang, D. Kasperkovitz, and A. van Roermund, “An optimally coupled 5 GHz quadrature LC oscillator,” in Proc. 2001 Symp. VLSI Circuits, June 2001, pp. 115-118.
[23] H. R. Rategh and T. H. Lee, “Superharmonic injection locked oscillators as low power frequency dividers,” in Symp. VLSI Circuit Dig., 1998, pp.
132-135.
[24] Gerry C.T. Leung and Howard C. Luong “A 1-V 5.2-GHz CMOS Synthesizer for
WLAN Applications,” IEEE J. Solid-State Circuits, Vol. 39, NO. 11, NOV 2004.
簡 歷
許德賢於西元 1973 年一月十五日出生於台灣省高雄縣，性別男。西 元 1997 年畢業於雲林科技大學，獲電子系工學學士學位。西元 1997 年 任職於茂達電子公司類比 IC 設計工程師。西元 2000 年任職於揚智科技 公司類比 IC 設計研究員。西元 2004 年畢業於國立交通大學電機資訊學 院碩士在職專班，獲電電機資訊學院電子與光電組碩士學位。
主修學科有: 類比積體電路，數位積體電路，數位訊號處裡，無線
主修學科有: 類比積體電路，數位積體電路，數位訊號處裡，無線