Fabrication of Flip-Chip Bonding Process - The Fabrication Process of the Flip-Chip Structure

Chapter 2 The Fabrication Process of the Flip-Chip Structure

2.2 Fabrication of Flip-Chip Bonding Process

After finishing the substrate process, the HEMT device and the passive transmission line were flip-chip bonded on the fabricated substrate by Au-to-Au thermal compression bonding process using M9 flip-chip bonder. Figure 2.2 shows the photograph of the flip-chip bonder. The bonding conditions, such as bonding temperature, bonding force and bonding time were optimized to achieve good interconnection between chip and substrate without significant loss. The bonding temperature on the chip side and the substrate side were 180 ℃ and 300 ℃, respectively. The bonding force was 10 grams per bump and maintained about 3 minutes.

2.3 Underfill Process of the Flip-chip Structure

The underfill was used to improve the reliability of the flip-chip interconnections because the connections between the chip and substrate are just some small Au bumps with 50 um of the diameter. The RF performance of the flip-chip structure with

underfill injection will be changed due to the change of the characteristic impendence.

Hence, the epoxy resin (dielectric constant~3.5; dielectric loss~0.02) was studied the impacts of the underfill on electrical and mechanical properties.

The in-house process of epoxy resin injection is shown in Fig. 2.3. First, the chip and the substrate were heated to 180 ℃ and 300 ℃ on M9 flip-chip bonder, respectively. After finishing the flip-chip bonding process, the sample was cooled down to 90 ℃ and then the epoxy resin was injected into the gap between chip and substrate by using the capillary force. When the underfill completely flowed to another side, a curing process at 150 ℃ for 2 hours was performed to make cross-linking of the polymer chains. Figure 2.4 shows the cross section view of the flip-chip structure with underfill. The image exhibits that the underfill successfully flowed into the gap between the chip and the substrate.

2.4 No-flow Underfill process for Flip-chip Structure

According the experiment result, liquid BCB cannot easily flow into the gap between the chip and substrate using capillary force. The BCB can’t be fully filled into the gap between chip and substrate. To solve this issue, the no-flow underfill process was proposed as shown in Fig. 2.5. Liquid BCB was first deposited on the substrate. Then the substrate was heated to cause BCB to flow. The heating conditions, such as the heating time and temperature, were optimized to enhance the BCB flow.

Finally, the chip and the substrate were flip-chip bonded by using the Au-to-Au thermo-compression method. An additional curing at 250 ℃ for 2 hours was performed to facilitate cross-linking of the BCB polymer chains.

2.5 Scattering Parameter Measurement

Scattering Parameters (S-parameter) are fundamental to microwave measurement.

These parameters were defined by the small signal gain and input/output emittance properties of any linear two port network [49].

The S-parameter measurement was characterized from 2 to 110 GHz by using an HP 8510XF network analyzer with E7352 test heads calibrated by using a standard load-reflection-reflection-match (LRRM) method.

Fig. 2.1

The in-house fabrication process of the Al2O3 substrate

27 Fig. 2.2The image of the M9 flip-chip bonder

28 Fig. 2.3The in-house process of epoxy resin injection

Fig. 2.4TheSEM cross section view of the flip-chip structure with underfill.

Fig. 2.5 Theno-flow underfill process flow for flip-chip structure.

Chapter 3 A Flip-chip Packaged InGaAs MHEMT Device on A1

₂

O

₃

Substrate for MMWs Low-Noise Applications

In this chapter, a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an Al₂O₃ substrate with very little degrade on device RF performance up to 60 GHz is firstly presented. After the flip-chip packaging, the device exhibited high I_DS = 435 mA/mm at V_DS= 1.5 V, high g_m= 930 mS/mm at V_DS= 1.3 V. And the measured gain was 7.5 dB and the minimum noise figure (NFmin) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range. Besides, a two-stage gain block at 60 GHz was designed and fabricated using the microwave integrated circuit (MIC) approach to demonstrate the applicability of such device for V-band applications. The MIC approach offers certain cost competence because of the smaller semiconductor area with a simple fabrication process, high production yield due to the ease of handling ceramic substrates, and ability to prescreen devices during the assembly process. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal–oxide–semiconductor (CMOS) technology with lower power consumption.

3.1 Background and Motivations

In recent years, MMWs products, including auto-motive radar systems and high-resolution imaging sensors, develop rapidly because these frequency bands provide superior characteristics such as high resolution of images, wide available bandwidth, and small component size [50,51]. In such systems, low noise amplifiers (LNA) play a critical role in maintaining the desired signal-to-noise ratio (SNR) at the receiving end to guarantee proper system operation. In general, there are two main approaches to realize the MMWs circuits. The first approach is the MMICs. The MMICs is a popular design for MMWs applications because of low cost, improved reliability, reproducibility, and circuit design flexibility with multifunction performance on a chip [52]. The other approach is MICs. The advantages of MICs design are smaller chip size, selective active devices with applicable performance and simple fabrication process without via hole [14,15]. However, the use of MMWs MICs design is restricted by the interconnect technology connecting active device and substrate. In the conventional MICs design, the wire-bonding is usually used as the interconnect technology. However, when operating at higher frequencies, it becomes inappropriate because the parasitic effect due to long interconnection between device and substrate that will significantly affect overall performance. Thus, the use of flip-chip technology is proposed for MMWs applications due to its short interconnect length, good thermal management, better mechanical stability and small package size [23,26]. Sakai demonstrated the MIC design with flip-chip packaged HEMT and HBT devices on Si substrate to form one-stage and two-stage amplifiers operating at 20 GHz [14]. Arai reported the 60 GHz MIC design with flip-chip assembled 0.10

lm-gate pHEMT on the ceramic substrate [15]. In these MMWs MIC designs, the circuit performance is mostly depending on the active device characteristics, such as gain, noise figure and output power. In terms of device technology for such applications, In-rich In_xGa_1-xAs-channel HEMTs have been proven working due to the superior electron mobility and saturation velocity [53]. While a lot of research efforts have been devoted to the device technology, very few reports addressed the packaging technology for such devices applied at high frequencies.

3.2 Fabrication and Flip-chip Package Process

The in-house fabricated 80-nm In_0.7Ga_0.3As-channel MHEMT with Pt-buried gate was employed. The epitaxial layer was grown on a 3-inch semi-insulating GaAs substrate by molecular beam epitaxy (MBE). The epitaxial structure is shown in Fig.

3.1. The indium-rich heavily-doped In_0.65Ga_0.36As cap layer was used and a low ohmic contact resistance of 0.05 Ω·mm was achieved.

The device fabrication process was reported in our previous paper [54]. After finishing the device process, the wafer was thinned down to 100 um and diced into discrete MHEMT dies for flip-chip packaging process. The image of the fabricated MHEMT device is shown in Fig. 3.2 (a).

Fig. 3.3 shows the process flow of the Al₂O₃ carrier for flip-chip assembly. The Al2O3 was chosen due to its superior material properties, i.e. dielectric constant of 9.8 and loss tangent of 0.0006. Firstly, the seed layers of titanium (Ti) and gold (Au) metal (300 Å and 500 Å ) were deposited on Al₂O₃ substrate by E-gun evaporator. The Ti

layer was used to enhance the adhesion between the Al₂O₃ substrateand Au metal layer. Thin photoresist was then patterned on the Al₂O₃ substrate for later gold electroplating of the CPW transmission line. The characteristic impendence of the CPW transmission line with optimum dimensions was 50 ohm. After electroplating, the thickness of the CPW transmission line was 3 um. The thick photoresist from TOK Company was used and patterned for the gold bump electroplating. The final bump and CPW patterns are shown in Fig. 3.2 (b). Finally, the thick photoresist and seed layers were removed. For our specific applications targeted in millimeter wave frequencies, the bump height was optimized to be 20 um through experimental characterizations of passive circuits composed of 50  lines in CPW structure on both the GaAs and Al₂O₃ substrates. Quantitatively, the inductance of the bump was extracted to be 80 pH in the frequency range of interest.

The In_0.7Ga_0.3As MHEMT device was flip-chip assembled onto the fabricated Al₂O₃packaged substrate by flip-chip bonder. The schematic of the flip-chip device structure is presented in Fig. 3.2 (c). The thermo-compression bonding process with optimized bonding conditions such as bonding force, time, and temperature was employed. The image of the flip-chip packaged 80-nm In_0.7Ga_0.3As MHEMT on Al₂O₃ substrate is shown in Fig. 3.2 (d).

3.3 Measured Results of the Packaged MHEMT on Al

O

Substrate

Fig. 3.4 shows the drain current (IDS) versus drain voltage (VDS) characteristics with various gate voltage (V_G) of the MHEMT device before and after flip-chip assembly. The maximum drain current density (IDS) of 435 mA/mm was obtained at

V_DS = 1.5 V and V_G = 0.2 V. The comparison of the measured transconductance (g_m) and I_DS as a function of V_G at V_DS = 1.3 V with and without flip-chip packaging is shown in Fig. 3.5. The maximum g_m peak and drain current of the packaged device at a V_DS of 1.3 V were 930 mS/mm and 425 mA/mm, respectively. This high transconductance is due to the superior electron transport properties in the In_0.7Ga_0.3As channel and good ohmic contact. The device can be well pinched off with a threshold voltage (V_T) of -0.45 V due to the Pt sinking into barrier layer. As is observed from these measured results, the dc performance of the flip-chip packaged device showed slight difference compared to the bare device, indicating a very low contact resistance from Au bump to CPW transmission line.

The RF performances were characterized by using on-wafer probing measurement system with vector network analyzer (VNA). The Short-Open-Load- Thru (SOLT) calibration technique was used to calibrate the measurement system.

During the measurement, a 5 mm thick layer of Rohacell 31 was put between the Al2O3 substrate and the metal chuck of the probe station to avoid the grounding effect on the backside of the substrate. As observed from Fig. 3.6, the packaged device showed a high insertion gain of 7.5 dB at 60 GHz. The return loss (S₁₁) and gain (S₂₁) remained the same for the bare device and packaged device at frequencies up to 50 GHz. However, the S21 of the flip-chip device showed a slight degradation for frequencies above 50 GHz, which is attributed to the additional inductance induced from the bump transition. Besides, due to the good electrical conductivity of Au metal and the good interface transition achieved between the CPW Au plated circuit and Au bumps, the transmission losses on the signal transmission path was reduced.

To evaluate the feasibility of this packaged structure for MMWs low-noise applications, the noise figure (NF) of the In_0.7Ga_0.3As MHEMT device was characterized with the frequency range of 22 to 60 GHz. The measured noise figures of the device before flip-chip assembly with different dc power consumptions at 54 GHz are shown in Fig. 3.7. As can be seen, the minimum noise figure (NF_min) was less 2 dB below 10 mW power consumption. Fig. 3.8 shows the NF_min and the corresponding associated gain (Ga) for the device with and without flip-chip package under the optimal bias conditions. The measured NF_min was 2.7 dB up to 60 GHz after flip-chip packaging with 11 dB corresponding Ga. Meanwhile, for the device without package, the NF_min and Ga were 2.4 dB and 11.5 dB, respectively. Evidencing from the measurement results, the DC and RF performances of the In_0.7Ga_0.3As MHEMT still exhibited very good electrical performances up to 60 GHz after flip-chip package.

3.4 V-Band Flip-Chip Assembled Gain Block Using In

0.6

Ga

0.4

As MHEMTs Technology

To demonstrate the applicability of the device for V-Band application, a two-stage gain block was designed and realized using the MIC approach. The adopted substrate was 127-μm-thick Al2O3 with a relative dielectric constant of 9.8. Microstrip line circuits were patterned with 3μm thick Au metal. It is worth mentioned that the passive components, such as metal–insulator–metal (MIM) capacitors and thin-film resistors (TFRs), are excluded in the circuit realization to ensure that the fabrication process is simple and straightforward along with the flip-chip packaging. The main

advantage of this approach lies in the fact that the inclusion of matching circuits on the original carrier for flip-chip packaging provides a cost-effective solution for seamless integration of the device into the circuit.

Fig. 3.9 shows the circuit diagram of the two-stage gain block designed at 60 GHz. The matching circuits with the included bumps at the input, output, and interstage were designed for conjugate matching of the S-parameters and were realized with transmission lines and open stubs. Bandpass filters with coupled-line configuration were employed for DC blocking in the input, output, and interstage circuits. The gate and drain bias were supplied through the biasing network consisting of high impedance lines and radial stubs. The geometries of the radial stubs were determined through electromagnetic simulations so that the impedance levels were high enough to prevent the RF signal from leaking to the DC path. Fig. 3.10 shows the measured S-parameters of the fabricated gain block. Both stages were biased at VDS = 0.5 V and VGS = 0.4 V, corresponding to a total DC power consumption of 20 mW. A measured small-signal gain of 9 dB was obtained at 60 GHz with effective input and output S11. The loss in gain performance was mainly from the insertion loss of the bandpass filters at the input and output ends. The metallic loss of the input, interstage, and output matching networks also contributed to the overall loss. The favorable agreement between the simulated and measured performances validated the design method.

3.5 Summary

The in-house fabrication of the flip-chip package of 80-nm gate In_0.7Ga_0.3As MHEMT device on Al₂O₃ substrate was presented. After flip-chip packaging, the device showed high I_DS = 435 mA/mm at V_DS= 1.5 V, and high g_m= 930 mS/mm at V_DS= 1.5 V, which is almost the same as the bare chip performance. The packaged devices also showed very small change in RF characteristics with NF_minof 2.7 dB and Ga of 11 dB at 60 GHz after packaging. The flip-chip packaged low noise In0.7Ga0.3As MHEMT device exhibited superior DC and RF performance, demonstrating the feasibility of using the proposed flip-chip technology for MMWs low noise applications.

To demonstrate the applicability of device using MICs design for V-band applications, a two-stage gain block at 60 GHz was designed and realized using a simple fabrication process. A 150 nm gate In0.6Ga0.4As mHEMT device was flip-chip packaged on an Al2O3 substrate. The small signal gain was measured to be 9 dB at 60 GHz with only 20 mW DC power consumption. The superior performance proved the applicability of such technology as a cost-effective solution for 60 GHz applications.

Fig. 3.1 Epitaxial layer structure of the In0.7Ga0.3As high electron mobility transistors

(HEMTs)

Fig. 3.2 (a) Image of the in-house fabricated 80-nm gate In_0.7Ga_0.3As MHEMT device,

(b) The SEM image of the electroplated micro Au bumps (c) The schematic of the

flip-chip packaged structure (d) Image of the flip-chip packaged In_0.7Ga_0.3As

MHEMT device on Al₂O₃ substrate.

(a)

(b)

(c)

(d)

Fig. 3.3 In-house fabrication flow of the alumina (Al2O3) substrate for flip-chip packaging

structure

0.0 0.3 0.6 0.9 1.2 1.5

0 100 200 300 400 500

D rai n C urrent I

(m A /mm )

Drain-source Voltage V_DS (V)

In0.7Ga

0.3As HEMTs Lg = 80 nm; V

G -0.6 ~ 0.2 V Before Flip-chip After Flip-chip

Fig. 3.4 Comparison of drain-source current (IDS) versus drain-source voltage (VDS) curves

with various gate voltages (VG) of In0.7Ga0.3As MHEMT devices with and without flip-chip

packaging.

Fig. 3.5 Comparison of drain current density (IDS) and transconductance (gm) as a function of

gate-source voltage (VGS) at VDS = 1.3V for In0.7Ga0.3As MHEMT devices with and without

flip-chip packaging.

0 10 20 30 40 50 60

-5 0 5 10 15 20

S

₂₁

S-Parameter (dB)

Frequency (GHz)

In0.7Ga

0.3As; Lg = 80 nm V_DS = 1.3 V; V_G = 0 V

Before Flip-chip After Flip-chip

Fig. 3.6 Comparison of insertion gain (S21) and reflection loss (S11) for In0.7Ga0.3As MHEMT

devices with and without flip-chip packaging.

1 10

0 1 2 3 4 5 6

40 30 20

In0.7Ga

0.3As; Lg = 80 nm VDS= 1.0 V

Frequency = 54 GHz

N o ise Figu re (d B )

DC Power Consumption (mW)

Fig. 3.7 The minimum noise figure with different DC Power consumptions at VDS = 1 V for

In0.7Ga0.3As MHEMT devices before flip-chip packaging

-0.1 V for In0.7Ga0.3As MHEMT devices with and without flip-chip packaging.

Fig. 3.9 Circuit diagram of the two-stage gain block designed at 60 GHz.

Fig. 3.10 Measured S-parameters of the fabricated gain block biased at VDS = 0.5 V and VGS = 0.4 V.

Chapter 4 Investigation of the Flip-chip Package with BCB Underfill for W-band Applications

Flip-chip package is promising for MMWs applications. However, the CTE mismatch between the chip and the substrate generates thermal stresses that fracture the flip-chip structure. The use of underfills with low dielectric loss is essential to improve the mechanical strength and reliability of the flip-chip package. BCB (Benzocyclobutene) was used in this study as the underfill material for the flip-chip structure using the no-flow process. The flip-chip structure with BCB injection provides good RF performance with a S₁₁ of better than 18 dB and an S₂₁of 0.6 dB up to 100 GHz. Furthermore, thermal cycle and shear force tests showed that the underfill injection can significantly improve the reliability of a flip-chip package.

4.1 Background and Motivations

Wireless communication and imaging systems at MMW and sub-MMW frequencies are gaining increasing attention. Packages with good electrical performance, decent mechanical reliability and low cost are crucial for high frequency applications. Flip-chip interconnects are considered as a promising interconnect technology due to several reasons [31,55]. Compared with conventional wire-bonding technology, flip-chip has much shorter interconnects, significantly reducing the parasitic effects at MMW frequencies [56]. However, the reliability of flip-chip

packaging is critical due to the thermal mechanical stresses from CTE mismatch of substrate and chip CTE [38,57]. Many previous studies have investigated the underfill effect in a flip-chip structure [23,40,48]. Kusamitsu et al. demonstrated LNA flip-chip bonded Al₂O₃ with an epoxy-based underfill with response shifted in frequency due to the underfill injection [23]. Feng et al. presented increase in the fatigue life with only a small additional loss of flip-chip assemblies [38]. Improvement in the reliability with small loss of flip-chip structure on polymer substrate has also been achieved in [49].

Conventional epoxy-based underfill has a high dielectric loss tangent which induces extra signal dissipation and degrades RF performance. Previously, by performing the EM simulations, we demonstrated that the loss can be further reduced using lower loss underfill materials [40]. Therefore, the important considerations of underfill materials are low loss tangent, good thermo-mechanical properties and good process compatibility. BCB is a good candidate as an underfill material. Table 4.1 summaries the material properties of conventional epoxy resin and BCB. BCB is designed for high frequency and low-k applications. It has been used for device passivation, interlayer dielectrics, and stress buffer layer. In general, BCB has a lower loss tangent than epoxy resin, making it very promising for MMW applications. The moisture uptake is also an important concern because moisture inside the materials can increase the dielectric loss at high frequencies [58, 59, 70].

在文檔中應用於毫微米波段高電子遷移率電晶體之覆晶封裝研究 (頁 38-0)