Chapter 5 Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility
5.5 Performance Characterization of the Packaged Device
To demonstrate the capability of the proposed technology for device application, an In0.6Ga0.4As mHEMT device with 150 nm gate length was flip-chip-assembled on the RO3210 organic substrate for performance evaluation. Note that the high-impedance transmission lines used to compensate for the capacitive impedance were included in the patterns on the RO3210 organic substrate to connect the gate and drain of the device. Figure 5.13 shows the measured DC characteristics where the gm
and IDS are plotted as functions of VDS at various VG levels. Similar performance characteristics were obtained for the flip-chip-packaged device. The RF performance was characterized using an on-wafer probing system with a vector network analyzer up to 110 GHz. Figure 5.14 shows the measured S21 against frequency up to 110 GHz for the bare die, flip-chip-packaged device without the underfill, and flip-chip-packaged device with the underfill. All the devices were biased at peak gm
71
occurrence with the input and output terminated by a 50 load. A degradation less than 2 dB was observed for the flip-chip-packaged device with the underfill compared with the bare die over the entire frequency range of interest. The effect of the compensation through high-impedance lines was evidenced by the minor degradation observed for frequencies above 60 GHz. In this aspect, the proposed FCOB approach showed a certain competitive edge over the conventional approach. In ref. 68, a Ka-band LNA MMIC chip was firstly packaged into a ceramic-based QFN package and then integrated into an RO4003C PCB. A gain degradation of 4.5 dB at 40 GHz compared with the bare die case was presented. Finally, the NFmin was measured and is plotted in Fig. 5.15. As is shown, the flip-chip-packaged device with the underfill exhibited an NFmin of 3 dB with an associated gain of 6 dB at 62 GHz, indicating promising results of the proposed low-cost FCOB technology for applications in the W-band.
5.6 Summary
In this chapter, we successfully demonstrated the FCOB technology for applications in the W-band at very low cost. The main breakthrough for the proposed technology lies in the fact that commercially available organic substrates were used as the carriers instead of conventional ceramic-based substrates. Design optimization was performed on the layout patterns of the RO3210 organic substrate through electromagnetic simulations, which also took into account the change in impedance due to the existence of the epoxy-based underfill for reliability improvement.
High-impedance lines were introduced into the structure on the RO3210 organic
72
substrate to compensate for the capacitive impedance and thus achieved good transmission properties when the 50 transmission line was flip-chip-assembled. The In0.6Ga0.4As mHEMT device was packaged and characterized with the optimized structure design. The measured DC and RF performance characteristics of the assembled mHEMT using the proposed low-cost FCOB technology showed very promising features, indicating that this technology can be used for applications up to the W-band.
Degradations in RF performance were observed due to the stress from the CTE mismatch between the materials during the bonding process. Higher parasitic levels of the bump interconnections have been observed through the extraction of the equivalent circuit for the case of higher bonding temperature. Such increase is related to the higher induced stress level during the bonding process, which leads to the degradation in RF performance.
73
Fig. 5.1 (a) Schematic and (b) cross-sectional views of the flip-chip interconnect structure
74
Fig. 5.2 In-house fabrication of FCOB structure on RO 3210 polymer substrate.
75 (a)
(b)
Fig. 5.3 SEM images of the low-cost RO 3210 organic substrate (a) before and (b) after CMP lapping process.
76
77
Fig. 5.5 (a) Measured S-parameter of the common flip-chip interconnect structure and (b) Smith chart of the corresponding S11 results.
78
79
0 20 40 60 80 100
-40 -30 -20 -10 0
Insertion loss (dB)
Return loss (dB)
Frequency (GHz)
Flip-chip structure with compensation With underfill
Without underfill
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 5.7 Measured S-parameter results of the optimized flip-chip interconnect structure with and without underfill.
80
(a)
(b)
Fig. 5.8 Measured drain current and DC transconductance as functions of gate bias at VDS = 0.5 V of the flip-chip-packaged device under different bonding conditions, (a) with high bonding temperature and (b) with low bonding temperature, with those of bare dies included for comparison.
81
Fig. 5.9 Measured MSG/MAG as a function of frequency for the cases of bare die, flip-chip-packaged device with high bonding temperature, and flip-chip-packaged device with low bonding temperature.
82
Fig. 5.10 Illustration of induced mechanical stress during bonding process with different bonding temperatures.
Fig. 5.11 The corresponding equivalent circuit model of the bump interconnect.
83
Fig. 5.12 Measured and modeled S parameters of the complete structure in Fig. 6 at high bonding temperature.
84 mHEMT device, packaged device, and packaged device with underfill.
85
1 10 100
0 2 4 6 8 10 12
S-p arameter (dB)
Frequency (GHz)
In0.6Ga
0.4As mHEMT
Lg = 150 nm; VDS= 0.8 V, VG=- 0.6 V Bare die
FC package
FC package with UF
Fig. 5.14 Comparison of insertion gain (S21) between the In0.6Ga0.4As MHEMT device, packaged device, and packaged device with underfill.
86
Fig. 5.15 Comparison of the minimum noise figure and associated gain at VDS = 0.8 V, VG = - 0.6 V between the In0.6Ga0.4As MHEMT device, packaged device, and packaged device with underfill.
87
Table 5.1 Material properties of the substrates commonly used for flip-chip packaging.
Table 5.2 Bonding conditions at high and low substrate bonding temperatures.
Conditions Chip temp.
Table 5.3 Extracted parasitic values at high and low bonding temperatures.
Conditions R1
Material Dielectric constant (at 10 GHz)
88
Chapter 6
Conclusions
This dissertation demonstrates the applicability of flip-chip interconnection and structure for millimeter-wave applications. The in-house flip-chip process, including the substrate fabrication and flip-chip bonding, was developed. From the optimized design of the flip-chip structure using EM simulation, the flip-chip interconnection between GaAs chip and Al2O3 substrate demonstrated very good RF performance.
The 80-nm gate In0.7Ga0.3As MHEMT devices had successfully flip-chip packaged on the Al2O3 substrate. After flip-chip packaging, the packaged devices exhibited almost the same performance as the bare chip in RF characteristics with minimum noise figure of 2.7 dB and device gain of 11 dB at 60 GHz, which evidenced that the proposed flip-chip technology can be used for the millimeter-wave low noise applications. A two-stage gain block at 60 GHz was designed and fabricated using the MIC approach. This design included flip-chip packaged device and the matching circuits on the same carrier. The measured signal gain was 9 dB at 60 GHz.
The performance proved the applicability of the MIC design for cost-effective solution and seamless integration of the device into the circuit at 60 GHz.
To improve the reliability of the flip-chip interconnection, BCB material with lower dielectric loss was injected into the flip-chip structures using the no-flow underfill process. The package with BCB underfill showed the insertion loss of better than 0.6 dB and a return loss of 18 dB up to 100 GHz. The use of BCB exhibited lower RF loss than epoxy underfill. Besides, the flip-chip with BCB injection had
89
passed 1000 cycles of thermal cycling test. After 1000 cycles of thermal cycling test, the flip-chip package with BCB unerfill still showed good shear force resistance against the thermal stress from the CTE mismatch inside the flip-chip structure. From the RF performance and mechanical test results, BCB material demonstrates great potential as the underfill material for flip-chip packaging up to millimeter-wave applications.
The production cost of the flip-chip packing structure is also an important issue.
Hence, the FCOB technology was experimented on low-cost polymer substrate by passing chip-level package. The commercially available organic substrate RO 3210 was used as the flip-chip carriers instead of the conventional ceramic substrates. The high-impedance lines before the flip-chip transition were introduced on the substrate to compensate the capacitive impedance and thus achieved characteristic impendence to 50 around the flip-chip transition. The packaged In6Ga0.4As mHEMT device using the proposed low-cost FCOB technology showed only small gain and NF degradations, demonstrating that this technology can be used for millimeter-wave applications.
To further investigate the mechanism causing the RF degradation, the equivalent circuit of the bump interconnection was constructed through the extraction of the S-parameter measurement. The thermal stress from the CTE mismatch between the materials of the flip-chip structure was observed during the bonding process. Higher bonding temperature induced the higher parasitic levels of the bump interconnections as evidenced through the extraction of the equivalent circuit. The increase in the parasitic levels should be the main reason resulting in the degradation of the RF performance of the flip-chip structure on RO 3210 polymer substrate.
90 References
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98
個人簡歷(CURRICULUM VITAE)
姓名：王景德 性別：男
生日：1983 年 11 月 6 日 籍貫：台北市
學歷：
國立中興大學材料科學與工程學系學士
（2002 年 9 月－2006 年 6 月）
國立交通大學材料科學與工程學所碩士 (博士班直升)
（2006 年 9 月－2007 年 6 月）
國立交通大學材料科學與工程學所博士
國立交通大學材料科學與工程學所博士