Summary - The Fabrication Process of the Flip-Chip Structure

Chapter 2 The Fabrication Process of the Flip-Chip Structure

3.5 Summary

The in-house fabrication of the flip-chip package of 80-nm gate In_0.7Ga_0.3As MHEMT device on Al₂O₃ substrate was presented. After flip-chip packaging, the device showed high I_DS = 435 mA/mm at V_DS= 1.5 V, and high g_m= 930 mS/mm at V_DS= 1.5 V, which is almost the same as the bare chip performance. The packaged devices also showed very small change in RF characteristics with NF_minof 2.7 dB and Ga of 11 dB at 60 GHz after packaging. The flip-chip packaged low noise In0.7Ga0.3As MHEMT device exhibited superior DC and RF performance, demonstrating the feasibility of using the proposed flip-chip technology for MMWs low noise applications.

To demonstrate the applicability of device using MICs design for V-band applications, a two-stage gain block at 60 GHz was designed and realized using a simple fabrication process. A 150 nm gate In0.6Ga0.4As mHEMT device was flip-chip packaged on an Al2O3 substrate. The small signal gain was measured to be 9 dB at 60 GHz with only 20 mW DC power consumption. The superior performance proved the applicability of such technology as a cost-effective solution for 60 GHz applications.

Fig. 3.1 Epitaxial layer structure of the In0.7Ga0.3As high electron mobility transistors

(HEMTs)

Fig. 3.2 (a) Image of the in-house fabricated 80-nm gate In_0.7Ga_0.3As MHEMT device,

(b) The SEM image of the electroplated micro Au bumps (c) The schematic of the

flip-chip packaged structure (d) Image of the flip-chip packaged In_0.7Ga_0.3As

MHEMT device on Al₂O₃ substrate.

(a)

(b)

(c)

(d)

Fig. 3.3 In-house fabrication flow of the alumina (Al2O3) substrate for flip-chip packaging

structure

0.0 0.3 0.6 0.9 1.2 1.5

0 100 200 300 400 500

D rai n C urrent I

(m A /mm )

Drain-source Voltage V_DS (V)

In0.7Ga

0.3As HEMTs Lg = 80 nm; V

G -0.6 ~ 0.2 V Before Flip-chip After Flip-chip

Fig. 3.4 Comparison of drain-source current (IDS) versus drain-source voltage (VDS) curves

with various gate voltages (VG) of In0.7Ga0.3As MHEMT devices with and without flip-chip

packaging.

Fig. 3.5 Comparison of drain current density (IDS) and transconductance (gm) as a function of

gate-source voltage (VGS) at VDS = 1.3V for In0.7Ga0.3As MHEMT devices with and without

flip-chip packaging.

0 10 20 30 40 50 60

-5 0 5 10 15 20

S

₂₁

S-Parameter (dB)

Frequency (GHz)

In0.7Ga

0.3As; Lg = 80 nm V_DS = 1.3 V; V_G = 0 V

Before Flip-chip After Flip-chip

Fig. 3.6 Comparison of insertion gain (S21) and reflection loss (S11) for In0.7Ga0.3As MHEMT

devices with and without flip-chip packaging.

1 10

0 1 2 3 4 5 6

40 30 20

In0.7Ga

0.3As; Lg = 80 nm VDS= 1.0 V

Frequency = 54 GHz

N o ise Figu re (d B )

DC Power Consumption (mW)

Fig. 3.7 The minimum noise figure with different DC Power consumptions at VDS = 1 V for

In0.7Ga0.3As MHEMT devices before flip-chip packaging

-0.1 V for In0.7Ga0.3As MHEMT devices with and without flip-chip packaging.

Fig. 3.9 Circuit diagram of the two-stage gain block designed at 60 GHz.

Fig. 3.10 Measured S-parameters of the fabricated gain block biased at VDS = 0.5 V and VGS = 0.4 V.

Chapter 4 Investigation of the Flip-chip Package with BCB Underfill for W-band Applications

Flip-chip package is promising for MMWs applications. However, the CTE mismatch between the chip and the substrate generates thermal stresses that fracture the flip-chip structure. The use of underfills with low dielectric loss is essential to improve the mechanical strength and reliability of the flip-chip package. BCB (Benzocyclobutene) was used in this study as the underfill material for the flip-chip structure using the no-flow process. The flip-chip structure with BCB injection provides good RF performance with a S₁₁ of better than 18 dB and an S₂₁of 0.6 dB up to 100 GHz. Furthermore, thermal cycle and shear force tests showed that the underfill injection can significantly improve the reliability of a flip-chip package.

4.1 Background and Motivations

Wireless communication and imaging systems at MMW and sub-MMW frequencies are gaining increasing attention. Packages with good electrical performance, decent mechanical reliability and low cost are crucial for high frequency applications. Flip-chip interconnects are considered as a promising interconnect technology due to several reasons [31,55]. Compared with conventional wire-bonding technology, flip-chip has much shorter interconnects, significantly reducing the parasitic effects at MMW frequencies [56]. However, the reliability of flip-chip

packaging is critical due to the thermal mechanical stresses from CTE mismatch of substrate and chip CTE [38,57]. Many previous studies have investigated the underfill effect in a flip-chip structure [23,40,48]. Kusamitsu et al. demonstrated LNA flip-chip bonded Al₂O₃ with an epoxy-based underfill with response shifted in frequency due to the underfill injection [23]. Feng et al. presented increase in the fatigue life with only a small additional loss of flip-chip assemblies [38]. Improvement in the reliability with small loss of flip-chip structure on polymer substrate has also been achieved in [49].

Conventional epoxy-based underfill has a high dielectric loss tangent which induces extra signal dissipation and degrades RF performance. Previously, by performing the EM simulations, we demonstrated that the loss can be further reduced using lower loss underfill materials [40]. Therefore, the important considerations of underfill materials are low loss tangent, good thermo-mechanical properties and good process compatibility. BCB is a good candidate as an underfill material. Table 4.1 summaries the material properties of conventional epoxy resin and BCB. BCB is designed for high frequency and low-k applications. It has been used for device passivation, interlayer dielectrics, and stress buffer layer. In general, BCB has a lower loss tangent than epoxy resin, making it very promising for MMW applications. The moisture uptake is also an important concern because moisture inside the materials can increase the dielectric loss at high frequencies [58, 59, 70].

4.2 Fabrication and Flip-chip Package Process

In-house flip-chip interconnect structure with BCB underfill was performed in this study. The fabrication processes of the GaAs thru-line chip and alumina (Al₂O₃) substrate have been described in Chapter 2. Figure 4.1 (a) shows a schematic of the flip-chip structure. The total signal transmission path was 3 mm, including CPW on the Al₂O₃ substrate, CPW on the GaAs chip, and two flip-chip transitions. An optimized no-flow underfill process, which will be described as follows, was applied to fill BCB into the flip-chip structures. The characteristic impedance (Z₀) of the CPW transmission line on the GaAs chip and the Al₂O₃ substrate was designed to be 50 Ω. The underfill (r>1) injection changes the effective dielectric constant and results in an impedance mismatch which degrades the chip performance. To reduce the impact of the underfill, the CPW transmission line on GaAs was designed to achieve an impendence matching of 50 Ω. Compensation designs, such as ground pad shrinking and high impendence line, were also adopted on the substrate transmission line to compensate for the parasitic capacitance of the flip-chip interconnects as shown by Fig. 4.2. After implementing matching designs, the RF performance was evaluated and is presented in the next section.

Conventionally, a capillary underfill process is used to inject epoxy resin into the flip-chip structure. Unfortunately, liquid BCB cannot easily flow into the gap between the chip and substrate using capillary force. To solve this issue, the no-flow underfill process was proposed as shown in Fig. 4.3. Liquid BCB was first deposited on the substrate. Then the substrate was heated to cause BCB to flow. The heating conditions, such as the heating time and temperature, were optimized to enhance the BCB flow.

Finally, the chip and the substrate were flip-chip bonded by using the Au-to-Au thermo-compression method. An additional curing at 250 ^oC for 2 hours was performed to facilitate cross-linking of the BCB polymer chains. Figure 4.1 (b) shows a cross-sectional SEM image of the flip-chip structure with BCB underfill. The BCB was successfully injected into the flip-chip interconnect structure using the no-flow underfill process.

4.3 Measured Results of the Flip-chip Packaging Structure with Underfill Injection

The losses in the flip-chip interconnects with underfill include mismatch loss and real loss. Mismatch loss is mainly due to the dielectric constant change from the underfill. To reduce the impact from the underfill, the dimensions of the chip transmission line were modified, and compensation designs on the substrate transmission line were adopted. Figure 4.4 shows comparison of the flip-chip interconnects with and without underfill. The flip-chip with BCB has lower loss than the flip-chip with epoxy at high frequencies. The S₁₁ and S₂₁ of the flip-chip structure with BCB were better than 18 dB and 0.6 dB, respectively, from DC to 100 GHz. As for the case of flip-chip sample without underfill, an S21 of 0.66 dB was observed.

The corresponding contribution to the overall S₂₁ at 90 GHz were further extracted to be 0.14 dB from the CPW trace on GaAs substrate, 0.26 dB from CPW on Al2O3, and 0.26 dB from the transition. It was then concluded that the optimized design can effectively reduce the mismatch loss.

The real loss includes metal loss (LM), dielectric loss, and radiation loss. The

radiation loss can be neglected because it is very small. The dielectric loss is composed of chip loss (L_C), substrate loss (L_S) and underfill loss (L_UF). After the underfill injection, the extra dielectric loss induces and degrades the transmission properties. Hence, to investigate the influence of underfill injection, the loss factor is calculated using (1) [60]:

2 2

Loss Factor = 1S11 S21 (1)

The underfill loss can be calculated by subtracting the loss of the flip-chip without underfill from the loss of flip-chip with underfill. The losses of chip, substrate, and metal in the flip-chip structure are also extracted by electromagnetic simulation for comparison. Figure 4.5 shows the comparison of the loss factors between the metal, chip, substrate, epoxy, and BCB. As can be seen, the major losses are metal loss and underfill loss. The epoxy loss is near the metal loss. The BCB loss is lower than epoxy loss. The flip-chip package with BCB shows a lower insertion loss of 0.11 dB/mm compared to the epoxy loss of 0.24 dB/mm at 100 GHz. These results demonstrate that underfill materials with lower dielectric loss tangents, such as BCB, can effectively reduce the RF loss of the flip-chip assembly caused by the underfill.

Given that fact that the metal loss contributed the most to the total loss as shown in Fig. 4.5, it is worth mentioning that for Si Complementary Metal–oxide–

semiconductor (CMOS) process where much narrower traces are encountered, the improvement in overall loss due to BCB might not be as pronounced since the metal loss are much higher for such cases.

4.4 Reliability Test Results of the Flip-chip Packaging Structure with Underfill Injection

The flip-chip interconnect structure with BCB underfill has demonstrated excellent RF performance as described in previous section. However, reliability is also of great concern to the industry. Thermal property analysis was performed by thermal cycling with temperature changes from -55 ^OC to 125 ^OC with a dwell time of 15 minutes (the specifications of the JEDEC standard) [61]. During the thermal cycling test, the DC resistance of the transmission line was measured after every 200 cycles as shown in Fig. 4.6. The flip-chip structure with BCB passes a 1000 cycle thermal cycling test. The contact resistance showed little change and no samples failed after 1000 cycles. Table. 4.2 shows the shear force test results before and after 1000 cycle thermal cycling tests. The results revealed that the flip-chip interconnects without underfill fractured at a shear force of 173 g, which is not acceptable for commercial applications. After BCB injection, the shear force for failure was effectively increased to 1305 g. The shear force of the flip-chip structure degraded after thermal cycling due to the thermal stresses induced by CTE mismatch. The flip-chip structure without underfill has a lower shear force resistance and the mechanical reliability was seriously degraded. However, the shear force resistance was enhanced because the stress was redistributed by the underfill. BCB injection into flip-chip structures improves the reliability and excellent RF performance is retained after the packaging process.

4.5 Summary

BCB was successfully injected into the flip-chip structures using the no-flow underfill process. The package with BCB underfill showed better RF performance with an insertion loss of better than 0.6 dB and a return loss of 18 dB up to 100 GHz, in addition to lower dielectric loss. Furthermore, thermal cycling and shear force testing showed that BCB injection could effectively improve the reliability of the flip-chip interconnect structure. Excellent RF performance with improved reliability demonstrates that BCB is a good underfill material for MMW package applications.

Table 4.1 Material properties of underfills, chip and substrate

Dielectric Materials

Dielectric Constant

Dielectric Loss CTE (ppm/℃) Moisture Uptake (wt％)

(a)

(b)

Fig. 4.1 (a) A schematic and (b) an SEM image of the cross section of the flip-chip structure with BCB underfill injection.

Fig. 4.2 The design parameters for the flip-chip structure with BCB injection.

Fig. 4.3 The no-flow underfill process flow for flip-chip structure

Fig. 4.4 Measured S-parameters of the flip-chip interconnects without UF and with BCB or epoxy underfill injection.

Fig. 4.5 LM(Gold), LC(GaAs) and LS(Al2O3) of the flip-chip interconnect structure as extracted from EM simulation; the LBCB and LEpoxy as extracted from the measurement for comparison.

Fig. 4.5 Thermal cycling test results of the flip-chip interconnect with and without BCB underfill injection.

Table 4.2 Shear force test results

Before TCT After TCT (1000 cycle)

Without underfill 173 g 19 g

With BCB 1305 g 1244 g

Chapter 5 Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-cost Organic Substrate

The rapid growth of high-frequency wireless communication demands high-performance packaging structures at low cost. A flip-chip interconnect is one of the most promising technologies owing to its low parasitic effect and high performance at high frequencies. In this chapter, the in-house fabricated In0.6Ga0.4As Metamorphic High Electron Mobility Transistor (mHEMT) device was flip-chip-assembled using a commercially available low-cost organic substrate. The packaged device with the optimal flip-chip structure exhibited almost similar DC and RF results to the bare die. An exopy-based underfill was applied to the improvement of reliability with almost no degradation of the electrical characteristics. Measurement results revealed that the proposed packaging structure maintained NFmin of 3 dB with 6 dB of associated gain at 62 GHz. Such a superior performance after flip-chip packaging demonstrates the feasibility of the proposed low-cost organic substrate for commercial high-frequency applications up to the W-band.

Besides, the impact of bonding temperature on the device performance was also experimentally investigated. While the DC performance was not as sensitive, serious degradation in RF performance was observed at high bonding temperature. Such degradation was mainly due to the thermal-mechanical stress resulting from the mismatch of CTE between the GaAs chip and the polymer substrate. Quantitative

assessment was also performed through equivalent circuit extraction from S-parameter measurements.

5.1 Background and Motivations

The demand for communication systems at frequencies up to the W-band has been growing rapidly in recent years because such systems may provide high data transmission rates [62,63]. The high-frequency performance of these systems mainly depends on the device characteristics and packaging structure. In terms of the device technology, In-rich In_xGa_1-xAs/In_xAl_1-xAs-based mHEMTs are gaining increasing popularity owing to the high electron mobility and saturation velocity of the InGaAs materials, which in turn delivers a lower NF with higher gain at high frequencies [41-44].

The packaging structure is also a key issue for practical implementation concerns.

Generally, such a structure should provide a reliable transmission path from chip to substrate and protect the device from external hazards, such as environmental effects, mechanical stress, and humidity [64]. Conventionally, the chip is assembled on ceramic-based substrates, such as Al₂O₃ [23], and then the ceramic-based modules are integrated into the systems made of PCB.

Despite of the major advantages provided by the flip-chip packaging, such as good thermal management, good mechanical stability, and high reliability [30,32,65], mounting ceramic-based substrates onto PCBs unavoidably introduces additional transitions in signal paths, which will induce extra parasitic effects to degrade the system performance. In addition, the approach also causes additional cost owing to

the transition from ceramic substrates to PCBs.

This work is performed to develop a low-cost yet robust FCOB technology for high-frequency applications up to the W-band. A commercially available PCB (RO3210 organic substrate from Rogers) was adopted for the study of the proposed technology. To further improve the reliability of the overall structure, an epoxy-based underfill, which can alleviate the stress on the bump transitions between the chips and the PCB [38,57,66], was applied. Possible performance degradations at high frequencies due to the inclusion of the underfill (though with low dielectric constant) were taken care of by the optimal design of the geometries on the RO3210 organic substrate through full-wave electromagnetic simulation. The optimal design of the layout patterns on the RO3210 organic substrate was verified by the measurement of flip-chip-bonded 50 Ω transmission lines.

5.2 Fabrication and Flip-chip Package Process

Both the GaAs substrate with 50  CPW transmission lines and the In_0.6Ga_0.4As mHEMT device with 150 nm gate length were flip-chip-assembled on the RO3210 organic substrate for performance characterization. The interconnect structure is shown in Fig. 5.1. The In0.6Ga0.4As mHEMT device with 150 nm gate length used in this study was fabricated using in-house process.

Figure 5.2 shows the in-house fabrication process of the FCOB structure on the RO 3210 polymer substrate. The commercial RO3210^TM PCB of 0.635 mm thickness from Rogers Corporation was used as the substrate material. Compared with the

conventional Al2O3 substrate commonly used for the flip-chip process, the RO3210 substrate exhibits great competitiveness in terms of the very low cost. For both electrical and mechanical performance improvements, chemical mechanical polishing (CMP) was first applied to reduce the surface roughness of the polymer substrate.

Figure 5.3 (a) shows the SEM image of the RO3210 organic substrate, which has a surface roughness of 3 m by using a P-10 Surface Profiler. In the beginning of the RO 3210 substrate process, the seed layers of Ti and Au metals were deposited by an E-gun evaporator with thicknesses of 500 and 1000 Å , respectively. The Ti layer was used as the adhesion layer between the Au circuit and the RO3210 organic substrate.

The CPW transmission line with a characteristic impedance of 50 Ω was patterned on the photoresist and gold-electroplated to a thickness of 3 m. To obtain good RF performance of the FCOB structure, the CPW transmission line with compensation design has been considered. Then, the thick photoresist from TOK Company was patterned for the Au bump electroplating. The height and diameter of the Au bumps are 20 m and 50 m, respectively.

After the chip and RO3210 organic substrate were fabricated, the flip-chip bonding process was performed by using M9 flip-chip bonder system. The chip was flip-chip-assembled on the RO3210 organic substrate by Au-to-Au thermal compression process with optimization bonding conditions, such as bonding temperature, bonding time, and bonding force.

5.3 Design and Optimization of the flip-chip packaging structure on RO 3210 polymer substrate

Prior to the assembly of active devices through the flip-chip bonding process, the high-frequency characteristics of the RO3210 organic substrate were investigated by the measurement of a 50  CPW transmission line. A 50  CPW transmission line designed on the RO3210 organic substrate with a line width of 50 m and a spacing of 27 m between the signal trace and the ground, and a length of 854 m was fabricated and measured. Figure 5.4 shows the measured results up to 110 GHz using an on-wafer probing system after load-reflection-reflection-match (LRRM) calibration. The simulated results using electromagnetic simulators [68] are also included. The measured S21 and simulated S21 match well with a difference of less than 0.7 dB up to 110 GHz. The measured return loss of the CPW thru line was below 20 dB up to 90 GHz. Generally, the organic substrate exhibited low S11 and S21 for

在文檔中應用於毫微米波段高電子遷移率電晶體之覆晶封裝研究 (頁 52-0)