Motivation

1.4.1 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying Ni-Silicidation in Gate Engineering, Source/Drain Engineering, and Channel Crystallization

. The output characteristics exhibit an anomalous current increase in the saturation regime, often called “kink” effect [1.64], [1.65] due to an analogy with silicon- on-insulator (SOI) devices [1.66]. This phenomenon can be attributed to the floating- body effect [1.67] and the avalanche multiplication enhanced by grain boundary-traps [1.68]. The avalanche multiplication is caused by the high drain electric field and the presence of grain boundaries and traps enhances the kink effect in poly-Si TFTs [1.68].

With increasing drain voltage, the added drain current enhances impact ionization and parasitic bipolar junction transistor (BJT) effect, which leads to a premature breakdown in return, particularly in n-channel TFTs [1.33]. Several structures such as lateral body terminal (LBT) [1.36], low-barrier body-contact (LBBC) [1.37], and Schottky body contact [1.38] have been reported in order to reduce the kink current.

Among these structures, Schottky barrier MOSFETs (SB-MOSFETs) are thought to have some advantages over conventional MOSFETs, such as the reduction of parasitic resistance and capacitance, and the immunity to the short channel [1.69], latch-up, or silicon-on- insulator floating-body effects [1.70].

In the floating-body thin-film devices, the improved parasitic BJT effect can be achieved by using deep salicidation and fully silicided source/drain structure [1.34], [1.35]. Due to low hole field-effect mobility, p-channel TFTs have lower on-state current compared with n-channel TFTs. Nevertheless, the p-channel TFTs have some advantages, such as low off-state leakage current, slight floating-body effect and kink effect, weak drain impact ionization and high hot carrier reliability. In addition, the

thin-channel poly-Si TFTs have the improved device characteristics such as small leakage current and suppressed floating-body effect compared with the thick-channel poly-Si TFTs [1.71]. Thin channel film also leads to increased source and drain parasitic resistance. The parasitic S/D resistances become increasingly a serious issue in the thin-channel poly-Si TFTs and SOI devices. Several methods such as self-aligned silicide, selective tungsten-clad and metal-replaced junction technology were proposed to reduce parasitic S/D resistance for thin-channel SOI devices and poly-Si TFTs [1.72]-[1.75]. Furthermore, silicided and metal gates have a higher capacitance than poly-Si gates due to the elimination of poly-Si depletion [1.76]. The field-effect mobility and on-state current can be improved by reducing parasitic S/D resistance and increasing gate capacitance [1.74], [1.75]. In the Chapter 2 and 3, application of Ni-salicidation for suppression of floating-body effect and parasitic BJT effect in poly-Si TFTs were demonstrated and investigated.

However, the application of poly-Si TFTs is mainly limited in low-temperature flat-panel display. Conventional poly-Si TFTs suffer from serious poor device characteristics and device-to-device variations resulted from the grain boundaries in the channel region. It is believed that electrical characteristics of the poly-Si TFTs can be improved if the poly-Si grain size can be enhanced and the number of grain boundaries in the channel can be reduced. Metal-Induced-Lateral-crystallization (MILC) technology has been studied in the past to achieve large and regular poly-Si grain from amorphous silicon [1.18]-[1.20]. In addition, vertical thin film transistors (VTFTs) are suitable for high density 3-D integration since their channel length are determined by the thicknesses of SiO₂ or poly-Si films instead of the photolithographic limitation. Many works had been devoted to developing and studying VTFTs [1.77], [1.78]. In Chapter 4, application of Ni-silicide induced lateral crystallization for novel symmetric vertical channel poly-Si TFTs were investigated.

1.4.2 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying Germanium in Gate Engineering and Nonvolatile Memories

The large OFF-state leakage current and device instability of poly-Si TFTs are hindrances to the high-performance and high reliability circuit applications. It is well known that the dominant mechanism of the OFF-state leakage current is the field emission via grain boundary traps due to a high electric field in the drain depletion region. The leakage current is increased with increasing gate and drain voltages which enhance the field emission via grain boundary traps in the depletion region near the drain [1.79], [1.80]. In order to increase the reliability and reduce the leakage current, poly-Si TFTs with offset gated, lightly doped drain (LDD), gate-overlapped LDD, floating gate spacer, air cavities, or field-induced drain (FID) structures have been suggested to reduce the electric field near the drain [1.23]-[1.29]. In Chapter 5, application of novel self-aligned Si / Ge T-gate for suppression of OFF-state leakage current in poly-Si TFTs were proposed and demonstrated.

In addition, nanocrystal floating-gate memories offer a number of potential advantages over FLASH devices, including improved scalability, retention, and cyclability, as well as lower voltage operation. In these devices the floating gate is composed of discrete, electrically-isolated particles (rather than a continuous film as in conventional FLASH) [1.81]. Recently, nonvolatile memory devices using Ge or Si nanocrystals (Ge-NCs or Si-NCs) as floating gate (FG) have been widely studied because of its excellent memory performance and high scalability. Ge has smaller bandgap and similar electron affinity compared with Si. Nonvolatile memory devices using Ge-NCs instead of Si-NCs have superior retention properties [1.39]. In addition, Ge/Si-NCs have been reported to possess superior charge retention capability than Ge or Si-NCs [1.82]. In Chapter 6, application of new Ge-NCs for poly-Si TFT

nonvolatile memories with low temperature annealing were proposed and studied.