應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究

全文

(1)國立交通大學電子工程學系電子研究所. 博士論文應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究 Applications of Ni-Silicidation and Germanium for Novel Structures of Polycrystalline Silicon Thin-film Transistors 研究生：郭柏儀指導教授：雷添福教授. 中華民國九十六年九月.

(2) 應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究 Applications of Ni-Silicidation and Germanium for Novel Structures of Polycrystalline Silicon Thin-film Transistors. 研究生：郭柏儀. Student：Po-Yi Kuo. 指導教授：雷添福博士. Advisor：Dr. Tan-Fu Lei. 國立交通大學電子工程學系. 電子研究所. 博士論文 A Dissertation Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering September 2007 Hsinchu, Taiwan, Republic of China. 中華民國九十六年九月.

(3) 應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究. 學生：學生：郭柏儀. 指導教授：指導教授：雷添福博士. 國立交通大學電子工程學系電子研究所博士班. 摘. 要. 此論文製作多種高效能新結構複晶矽薄膜電晶體，研究鎳矽化物與鍺在閘極工程、源極/汲極工程、通道結晶與非揮發記憶體上之應用。首先我們提出一種新自我對準蕭特基(Schottky)位能障源極與歐姆接觸 (ohmic contact)基極結構(SSOB)，我們使用不對稱 p 型接面源極 / n 型接面汲極結構與自我對準鎳矽化物來形成蕭特基位能障源極與歐姆接觸基極結構，此結構能有效抑制複晶矽薄膜電晶體浮接基體效應(Floating-Body Effect)。和傳統複晶矽薄膜電晶體相比，實驗結果顯示此蕭特基位能障源極與歐姆接觸基極結構之複晶矽薄膜電晶體(SSOB-TFTs)具有較高的輸出阻抗(output resistance)、較少的臨界電壓變化 (threshold voltage variation) 、改善的次臨界特性 (subthreshold characteristics)和較大的崩潰電壓(breakdown voltage)。然後我們首次成功發展出具完全自我對準鎳矽化物(fully Ni-salicided)於源極/汲極和閘極之 n 型通道與 p 型通道複晶矽薄膜電晶體(FSA-TFTs)，和傳統複晶矽薄膜電晶體相比，實驗結果顯示此完全自我對準鎳矽化物(fully Ni-salicided)於源極/汲極和閘極之 n 型通道與 p 型通道複晶矽薄膜電晶體 (FSA-TFTs) 具有較高的導通 / 關閉電流比 (Ion/Ioff I.

(4) current ratio)、改善的次臨界特性(subthreshold characteristics)、較少的臨界電壓下降(threshold voltage roll-off)、較低的源極/汲極寄生電阻(parasitic S/D resistance)、較高的閘極電容和較大的場效應電子遷移率(field-effect mobility)。另外我們亦研究發展出新穎鎳矽化物引發橫向結晶技術於對稱式垂直通道複晶矽薄膜電晶體(NSILC-VTFTs)，兩階段的鎳矽化物引發橫向結晶技術(NSILC)包含第一階段: 爐管 500oC 12 小時退火和第二階段的 700oC 60 秒快速熱退火(RTA)，此新穎結晶技術可以加強結晶大小、改善結晶品質並抑制鎳金屬的累積污染。元件製作完全無經過氨電漿後處理，此新穎鎳矽化物引發橫向結晶技術於對稱式垂直通道複晶矽薄膜電晶體(NSILC-VTFTs)具有陡峭的次臨界擺動(subthreshold swing)和相當高的場效應電子遷移率(field-effect mobility)。接著我們首次成功發展製作出自我對準堆疊矽/鍺 T 型閘極結構之複晶矽薄膜電晶體(Si / Ge T-gate TFTs)，此新結構之閘極靠源極/汲極兩邊具有較厚之閘極氧化層，此設計能有效地降低汲極的垂直與橫向電場而不需要額外的光罩、輕摻雜汲極(lightly doped drain)、間隙壁(spacer)或副閘極(sub-gate)等製程和結構。和傳統複晶矽薄膜電晶體相比，實驗結果顯示此堆疊矽/鍺 T 型閘極結構之複晶矽薄膜電晶體(Si / Ge T-gate TFTs)具有較低的關閉電流(off-state leakage current)、較高的導通 / 關閉電流比 (Ion/Ioff current ratio) 與較飽和的輸出特性 (output characteristics)。在論文的最後，我們成功發展製作出具鍺奈米微晶粒之非揮發複晶矽薄膜記憶體(poly-Si TFT nonvolatile Ge-NCs memories)，此鍺奈米微晶粒是利用低壓化學氣相沉積系統在 370°C 下直接沉積在氧化層上來完成。此外，我們應用適當的浮接基體效應(Floating-Body Effect)來提高寫入/抹除效率。實驗結果顯示此鍺奈米微晶粒之非揮發複晶矽薄膜記憶體 (poly-Si TFT nonvolatile Ge-NCs memories)具有高的寫入/抹除效率、長的電荷儲存持久性、低的閘極和汲極干擾與良好的寫入/抹除忍受力。. II.

(5) Applications of Ni-Silicidation and Germanium for Novel Structures of Polycrystalline Silicon Thin-film Transistors Student: Po-Yi Kuo. Advisor: Dr. Tan-Fu Lei. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University ABSTRACT In this thesis, applications of Ni-silicidation and Germanium in gate engineering, source/drain engineering, channel crystallization and nonvolatile memories for fabricating high performance new structures of polycrystalline silicon thin-film transistors (poly-Si TFTs) have been investigated. First, we have developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si TFTs. Experimental results show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. Second, the n-channel and p-channel fully Ni-self-aligned silicided (fully Ni-salicided) source/drain and gate poly-Si TFTs (n-channel and p-channel FSA-TFTs) have been successfully are successfully developed and fabricated for the first time. Experimental results show that the FSA-TFTs give increased Ion/Ioff current ratio, improved subthreshold characteristics, less threshold voltage roll-off, low parasitic III.

(6) S/D resistance, high gate capacitance and larger field-effect mobility compared with conventional TFTs. Next, the novel symmetric vertical channel poly-Si TFTs fabricated by Ni-silicide induced lateral crystallization technology (NSILC-VTFTs) are successfully developed and demonstrated. Two step NSILC (1th step: 500oC, 12hr and 2th step: RTA 700oC, 60-sec; without NH3 plasma treatment) has been introduced to enhance the grain size and improve the crystal integrity through secondary crystallization. The NSILC-VTFTs after two step NSILC treatment show a steep subthreshold swing (S.S.) of 180 mV / dec and max field effect mobility μ= 553 cm2 / V-s with Leff = 0.6µm and gate oxide = 500Å. Then, we have successfully developed and fabricated the self-aligned Si / Ge T-gate poly-Si thin-film transistors (Si / Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain (LDD), spacer, or sub-gate bias. Experimental results show that the Si / Ge T-gate TFTs have low off-state leakage currents, improved Ion / Ioff current ratio, and more saturated output characteristics compared with conventional TFTs. Finally, we have successfully developed and fabricated the poly-Si thin-film transistor (poly-Si TFT) nonvolatile Ge nanocrystals (Ge-NCs) memories for the first time. The pure Ge-NCs trapping layer was directly deposited by low-pressure chemical vapor deposition (LPCVD) at 370°C. In addition, a programming/erasing scheme adopting appropriate floating body effect was proposed. Results show that the new poly-Si TFT nonvolatile Ge-NCs memories have high programming/erasing efficiency, long charge retention time, less gate and drain disturbance, and good endurance characteristics. IV.

(7) 誌謝首先我要感謝我的指導教授雷添福博士並致上最高的敬意，感謝老師在研究與學業上給我的指導和鼓勵，老師的包容寬大、泱泱風範、學術成就是我學習的模範，在這五年的博士生涯中，讓我學習到待人處世與研究的態度，對於學生的諄諄教誨我會銘記在心。此外，我要感謝趙天生教授，老師的無私奉獻、致力研究、不爭功利的風骨，實在非常值得效法，有老師的開放創新，讓我能發揮我的想像力與創造力，有老師的明燈指引，讓我的研究找出屬於自己的方向。感謝曾經帶過我指導過我的學長姊，冉曉雯、彭杜仁、李明鎮、俞正明、李介文、張子云、王哲麒、葉冠麟、王夢凡、呂嘉裕、林家彬、李耀仁，從你們身上我學到做實驗的方法和態度。此外感謝我曾經帶過的學弟妹，曾健旭、王仁杰、黃彥學、黃竣祥、謝佩珊、周明宏、劉美君和賴久騰，和我共同度過這段同甘共苦的歲月。也感謝實驗室裡曾經一起研究一起歡笑一起打拼的夥伴，謝明山、游信強、王獻德、楊紹明、羅文政、林育賢、吳家豪、吳偉成、張宗憲、賴冠宏、陳百宏、呂宗宜、馬鳴汶、吳偉成、陳志仰、張家文、黃俊嘉以及學弟學妹們、李美錡、謝德慶、林育信、賴久盟、謝松齡、江國誠、林余俊、羅韋翔、范嘉豪、譚祥梅、于慶潭、郭雅欣、李伯浩、楊宗元、徐梓翔、徐源俊、桑任逸、周棟煥、彭武欽、高國興、呂宜憲、賴妍心、楊宗諭、邱德馨、王統億、洪錦石、張哲綸、余明爵、羅文呈、王智盟、王冠迪、江宗育、顏榮嘉、林威良、吳翊鴻、張子恆、張婷，有你們的陪伴、幫忙和討論，使我研究更順利，生活充滿歡樂。感謝一路走來始終陪伴在我身旁的好朋友，顏碩廷、陳建豪、陳漢譽、鄧至剛、林宏年，以及多年好友蔡猛麒、傅士卿、潘祥斌、劉鶴軒、李翔任、劉力仁、王東鉑，在研究上與生活上有你們的幫忙和鼓勵，使我得到繼續向前進的推力。感謝曾經在生活上實驗上幫助過我的朋友，若沒有你們的幫忙，實驗就不能順利完成。最後感謝我的父母感謝他們在我這段求學時間無私的犧牲和奉獻，你們對我的照顧與關懷是我低潮時的助力，沒有你們就不能完成此論文，我今天的成就完全是屬於你們的。另外感謝我的妹妹，有妳的互相扶持，生命才是圓滿。 V.

(8) Contents Abstract (in Chinese)….……………………………………………………………I Abstract (in English)……………………………………………………………….III Acknowledgements (in Chinese)..…………………………………………….……V Contents …………………………………………………………………………….VI Table Lists.………………………..……………………............................................X Figure Captions……………………………………………………………………XII. Chapter 1 Introduction ………..…………………………………………………….1 1.1 Overview of Polycrystalline Silicon Thin-Film Transistors…………………..1 1.2 Applications of Metal-Silicidation in Poly-Si TFTs…………………………..4 1.3 Applications of Germanium in Poly-Si TFTs…………………………………5 1.4 Motivation ……………….……………………………………………..……..7 1.4.1 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying. Ni-Silicidation. in. Gate. Engineering,. Source/Drain. Engineering, and Channel Crystallization……………………………..7 1.4.2 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying. Germanium. in. Gate. Engineering. and. Nonvolatile. Memories………………………………………………………………9 1.5 Thesis Organization …………………….……………………………………10. Chapter 2 Suppression of the Floating-Body Effect in Poly-Si Thin-Film Transistors with Self-Aligned Schottky Barrier Source and Ohmic Body Contact Structure………………………………………………13. VI.

(9) 2.1 Introduction …………………………….…………………………………….13 2.2 Experiment ….....………..…………………...…………………………….....14 2.3 Results and Discussion……………………………………………………….15 2.3.1 n+ Drain - p+ Source Poly-Si TFTs Structure…………………………...16 2.3.2 p+ Drain - n+ Source Poly-Si TFTs Structure…………………………...17 2.3.3 SSOB-TFTs at Different Negative Source Voltage…………………….18 2.4 Summary………………………………………………….……………….…18. Chapter 3 Characteristics of n-Channel and p-Channel Fully Ni-Self-Aligned Silicided S/D and Gate Poly-Si Thin-Film Transistors........................28 3.1 Introduction …………………………….………………………………...…..28 3.2 Experiment ….....………..…………………...…………………………….....29 3.3 Results and Discussion……………………………………………………….30 3.3.1 Fully Ni-Salicidation Process..…………………………………………30 3.3.2 n-Channel FSA-TFTs……………….………………………………….31 3.3.3 p-Channel FSA-TFTs………………....….………...……..……………35 3.4 Summary………………………………………………….……………….…36. Chapter 4 Novel Symmetric Vertical n-Channel Poly-Si Thin-Film Transistors Fabricated. by. Ni-Silicide. Induced. Lateral. Crystallization. Technology……………………………………………………………...54 4.1 Introduction …………………………….………………………………...…..54 4.2 Experiment ….....………..…………………...…………………………….....56 4.3 Results and Discussion……………………………………………………….57 4.3.1 Devices Structure and TEM Results……………………………………57 4.3.2 Ni Accumulation in Floating Region after MILC and NSILC VII.

(10) Processes……………………………………………………………..58 4.3.3 Comparison of NSILC-VTFTs, MICL-VTFTs, and Conventional TFTs...………………………………………………………………...59 4.3.4 NSILC-VTFTs with Constant Lmask and Different Wmask………………60 4.3.5 NSILC-VTFTs with Constant Wmask and Different Lmask……………...61 4.3.6 Comparison of NSILC-VTFTs and NSILC-VTFTs (RTA)…………….62 4.4 Summary………………………………………………….……………….…63. Chapter 5 Characteristics of Self-Aligned Si / Ge T-Gate Poly-Si Thin-Film Transistors with High ON/OFF Current Ratio...................................85 5.1 Introduction …………………………….………………………………...…..85 5.2 Device Structure Design and Simulation…………………………………….86 5.2.1 Si / Ge T-gate Structure Design………………………………………...86 5.2.2 Lateral Electric Field Simulation in Si / Ge T-gate TFTs………………87 5.3 Experiment ….....………..…………………...……………………………....88 5.4 Results and Discussion……………………………………………………….88 5.4.1 Cross-Sectional TEM microphotograph of Si / Ge T-gate TFTs……….88 5.4.2 Si / Ge T-gate TFTs with TEOS Passivation…………………………...89 5.4.3 Si / Ge T-gate TFTs with TEOS Passivation or SINX Passivation……..92 5.5 Summary………………………………………………….……………….…95. Chapter 6 Characteristics of Poly-Si Thin-Film Transistor Nonvolatile Ge Nanocrystals Memories with High Programming / Erasing Efficiency…………………………………………………………….111 6.1 Introduction …………………………….………………………………...…111 6.2 Experiment ….....………..…………………...……………………………...112 VIII.

(11) 6.3 Results and Discussion……………………………………………………...113 6.3.1 Formation of Ge-NCs Embedded in Oxide…………………………...113 6.3.2 Channel Hot Electron Injection Programming Mechanism in Poly-Si TFTs……………………………………………………...………….114 6.3.3 Programming and Erasing Characteristics of Poly-Si TFT Nonvolatile Ge-NCs Memories…………………………………………………….115 6.3.4 Gate and Drain Disturbance Characteristics of Poly-Si TFT Nonvolatile Ge-NCs Memories…………………………………………………….118 6.3.5 Data Retention and Rewrite Endurance Properties of Poly-Si TFT Nonvolatile Ge-NCs Memories……………………………………...119 6.4 Summary………………………………………………….………………...120. Chapter 7 Conclusions and Further Recommendations…...................................141 7.1 Conclusions…………………………………………………………………141 7.2 Further Recommendations………………………………………………….143. References………………………………………………………………………….145. Vita. Publication list. IX.

(12) Table Lists Chapter 4 Table 4.1. The split table of the devices. The NSILC-VTFTs and MILC-VTFTs were only crystallized by first step lateral crystallization (500°C for 12hr). The NSILC-VTFTs (RTA) were crystallized by first step lateral crystallization (500°C for 12hr) and second step RTA (700°C for 60sec). In order to investigate the impact of grain boundaries in the channel crystallized by NSILC or MILC processes, no further NH3 plasma. treatment. procedure. was. implemented. in. our. experiment…………………………………………………………...66 Table 4.2. The summary of measured devices parameters for NSILC-VTFTs, MILC- VTFTs, and conventional TFTs…………………………….74. Table 4.3. The Summary of measured devices parameters from NSILC-VTFTs with constant Lmask = 0.8µm and different Wmask. The effective channel length of NSILC-VTFTs is 0.6µm. The NSILC-VTFTs with Wmask / Lmask = 0.8µm / 0.8µm have the highest field effect mobility……………………………………………………………...76. Table 4.4. The summary of measured devices parameters from NSILC-VTFTs with constant Wmask = 0.8µm and different Lmask. The effective channel length of NSILC-VTFTs is 0.6µm.The NSILC-TFTs with Wmask / Lmask = 0.8µm / 0.8µm have the highest field effect mobility……………………………………………………………...81. Table 4.5. The summary of measured devices parameters from NSILC-VTFTs (RTA) with constant Wmask = 0.8µm and different Lmask. The effective channel length of NSILC-VTFTs (RTA) is 0.6µm. The NSILC-VTFTs (RTA) with Wmask / Lmask = 0.8µm / 0.8µm have the highest field effect mobility. The NSILC-VTFTs (RTA) with Wmask / Lmask = 0.8µm / 5µm have the largest Ion / Ioff current ratio……………………….84. X.

(13) Chapter 5 Table 5.1. The experimental split table of Si / Ge T-gate TFTs and conventional TFTs…………………………………………………………………97. Chapter 6 Table 6.1. The split table of the applied drain biases with different gate length and channel thickness in the program region. The applied drain voltage can be reduced with short gate length and thick channel thickness……………………………………………………………127. Table 6.2. The program efficiency of poly-Si TFT nonvolatile Ge nanocrystal memories in the program region. The program efficiency can be significantly enhanced with increased VD………………………….133. XI.

(14) Figure Captions Chapter 2 Fig. 2.1. The key processes of the SSOB-TFTs, (a) n+ drain-side implantation, (b) p+ body-contact implantation, (c) Ni-salicidation and Schottky barrier source formation, (d) The poly-Si TFTs with SSOB after contact and metallization processes…………………………………19. Fig. 2.2. The transfer characteristics of the n+ drain - p+ source poly-Si TFTs with channel thickness (a) 100nm and (b) 50nm before Ni salicidation. When gate voltage is increased, the drain current is. limited by the p+ source……………………………………………..20 Fig. 2.3. The transfer characteristics of the conventional and the SSOB-TFTs with channel thickness (a) 100nm and (b) 50nm. The SSOB-TFTs give low leakage currents and improved subthreshold characteristics compared with conventional TFTs………………………………….21. Fig. 2.4. The output characteristics of the conventional and the SSOB-TFTs with channel thickness (a) 100nm and (b) 50nm. Compared with conventional TFTs, SSOB-TFTs give reduced kink effect and increased breakdown voltage……………………………………….22. Fig. 2.5. The output characteristics of the the p+ drain - n+ source poly-Si TFTs with channel thickness 50nm before Ni salicidation. The drain voltage offset is approximately 0.5V………………………………………..23. Fig. 2.6. The transfer characteristics of the Schottky drain and the SSOB-TFTs with channel thickness 50nm. The large GIDL-like current is due to Schottky barrier drain……………………………………………….24. Fig. 2.7. The output characteristics of the Schottky drain and the SSOB-TFTs with channel thickness 50nm. The Schottky drain TFTs have a small drain voltage offset (< 0.5V)………………………………………..25. Fig. 2.8. The output characteristics of (a) the SSOB-TFTs and (b) the conventional TFTs with channel thickness 100nm at different negative source voltage. When the source voltage is more negative, the source. to body junction is more forward bias and kink effect is more serious. XII.

(15) in conventional TFTs………………………………………………..26 Fig. 2.9. The output characteristics of (a) the SSOB-TFTs and (b) the conventional TFTs with channel thickness 50nm at different negative source voltage. When the source voltage is more negative, the source to body junction is more forward bias and kink effect is more serious. in conventional TFTs………………………………………………..27. Chapter 3 Fig. 3.1. The main process flow of FSA-TFTs………………………………..38. Fig. 3.2. The. cross-sectional. transmission. electron. microscopy (TEM). micrographs of FSA-TFTs with gate length = 0.8µm and channel thickness = 40nm……………………………………………………39 Fig. 3.3. The measured transfer characteristics of the n-channel conventional and the n-channel FSA-TFTs with W / L = 10µm / 0.8µm………….40. Fig. 3.4. The field-effect mobility of the n-channel conventional and the n-channel FSA-TFTs with W / L = 10µm / 0.8µm…………………..41. Fig. 3.5. The measured output characteristics of the n-channel conventional and the n-channel FSA-TFTs with W / L = 10µm / 0.8µm………….42. Fig. 3.6. The parasitic resistance RP of (a) n-channel FSA-TFTs with in-situ doped gate, (b) n-channel FSA-TFTs with undoped gate and (c) n-channel conventional TFTs, in the linear region, is extracted by plotting measured on state resistance (RON) versus gate length (LG)…………………………………………………………………..43. Fig. 3.7. The on /off current ratio (ION / IOFF) of the n-channel conventional and the n-channel FSA-TFTs with W =10µm. The on-state current is defined as drain current ( ID ) at VG = 10.0 V, VDS = 3.0 V and the off-state current is defined as minimum drain current ( Imin ) at VDS = 3.0 V…………………………………………………………………44. Fig. 3.8. The extracted threshold voltage VTH of the n-channel conventional and the n-channel FSA-TFTs with different gate lengths (defined as ID = W / L × 100 nA at VDS = 0.5 V)…………………………………...45. XIII.

(16) Fig. 3.9. The extracted VTH roll-off of the n-channel FSA-TFTs with in-situ doped gate and n-channel partially salicided TFTs with in-situ doped gate. The partially salicided TFTs were form by RTA 500°C for 60-sec and RTA 550°C for 30-sec…………………………………………..46. Fig.3.10. Threshold. voltage. shift. (∆VTH). versus. drain. voltage. VDS. characteristics for the n-channel conventional and the n-channel FSA-TFTs with W / L = 10µm / 0.8µm. The reduced VTH shift for the n-channel FSA-TFTs exhibits suppressed floating body effect……..47 Fig. 3.11. The measured transfer characteristics of the p-channel conventional and the p-channel FSA-TFTs with W / L = 10µm / 0.8µm………….48. Fig. 3.12. The field-effect mobility of the p-channel conventional and the p-channel FSA-TFTs with W / L = 10µm / 0.8µm…………………..49. Fig. 3.13. The measured output characteristics of the p-channel conventional and the p-channel FSA-TFTs with W / L = 10µm / 0.8µm………….50. Fig. 3.14. The parasitic resistance RP of (a) p-channel FSA-TFTs with undoped gate and (b) p-channel conventional TFTs, in the linear region, is extracted by plotting measured on state resistance (RON) versus gate length (LG)…………………………………………………………...51. Fig. 3.15. The on /off current ratio (ION / IOFF) of the p-channel conventional and the p-channel FSA-TFTs with W =10µm. The on-state current is defined as drain current ( ID ) at VG = -15.0 V, VDS = -3.0 V and the off-state current is defined as minimum drain current ( Imin ) at VDS = -3.0 V………………………………………………………………..52. Fig. 3.16. The extracted threshold voltage VTH of the p-channel conventional and the p-channel FSA-TFTs with different gate lengths (defined as ID = W / L × 10 nA at VDS = -0.5 V)…………………………………...53. Chapter 4 Fig. 4.1. The key process flows of NSILC-VTFTs and MILC-VTFTs…...…..65. Fig. 4.2. The Schematic device cross-section structure of NSILC-VTFTs. The NSILC-VTFTs are equivalent to dual-gate device structures. The effective channel length of NSILC-VTFTs is defined by thickness of poly-Si gate and gate oxide………………………………………….67 XIV.

(17) Fig. 4.3. The plan view optical microscope microphotograph of NSILCVTFTs. The length of n+ floating region is defined by the mask channel length (Lmask). The mask channel width (Wmask) is equal to effective channel width of NSILC-VTFTs…………………………..68. Fig. 4.4. (a) The transmission electron diffraction (TED) pattern of vertical poly-Si channel in NSILC-VTFTs and (b) cross-section transmission electron microscope (TEM) microphotograph of NSILC-VTFTs. The gate oxide thickness and channel thickness are both 500Å. The undercut depth of poly-Si gate is 1000Å……………………………69. Fig. 4.5. (a) The plan view optical microscope microphotograph of test key after MILC process at 500°C for 24hr and (b) the plan view optical microscope microphotograph of test key after NSILC process at 500°C for 12hr. The Ni accumulation of grain boundaries is found in the MILC process but it is not found in the NSILC process………...70. Fig. 4.6. (a) The plan view optical microscope microphotograph of MILC-VTFTs after annealing at 500°C for 12hr and (b) the plan view optical. microscope. microphotograph. of. NSILC-VTFTs. after. annealing at 500°C for 12hr. The Ni accumulation of the n+ floating region is found in the MILC-VTFTs but it is not found in the NSILC-VTFTs………………………………………………………71 Fig. 4.7. The transfer characteristics of conventional TFTs and NSILC-VTFTs. The effective channel length of NSILC-VTFTs is 0.6µm…………..72. Fig. 4.8. The transfer characteristics of MILC-VTFTs and NSILC-VTFTs. The effective channel length of MILC-VTFTs and NSILC-VTFTs is 0.6µm………………………………………………………………..73. Fig. 4.9. The transfer characteristics of NSILC-VTFTs with constant Lmask = 0.8µm and different Wmask. The effective channel length of NSILC-VTFTs is 0.6µm…………………………………………….75. Fig. 4.10. The illustration of Ni induced lateral crystallization in wide channel width (Wmask) and narrow channel width (Wmask)…………..………77. Fig. 4.11. The transfer characteristics of NSILC-VTFTs with constant Lmask =10µm and different Wmask. The effective channel length of NSILC-VTFTs is 0.6µm…………………………………………….78 XV.

(18) Fig. 4.12. The transfer characteristics of NSILC-VTFTs with Wmask = 5µm and NSILC-VTFTs with multi-channel Wmask = 0.8 × 5 µm. Lmask is constant = 10µm. The effective channel length of NSILC-VTFTs is 0.6µm………………………………………………………………..79. Fig. 4.13. The transfer characteristics of the NSILC-VTFTs with constant Wmask = 0.8µm and different Lmask. The effective channel length of NSILC-VTFTs is 0.6µm…………………………………………….80. Fig. 4.14. The transfer characteristics of the NSILC-VTFTs and NSILC-VTFTs (RTA) with Wmask / Lmask = 0.8µm / 0.8µm. The effective channel length is 0.6µm……………………………………………………...82. Fig. 4.15. The transfer characteristics of the NSILC-VTFTs (RTA) with constant Wmask = 0.8µm and different Lmask. The NSILC-VTFTs (RTA) were crystallized by first step lateral crystallization (500°C for 12hr) and second step RTA (700°C for 60sec). The effective channel length of NSILC-VTFTs (RTA) is 0.6µm……………………………………..83. Chapter 5 Fig. 5.1. The schematic cross-sectional device structures of (a) Si / Ge T-gate TFTs and (b) conventional TFTs…………………………………….96. Fig. 5.2. The simulated lateral electric field distribution along the channel / gate oxide interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation at VG = 0 V and VD = 15 V……………………………………………………………98. Fig. 5.3. The simulated lateral electric field distribution along the channel / gate oxide interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation at VG = -10 V and VD = 10 V……………………………………………………………99. Fig. 5.4. The main fabrication process steps of Si / Ge T-gate TFTs….…….100. Fig. 5.5. The. cross-sectional. transmission. electron. microscope. microphotograph ( TEM ) of Si / Ge T-gate TFTs…………………101 Fig. 5.6. The composition of pure Ge gate layer extracted from the energy dispersive x-ray spectrometer analysis…………………………….102 XVI.

(19) Fig. 5.7. The measured transfer characteristics of conventional TFTs and Si / Ge T-gate TFTs with (a) W / L = 10 µm / 10 µm and (b) W / L = 10µm/5 µm. The device channel thickness = 100nm……………...103. Fig. 5.8. The measured OFF-state leakage currents of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm and device channel thickness = 100nm for different drain biases at VG = -10V……….104. Fig. 5.9. The measured ON / OFF currnet ratio of conventional TFTs and Si / Ge T-gate TFTs with W = 10 µm and different channel length. The device channel thickness = 100nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( ID ) at VG = 20 V, VD = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I min ) at VD = 10 V………..105. Fig. 5.10. The output characteristics of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm and device channel thickness = 100nm………………………...……………………………………106. Fig. 5.11. The measured transfer characteristics of Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation. The device channel thickness = 50nm…………………………………………………..107. Fig. 5.12. The measured OFF-state leakage currents of Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation for different drain biases at VG = -10V. W / L = 10 µm / 10 µm and device channel thickness = 50nm…………………………………………………..108. Fig. 5.13. The measured ON / OFF currnet ratio of Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation in different channel length and constant channel width = 10 µm. The device channel thickness = 50nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( ID ) at VG = 20 V, VD = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I min ) at VD = 10 V………………………109. XVII.

(20) Fig. 5.14. The output characteristics of Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation. W / L = 10 µm / 10 µm and device channel thickness = 50nm…………………………………..110. Chapter 6 Fig. 6.1. The key process flows of poly-Si TFT nonvolatile Ge-NCs memories…………………………………………………………...121. Fig. 6.2. The schematics of the two-step growth process of Ge-NCs. In step 1, the Si nuclei are formed on the SiO2 surface. Then, in step 2, the Ge-NCs grow selectively on the Si nuclei…………………………122. Fig. 6.3. The atomic force microscope (AFM) microphotographs of Ge-NCs for (a) 80sec and (b) 120sec GeH4 deposition time at 370°C……...123. Fig. 6.4. The cross section Transmission Electron Microscope (TEM) microphotographs of poly-Si TFT nonvolatile Ge-NCs memories. The blocking oxide and tunneling oxide thickness is about 44nm and 11nm. respectively. The pure Ge-NCs embedded in oxide are easy to control the real thickness of tunneling oxide. The sizes of the Ge-NCs are about 9nm~12nm and the density of the Ge-NCs is about 2~ 4×1011cm-2………………………………………………………….124 Fig. 6.5. The channel hot electron injection program mechanism in poly-Si TFTs with gate length = 1µm ~ 0.8µm. The floating body induced drain avalanche is biased at (a) VG = 0V, VD = 8~12V and (b) VG = 10V, VD = 8~12V. The additional electron injection is due to the floating body induced drain avalanche with parasitic n-p-n bipolar in the thin film devices………………………………………………..125. Fig. 6.6. The measured floating body induced drain avalanche currents of poly-Si TFTs with different channel thickness and (a) gate length = 1µm (b) gate length = 0.8µm. The thin film devices have high channel hot electron injection efficiency in the program region. The applied drain voltage can be reduced with short gate length and thick channel thickness……………………………………………………………126. Fig. 6.7. The measured transfer characteristics of poly-Si TFT nonvolatile. XVIII.

(21) Ge-NCs memories in the P/E states. The memory windows of poly-Si TFT nonvolatile Ge-NCs memories with W / L = 0.8µm / 0.8µm can be larger than 7~8V for (a) channel thickness = 50-nm and (b) channel thickness = 100-nm………………………………………………...128 Fig. 6.8. The. measured. programming. characteristics. of. poly-Si. TFT. nonvolatile Ge-NCs memories with channel thickness = 50-nm and W/L = 1µm / 1µm in the program region biased at (a)VG = 10V, VD = 11V, 12V and (b)VG = 12V, VD = 11V,12V……………………….129 Fig. 6.9. The. measured. programming. characteristics. of. poly-Si. TFT. nonvolatile Ge-NCs memories with channel thickness = 50-nm and W/L = 0.8µm / 0.8µm in the program region biased at (a)VG = 10V, VD = 10V, 11V and (b)VG = 12V, VD = 10V,11V………………...130 Fig. 6.10. The. measured. programming. characteristics. of. poly-Si. TFT. nonvolatile Ge-NCs memories with channel thickness = 100-nm and W / L = 1µm / 1µm in the program region biased at (a)VG = 10V, VD = 10V, 11V and (b)VG = 12V, VD = 10V,11V…………………….131 Fig. 6.11. The. measured. programming. characteristics. of. poly-Si. TFT. nonvolatile Ge-NCs memories with channel thickness = 100-nm and W / L = 0.8µm / 0.8µm in the program region biased at (a)VG = 10V, VD = 9V, 10V and (b)VG = 12V, VD = 9V,10V…………………...132 Fig. 6.12. The measured erasing characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 50-nm and W / L = 0.8µm / 0.8µm in the erase region biased at (a)VG = -10V, VD = 10V, 11V and (b)VG = -12V, VD = 10V,11V. The high erasing efficiency is due to floating body effect induced drain avalanche………………134. Fig. 6.13. The measured erasing characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 100-nm and W / L = 0.8µm / 0.8µm in the erase region biased at (a)VG = -10V, VD = 9V, 10V and (b)VG = -12V, VD = 9V,10V. The high erasing efficiency is due to floating body effect induced drain avalanche………………135. Fig. 6.14. The measured gate disturbance characteristics of poly-Si TFT nonvolatile Ge-NCs memories with W / L = 0.8µm / 0.8µm for (a) channel thickness = 50-nm and (b) channel thickness = 100-nm….136 XIX.

(22) Fig. 6.15. The measured drain disturbance characteristics of poly-Si TFT nonvolatile Ge-NCs memories with W / L = 0.8µm / 0.8µm for (a) channel thickness = 50-nm and (b) channel thickness = 100-nm….137. Fig. 6.16. The measured retention characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 50-nm and W / L = 0.8µm / 0.8µm at (a) room temperature and (b) 85°C. The poly-Si TFT nonvolatile Ge-NCs memories with two-level threshold voltage states have good retention characteristics at 85 °C due to the deep trapping level of Ge-NCs…………………………………………..138. Fig. 6.17. The measured retention characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 100-nm and W / L = 0.8µm / 0.8µm at (a) room temperature and (b) 85°C. The poly-Si TFT nonvolatile Ge-NCs memories with two-level threshold voltage states have good retention characteristics at 85 °C due to the deep trapping level of Ge-NCs…………………………………………..139. Fig. 6.18. The measured endurance characteristics of poly-Si TFT nonvolatile Ge-NCs memories with W / L = 0.8µm / 0.8µm for (a) channel thickness = 50-nm and (b) channel thickness = 100-nm. The memory windows narrow to about 2V after 10 4 P/E cycles………………..140. XX.

(23) Chapter 1 Introduction 1.1. Overview. of. Polycrystalline. Silicon. Thin-Film. Transistors Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in many potential applications including pixel driving elements of active matrix organic light emitting diode (AM-OLED), and integrated peripheral driving circuits and addressing elements of active-matrix liquid crystal displays (AMLCDs) [1.1]-[1.4]. Recently, poly-Si TFTs are very attractive for system on top of the panel (SOP) as devices performances improve further [1.5]. The degree of circuit integration will continue to increase as device performances improve further. The entire system will include memories, such as SRAM and nonvolatile FLSAH Memories, solar cells, and touch sensors as well as driver circuits for AMLCDs [1.6]-[1.8]. Poly-Si TFTs have the potential advantages of silicon-on-insulator (SOI) MOSFETs such as simple fabrication process, good device-to-device isolation, high circuit density, and high device performance as well as the possibility to be applied in vertical 3-D integration. Poly-Si TFTs technology has been receiving more attention because it is a promising mean of achieving 3-D integration, which has been utilized in various 3-D circuits [1.9]-[1.11]. In addition, poly-Si TFTs have been used as the driving devices for pixel, if they can have nonvolatile memories function, then they are very attractive for 3D integration of active devices and SOP application in the future. 1.

(24) However, grain boundaries of poly-Si material cause trap and tail states which put strong influences on device characteristics including an increase in threshold voltage (VTH), decrease in mobility, increase in off-state leakage current, decrease in on-state current, poor subthreshold characteristics and degradation in device reliability[1.12] [1.13]. The trap states in the grain boundaries is though to be associated with the presence of dangling and strained bounds [1.14] To solve these problems, some crystallization methods have been introduced to enlarge the grain size. Poly-Si thin film with large crystalline grains can be obtained using a variety of techniques: rapid thermal annealing (RTA) [1.15], solid phase crystallization (SPC) [1.16], laser crystallization (LC) [1.17] and the relatively new metal-induced lateral crystallization (MILC) [1.18]-[1.20] of amorphous silicon (a-Si). Because crystallization of poly-Si channel plays a main role in carrier mobility and uniformity of poly-Si channel, a robust crystallization method is required for poly-Si TFTs in future various applications. Moreover, these traps also enhance valence-band carriers jump to conduction band via trap-assisted thermionic emission or trap-assisted thermionic field emission, resulting in large leakage current even under off-state operation [1.21], [1.22]. In order to increase the reliability and reduce the leakage current, poly-Si TFTs with offset gated, lightly doped drain (LDD), gate-overlapped LDD, floating gate spacer, air cavities, or field-induced drain (FID) structures have been suggested to reduce the electric field near the drain [1.23]-[1.29]. In the thin-film transistors, the output characteristics exhibit an anomalous increase of current in the saturation regime, often called “kink” effect due to an analogy with silicon-on-insulator (SOI) devices [1.30]-[1.32]. This phenomenon can be attributed to the floating-body effect [1.33] and the avalanche multiplication enhanced by grain boundary-traps [1.31]. In the floating-body thin-film devices, the 2.

(25) improved parasitic BJT effect can be achieved by using deep salicidation and fully silicided source/drain structure [1.34], [1.35]. Several structures such as lateral body terminal (LBT) [1.36], low-barrier body-contact (LBBC) [1.37], and Schottky body contact [1.38] have been reported in order to reduce the kink current. With the increasing demand for portable systems, it is desirable to have high performance integrated circuits with high integration density, low power consumption, and low voltage operation. Traditionally, this has been achieved by device scaling. However, with the current state-of-the-art technology, the achievable integration density using a conventional approach has almost reached its saturation point. In order to provide a revolutionary breakthrough in circuit compactness, three-dimensional (3-D) VLSI technology has become an important topic in research [1.11]. In order to apply poly-Si TFTs in the 3D integration of active devices and SOP application in the future, nonvolatile memories function in poly-Si TFTs has become an important topic in research. Recently, nonvolatile memory devices using Ge, Si and metal nanocrystals (Ge-NCs, Si-NCs and M-NCs) as floating gate (FG) have been widely studied because of its excellent memory performance and high scalability. Some methods to form various NCs have been introduced in past including the thermal annealing of trapping materal and dielectric mixture, the oxidation of SiGe or SiMX and Si or Ge ion implantation [1.39]-[1.41]. In summary, the technologies of poly-Si TFTs will become more and more important in future applications including 3D integration of active devices and SOP. More researches investigate the related new technologies and underlying mechanisms in thin-film devices with scaling down dimension are worthy to study. Various materials will be applied for fabricating high-performance thin-film devices.. 3.

(26) 1.2 Applications of Metal-Silicidation in Poly-Si TFTs Recently, metal-silicidation procedures have been widely used in VLSI technology. These metal-silicides, such as Ti, Co, Pt, and Ni, have been introduced into integrated circuits for many processes properties including low resistivity, good adhesion, low contact resistance, low contamination to devices, no metal-compound formation, minimum silicon consumption, ease of pattern definition, high barrier height for Schottky devive applications [1.42]. It is well known that nickel monosilicide (NiSi) has several advantages over titanium silicide (TiSi2) and cobalt silicide (CoSi2) [1.43], [1.44]. These advantages include a low thermal budget. NiSi is typically formed between 400 oC and 600oC, as compared to above 800oC for a low-resistance TiSi2 [1.43]. The resistance of the narrow TiSi2 lines increases significantly when the linewidth is below 200–300 nm [1.45]. CoSi2 extends the linewidth down to ~ 100 nm [1.46]. NiSi has a low resistance in narrow lines for further reduction in the linewidth [1.43]. The formation of NiSi consumes less Si compared with TiSi2 and CoSi2, which is important in forming contacts to ultra-shallow source/drain junctions. Between 200 oC and 350 oC, several phases of Ni-rich Ni silicide, such as trinickel silicide (Ni3Si) and dinickel silicide (Ni2Si), are formed at the Ni / Si interface [1.47], [1.48]. Between 400 oC and 600 oC, the stable phase formed at the interface is NiSi. Above 700 oC, Ni disilicide (NiSi2) is formed [1.49], [1.50]. The Ni-rich phases formed below 400 oC, such as Ni2Si and Ni3Si, have much higher resistance than NiSi. Above 700oC, NiSi2 is formed, which also has a higher resistance than NiSi. Therefore, the temperature window for forming a low-resistance NiSi is limited to 400 oC ~ 600 oC. Moreover, NiSi has a lower-temperature than TiSi2 and CoSi2, making it suitable for the lower-temperature poly-Si TFTs fabrication. A self-aligned top-gate poly-Si. 4.

(27) TFT using Ni-silicide layers have been studied in the past [1.51]-[1.53]. To simplify the fabrication process of the poly-Si TFT and to reduce parasitic S/D resistance using Ni silicide as ohmic contact layers of the source/drain electrodes. Besides, a fully silicided S/D poly-Si TFTs (FSD TFTs) with ultrashort S/D extension (SDE) structure was developed. Because of the implant-to-silicide (ITS) technique, different to the process of salicide TFTs, the dopants can be implanted into the silicide region without damage the poly-Si region, and then, activated and diffused out quickly from silicide to the interface of silicide/poly-Si at about 600oC by rapid thermal annealing (RTA). Therefore, the activation thermal budget for FSD TFTs is less than that for the conventional and salicide TFTs [1.54].. 1.3 Applications of Germanium in Poly-Si TFTs It is easy to incorporate germanium with silicon to become Si1-XGeX alloy. Essentially, Si1-XGeX cannot only lower the process thermal budget but also promotes the carrier mobility. Poly-Si1-XGeX TFTs have been found to have higher mobility than similarly processed poly-Si TFTs [1.55]. P-channel TFTs with good device characteristics can be fabricated in poly-Si1-XGeX, films [1.56]. The use of relatively inexpensive glass substrates further reduces manufacturing cost; however, it places tighter constraints on the thermal-budget allowance for a TFT fabrication process, due to problems associated with glass shrinkage and warpage. The fabrication of high-performance poly-Si TFT's typically requires high- temperature (≥600oC) and/or long-time anneals, which makes it incompatible with large area glass substrates. This problem can be solved through the use of silicon-germanium (Si1-XGeX) films, which can be deposited and crystallized at lower temperatures than Si films. Dopants can be activated at lower temperatures in Si1-XGeX than in Si [1.57], [1.58]; therefore, a lower. 5.

(28) thermal budget can be used to fabricate poly- Si1-XGeX TFTs compared to poly-Si TFTs, to realize CMOS circuits on large-area glass substrates. Poly-Si1-XGeX TFTs fabricated using low-temperature solid phase crystallization (LT-SPC) have been demonstrated [1.56]. For LT-SPC applications, Si1-XGeX is particularly advantageous, as it requires substantially shorter annealing cycles than required for the crystallization of Si. Hence, Si1-XGeX seems to be a potential material for the active layer of a TFT [1.59]. Furthermore, vertical 3D integration of devices using thin film transistors (TFTs) is a promising means of achieving three-dimensional (3-D) integration. Unfortunately, TFT performance is typically substantially worse than that of bulk devices. Variation in device performance is introduced by the random distribution of grains in the device [1.60], since the grain size is on the order of the device size. To achieve large grain TFTs with a control over the location of the grain is therefore highly desirable. Lateral solid-phase crystallization using a seeding agent to precisely nucleate the grains is an extremely promising means of achieving this. Metal induced crystallization has been studied in the past, using metals such as nickel [1.61]. Unfortunately, the integration of such a process into a CMOS technology is problematic due to the deleterious effect of nickel on device performance [1.62]. A metal-contamination-free technique to achieve lateral crystallization could be integrated into a standard CMOS process. A technique to achieve lateral crystallization through the use of germanium seeding has been proposed [1.63]. This technique is free of metallic seeding agents and is therefore easily integrated into a CMOS technology. Additionally, the technique performs extremely well for small devices, making it very promising for next generation. VLSI. applications.. The. process. has. been. high-performance TFTs suitable for 3-D integration applications.. 6. used. to. fabricate.

(29) 1.4 Motivation 1.4.1 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying Ni-Silicidation in Gate Engineering, Source/Drain Engineering, and Channel Crystallization . The output characteristics exhibit an anomalous current increase in the saturation regime, often called “kink” effect [1.64], [1.65] due to an analogy with siliconon-insulator (SOI) devices [1.66]. This phenomenon can be attributed to the floatingbody effect [1.67] and the avalanche multiplication enhanced by grain boundary-traps [1.68]. The avalanche multiplication is caused by the high drain electric field and the presence of grain boundaries and traps enhances the kink effect in poly-Si TFTs [1.68]. With increasing drain voltage, the added drain current enhances impact ionization and parasitic bipolar junction transistor (BJT) effect, which leads to a premature breakdown in return, particularly in n-channel TFTs [1.33]. Several structures such as lateral body terminal (LBT) [1.36], low-barrier body-contact (LBBC) [1.37], and Schottky body contact [1.38] have been reported in order to reduce the kink current. Among these structures, Schottky barrier MOSFETs (SB-MOSFETs) are thought to have some advantages over conventional MOSFETs, such as the reduction of parasitic resistance and capacitance, and the immunity to the short channel [1.69], latch-up, or silicon-on- insulator floating-body effects [1.70]. In the floating-body thin-film devices, the improved parasitic BJT effect can be achieved by using deep salicidation and fully silicided source/drain structure [1.34], [1.35]. Due to low hole field-effect mobility, p-channel TFTs have lower on-state current compared with n-channel TFTs. Nevertheless, the p-channel TFTs have some advantages, such as low off-state leakage current, slight floating-body effect and kink effect, weak drain impact ionization and high hot carrier reliability. In addition, the. 7.

(30) thin-channel poly-Si TFTs have the improved device characteristics such as small leakage current and suppressed floating-body effect compared with the thick-channel poly-Si TFTs [1.71]. Thin channel film also leads to increased source and drain parasitic resistance. The parasitic S/D resistances become increasingly a serious issue in the thin-channel poly-Si TFTs and SOI devices. Several methods such as self-aligned silicide, selective tungsten-clad and metal-replaced junction technology were proposed to reduce parasitic S/D resistance for thin-channel SOI devices and poly-Si TFTs [1.72]-[1.75]. Furthermore, silicided and metal gates have a higher capacitance than poly-Si gates due to the elimination of poly-Si depletion [1.76]. The field-effect mobility and on-state current can be improved by reducing parasitic S/D resistance and increasing gate capacitance [1.74], [1.75]. In the Chapter 2 and 3, application of Ni-salicidation for suppression of floating-body effect and parasitic BJT effect in poly-Si TFTs were demonstrated and investigated. However, the application of poly-Si TFTs is mainly limited in low-temperature flat-panel display. Conventional poly-Si TFTs suffer from serious poor device characteristics and device-to-device variations resulted from the grain boundaries in the channel region. It is believed that electrical characteristics of the poly-Si TFTs can be improved if the poly-Si grain size can be enhanced and the number of grain boundaries in the channel can be reduced. Metal-Induced-Lateral-crystallization (MILC) technology has been studied in the past to achieve large and regular poly-Si grain from amorphous silicon [1.18]-[1.20]. In addition, vertical thin film transistors (VTFTs) are suitable for high density 3-D integration since their channel length are determined by the thicknesses of SiO2 or poly-Si films instead of the photolithographic limitation. Many works had been devoted to developing and studying VTFTs [1.77], [1.78]. In Chapter 4, application of Ni-silicide induced lateral crystallization for novel symmetric vertical channel poly-Si TFTs were investigated. 8.

(31) 1.4.2 From the Perspective of Poly-Si TFTs Characteristics Enhanced by Applying Germanium in Gate Engineering and Nonvolatile Memories The large OFF-state leakage current and device instability of poly-Si TFTs are hindrances to the high-performance and high reliability circuit applications. It is well known that the dominant mechanism of the OFF-state leakage current is the field emission via grain boundary traps due to a high electric field in the drain depletion region. The leakage current is increased with increasing gate and drain voltages which enhance the field emission via grain boundary traps in the depletion region near the drain [1.79], [1.80]. In order to increase the reliability and reduce the leakage current, poly-Si TFTs with offset gated, lightly doped drain (LDD), gate-overlapped LDD, floating gate spacer, air cavities, or field-induced drain (FID) structures have been suggested to reduce the electric field near the drain [1.23]-[1.29]. In Chapter 5, application of novel self-aligned Si / Ge T-gate for suppression of OFF-state leakage current in poly-Si TFTs were proposed and demonstrated. In addition, nanocrystal floating-gate memories offer a number of potential advantages over FLASH devices, including improved scalability, retention, and cyclability, as well as lower voltage operation. In these devices the floating gate is composed of discrete, electrically-isolated particles (rather than a continuous film as in conventional FLASH) [1.81]. Recently, nonvolatile memory devices using Ge or Si nanocrystals (Ge-NCs or Si-NCs) as floating gate (FG) have been widely studied because of its excellent memory performance and high scalability. Ge has smaller bandgap and similar electron affinity compared with Si. Nonvolatile memory devices using Ge-NCs instead of Si-NCs have superior retention properties [1.39]. In addition, Ge/Si-NCs have been reported to possess superior charge retention capability than Ge or Si-NCs [1.82]. In Chapter 6, application of new Ge-NCs for poly-Si TFT 9.

(32) nonvolatile memories with low temperature annealing were proposed and studied.. 1.5 Thesis Organization This thesis is organized as follow: In Chapter 1, the overview of poly-Si TFTs and applications of Ni-silicidation and germanium in poly-Si TFTs are described. In Chapter 2, a self-aligned Schottky barrier source and ohmic body contact (SSOB) method was proposed to contact the body terminal of poly-Si TFTs and form the silicided source applicable to technologies that incorporate self-aligned silicide cladded junctions. The new structure provides a very effective body contact to suppress all undesirable floating-body effects. Various device parameters such as subthreshold characteristics, output characteristics, and breakdown voltage are compared with conventional poly-Si TFTs. In Chapter 3, the n-channel and p-channel fully Ni- self-aligned silicided (fully Ni-salicided) source/drain and gate poly-Si thin-film transistors (n-channel and p-channel FSA-TFTs), whose source/drain and gate layer are completely silicided with Ni, have been successfully fabricated on a 40-nm thick channel layer. The low-resistance fully Ni-salicided source/drain and gate allow a significant recovery of the intrinsic characteristics of thin-channel TFTs. We found that the measured characteristics of FSA-TFTs significantly suppressed floating-body and parasitic BJT effects. Threshold voltage (VTH) difference between in-situ n+ doped gate and undoped gate n-channel FSA-TFTs was also discussed in this chapter. In Chapter 4, the novel symmetric vertical channel poly-Si TFTs fabricated by Ni-silicide induced. lateral crystallization technology (NSILC-VTFTs) were. investigated. The NSILC-VTFTs were fabricated by combining NSILC process and 10.

(33) vertical poly-Si channel. The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. In the dual-gate devices, a n+ floating region is included in the channel region between S/D. The Ni-accumulation and grain boundaries induced from S/D sides can be centralized in the n+ floating region. The dual-gate structure is employed to eliminate the grain boundaries perpendicular to the current flow in the channel. In this work, the effects of grain boundaries in the vertical channel and n+ floating region crystallized by NSILC or MILC processes are studied. The NSILC-VTFTs can eliminate metal contaminations on source and drain region due to the limited Ni source from Ni-silicided seeding window arranged on source and drain contact holes. When the device Lmask and Wmask are scaled down, the probability of the channel region in NSILC-VTFTs to cover grain boundaries in the length and width direction decreases significantly. The NSILC-VTFTs with small Lmask and Wmask have better device performance and higher uniformity. Furthermore, we have discovered that amorphous silicon was crystallized by two steps: first step lateral crystallization at 500°C for 12hr and second step rapid thermal annealing (RTA) at 700°C for 60-sec, the grain size of the resulting poly-Si can be significantly enhanced and device characteristics can be further improved. In order to investigate the impact of grain boundaries in the vertical channel and n+ floating region, all the devices were fabricated without further NH3 plasma treatment. The measured results show the NSILC-VTFTs without NH3 plasma treatment have high field-effective mobility, small subthreshold swing (S.S.), and low off-state leakage current. In Chapter 5, the novel self-aligned Si / Ge T-gate poly-Si TFTs (Si / Ge T-gate TFTs) were proposed and demonstrated. The Si / Ge T-gate was formed by selective wet etching of Ge gate layer. The Ge regions etched at the gate edges were refilled by low-pressure chemical vapor deposition tetraethoxysilane (LPCVD TEOS) oxide in the passivation process. The thick gate oxide layer at the gate edges and the 11.

(34) passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, LDD, spacer, and sub-gate bias. The lateral electric field within the channel can be lowered by using the lateral selective etching of Ge within the gate stack at the gate edges without extra fabrication cost in the Si / Ge T-gate TFTs. The Si / Ge T-gate TFTs have a reduced OFF-state leakage current at negative voltages, an improved ON / OFF current ratio, and a smaller drain conductance in saturation due to a reduced impact ionization at the drain end of the channel compared with conventional TFTs. In Chapter 6, the new poly-Si TFT nonvolatile Ge-NCs memories with low temperature annealing were proposed. The Ge-NCs embedded in oxide were formed by low-pressure chemical vapor deposition (LPCVD) at 370°C [6.10]. The size and density of Ge-NCs can be easily controlled by GeH4 deposition time and flow rate. Furthermore, the programming / erasing (P/E) characteristics of thin film nonvolatile memory devices (SOI and TFTs) with floating body effect have been investigated. We find that drain voltage is the key point to improve P/E efficiency in thin film nonvolatile memory devices. The mechanism is due to the floating body induced drain avalanche with parasitic n-p-n bipolar in the thin film devices. The drain voltage needs to adjust with different gate length and different channel thickness. We can reduce the applied drain voltage to achieve higher P/E efficiency by this floating body effect compared with bulk memory devices. Finally, conclusions as well as recommendation for further research are given in Chapter 7.. 12.

(35) Chapter 2 Suppression of the Floating-Body Effect in Poly-Si Thin-Film Transistors with Self-Aligned Schottky Barrier Source and Ohmic Body Contact Structure. 2.1 Introduction Polycrystalline silicon thin-film transistors (poly-Si TFTs) are key devices in active-matrix liquid crystal displays (AMLCDs). Due to the relatively-large field-effect mobilities in both n- and p-channel devices, poly-Si TFTs can be used to incorporate the integrated driving circuits in AMLCDs [2.1]. Recently, poly-Si TFTs are suitable for the pixel driving elements of active matrix organic light emitting diode (AM-OLED) [2.2], and the driving TFTs with a high output resistance are desirable. However, the output characteristics exhibit an anomalous current increase in the saturation regime, often called “kink” effect [2.3], [2.4] due to an analogy with silicon- on-insulator (SOI) devices [2.5]. This phenomenon can be attributed to the floating- body effect [2.6] and the avalanche multiplication enhanced by grain boundary-traps [2.7]. The avalanche multiplication is caused by the high drain electric field and the presence of grain boundaries and traps enhances the kink effect in poly-Si TFTs [2.7]. The added drain current enhances impact ionization which leads to a premature breakdown in return [2.6]. Several structures such as lateral body 13.

(36) terminal (LBT) [2.8], low-barrier body-contact (LBBC) [2.9], and Schottky body contact [2.10] have been reported in order to reduce the kink current. However, LBT needs additional terminal for the body bias; LBBC needs additional implantation processes and thicker channel thickness for the body contact; and the high forward bias turn on voltage of Schottky diode was reported using Schottky body contact. Among these structures, Schottky barrier MOSFETs (SB-MOSFETs) are thought to have some advantages over conventional MOSFETs, such as the reduction of parasitic resistance and capacitance, and the immunity to the short channel [2.11], latch-up, or silicon-on- insulator floating-body effects [2.12]. In this chapter, we have developed a self-aligned Schottky barrier source and ohmic body contact (SSOB) method for contacting the body terminal of poly-Si TFTs and forming the silicided source applicable to technologies that incorporate self-aligned silicide cladded junctions. The new structure provides a very effective body contact to suppress all undesirable floating-body effects. Various device parameters such as subthreshold characteristics, output characteristics, and breakdown voltage are compared with conventional poly-Si TFTs.. 2.2 Experiment The key processes to fabricate the SSOB-TFTs are shown in Fig. 2.1 First, a 50-nm or 100-nm amorphous silicon (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C on oxidized silicon wafers. Next, the a-Si layer was then recrystallized by solid phase crystallization (SPC) at 600°C for 24-hr. After the active region patterning, a 50-nm gate oxide layer was deposited by high-density plasma chemical vapor deposition at 350°C. Subsequently, a 150-nm in-situ n+ doped a-Si layer and a 150-nm Si3N4 hard mask layer were deposited by 14.