5.2 Device Structure Design and Simulation
5.4.3 Si / Ge T-gate TFTs with TEOS Passivation or SIN X Passivation
Passivation
Figures 5.11 exhibit the measured transfer characteristics of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation. The device channel thickness is 50-nm. The ON-state current degrades with increasing thickness of Ge gate layer in Si / Ge T-gate TFTs with TEOS passivation but the ON-state current can be maintained with increasing thickness of Ge gate layer in Si / Ge T-gate TFTs with SiNx passivation. This is due to that the gate dielectric near the drain can be effectively refilled by the high κ gate dielectric SiNX at the gate edges in Si / Ge T-gate TFTs with SiNX passivation. The high κ gate dielectric SiNX at the gate edges can increase the gate capacitance and maintain the ON-state current. The OFF-state leakage currents of Si / Ge T-gate TFTs with TEOS passivation are significantly lower than those of Si / Ge T-gate TFTs with SiNX passivation. The larger OFF-state leakage currents of Si / Ge T-gate TFTs with SiNX passivation is due to larger lateral drain electric field [5.8], [5.13]. In addition, the subthreshold swing (S.S.) can be improved with increasing undercut distance in Si / Ge T-gate TFTs with SiNX passivation. The OFF-state leakage currents of Si / Ge T-gate TFTs with with
TEOS passivation or SiNX passivation are almost identical in all experimental split conditions.
Figures 5.12 display the measured OFF-state leakage currents of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation for different drain biases at VG = -10V. The device channel thickness is 50-nm.The OFF-state leakage currents of Si / Ge T-gate TFTs with TEOS passivation are significantly lower than those of Si / Ge T-gate TFTs with SiNX passivation. The OFF-state leakage current is increased with increasing gate and drain voltages which enhance the field emission via grain boundary traps in the depletion region near the drain [5.6], [5.7]. In the Si / Ge T-gate TFTs with TEOS passivation, the lateral electric field near the drain can be greatly reduced due to the low κ gate dielectric TEOS oxide layer at the gate edges. The larger OFF-state leakage current of Si / Ge T-gate TFTs with SiNx passivation is due to the larger gate dielectric constant of SiNx at the gate edges and higher lateral electric field near the drain. The OFF-state leakage currents can be decreased with increasing thickness of Ge gate layer and the Ge lateral undercut distances in the Si / Ge T-gate TFTs with TEOS passivation but the OFF-state leakage currents are lightly decreased with only increasing thickness of Ge gate layer in the Si / Ge T-gate TFTs with SiNx passivation.
Figure 5.13 illustrates the measured ON / OFF current ratio of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation in different channel length and constant channel width = 10 µm. The device channel thickness is 50-nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( ID ) at VG = 20 V, VD = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I min ) at VD = 10 V. The ON-state current degrades with increasing thickness of Ge gate layer in Si / Ge T-gate TFTs
with TEOS passivation but the ON-state current can be maintained with increasing thickness of Ge gate layer in Si / Ge T-gate TFTs with SiNx passivation. It is due to larger thechannel series resistance under the thick gate dielectric region at the gate edges in thinner channel thickness (50-nm) Si / Ge T-gate TFTs with TEOS passivation. The minimum OFF-state leakage currents of Si / Ge T-gate TFTs with TEOS passivation or SiNX passivation are almost identical in all experimental split conditions. Therefore, the Si / Ge T-gate TFTs with 50-nm Ge gate layer have the highest ON / OFF current ratio than those with 100-nm Ge gate layer due to the highest ON-state currents in the Si / Ge T-gate TFTs with TEOS passivation. In the Si / Ge T-gate TFTs with SiNX passivation, the Si / Ge T-gate TFTs have the identical ON / OFF current ratio in all experimental split conditions. Hence, to optimize the Si / Ge T-gate TFTs with TEOS passivation in two kinds of channel thicknesses (100-nm or 50-nm), the thickness of Ge gate layer should be considered different.
The output characteristics of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation are shown in Figure 5.14. The device channel thickness is 50nm. The Si / Ge T-gate TFTs with TEOS passivation have more saturated output characteristics compared with Si / Ge T-gate TFTs with SiNX passivation due to lower drain lateral electric field. The kink current of Si / Ge T-gate TFTs with TEOS passivation is reduced considerably compared with that of Si / Ge T-gate TFTs with SiNX passivation. The Si / Ge T-gate TFTs with 100-nm Ge gate layer have the most saturated output characteristics but the ON-state current degrades with increasing thickness of Ge gate layer in Si / Ge T-gate TFTs with TEOS passivation. Thechannel series resistances under the thick gate dielectric region at the gate edges raises with increasing thickness of Ge gate layer in thinner channel thickness (50-nm) Si / Ge T-gate TFTs with TEOS passivation.
The Si / Ge T-gate TFTs with SiNx passivation have high ON-state current due
to the high gate dielectric constant of SiNx and low channel series resistance under the thick gate dielectric region at the gate edges. With increasing drain voltage, the added drain current enhances impact ionization and parasitic bipolar junction transistor (BJT) effect, which leads to a premature breakdown in return [5.18], [5.19].
Since the Si / Ge T-gate TFTs with SiNx passivatiocan have larger lateral electric fields near the drain compared with Si / Ge T-gate TFTs with TEOS passivation, the impact ionization and avalanche multiplication can be enhanced with increasing drain voltage VDS [5.8], [5.13].
5.5 Summary
In this work, a self-aligned Si / Ge T-gate poly-Si TFTs effectively reduce the OFF-state leakage current while still maintaining the ON-state current compared with conventional TFTs. The stacked Si / Ge gate layers were successfully deposited by LPCVD. The thick gate oxide layer at the gate edges and passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the vertical and lateral electric fields near the drain without additional mask, LDD, spacer, or sub-gate bias. The Si / Ge T-gate poly-Si TFTs are proved to be a very promising structure with low OFF-state leakage current, improved ON / OFF current ratio, and saturated output characteristics for display system-on- panel applications.
Gate Oxide
Fig.5.1 The schematic cross-sectional device structures of (a) Si / Ge T-gate TFTs and (b) conventional TFTs.
200nm / 0nm Conventional TFTs
800nm 100nm / 100nm
Si / Ge 100nm T-gate TFTs (800nm)
400nm 100nm / 100nm
Si / Ge 100nm T-gate TFTs (400nm)
800nm 150nm / 50nm
Si / Ge 50nm T-gate TFTs (800nm)
400nm 150nm / 50nm
50nm Si / Ge 50nm T-gate TFTs (400nm)
undercut
Si / Ge 100nm T-gate TFTs (800nm)
400nm 100nm / 100nm
Si / Ge 100nm T-gate TFTs (400nm)
800nm 150nm / 50nm
Si / Ge 50nm T-gate TFTs (800nm)
400nm 150nm / 50nm
50nm Si / Ge 50nm T-gate TFTs (400nm)
undercut
Table 5.1 The experimental split table of Si / Ge T-gate TFTs and conventional TFTs.
T E O S P a ssiv a tio n W /L = 1 0 µµµ m /1 0 µµ µµµ m VG = 0 V , VD = 1 5 V
P o sitio n A lo n g C h a n n el la y e r X ( µ m )
9 .5 9 .6 9 .7 9 .8 9 .9 1 0 .0
Lateral Electric Field ( MV/cm )
0 .0
Lateral Electric Field ( MV/cm )
0 .0 interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation at VG = 0 V and VD = 15 V.
T E O S P a ssiv a tio n W /L = 1 0 µµµµ m /1 0 µµµµ m VG = -1 0 V , VD = 1 0 V
P o sitio n A lo n g C h a n n e l L a y e r X ( µ m )
9 .5 9 .6 9 .7 9 .8 9 .9 1 0 .0
Lateral Electric Field ( MV/cm )
0 .0
Lateral Electric Field ( MV/cm )
0 .0 interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation at VG = -10V and VD = 10 V.
Gate implantation, P
+, 60keV, 5× × ×10 ×
15cm
-2Fig.5.4 The main fabrication process steps of Si / Ge T-gate TFTs.
Fig.5.5 The cross-sectional transmission electron microscope (TEM) microphotograph of Si / Ge T-gate TFTs.
Ge
Ge
Si Ge Ge
Ge
Si Ge
Fig.5.6 The composition of pure Ge gate layer extracted from the energy dispersive x-ray spectrometer analysis.
TEOS Passivation
1 0 0nmT-Gate TFTs (400nm) Si / Ge device channel thickness = 100nm.
TEOS Passivation W/L =10µ µ µm/10µ µ µ µm µ
Channel Thinkness =100nm V
G= -10V
Drain Voltage V
D( V )
0 2 4 6 8 10
D ra in C u rr en t I
D( A )
10
-1210
-1110
-1010
-910
-810
-710
-610
-5Si / Ge 5 0 nm T-gate TFTs( 400nm ) Si / Ge 5 0 nm T-gate TFTs( 800nm ) Si / Ge 1 0 0nmT-gate TFTs( 400nm ) Si / Ge 1 0 0nmT-gate TFTs( 800nm ) Conventional TFTs
Fig.5.8 The measured OFF-state leakage currents of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm for different drain biases at VG = -10V.
The device channel thickness = 100nm
TEOS Passivation
Channel Thinkness =100nm Channel Width : 10µm I
ON: V
G= 20V, V
D= 10V I
OFF: I
min, V
D= 10V
Gate Length L
G( µm )
3 4 5 6 7 8 9 10
O N / O F F C u rr en t R at io I
ON/ I
OFF( 1 0
7)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Si / Ge
5 0 nmT-gate TFTs ( 400nm ) Si / Ge
5 0 nmT-gate TFTs ( 800nm ) Si / Ge
1 0 0nmT-gate TFTs ( 400nm ) Si / Ge
1 0 0nmT-gate TFTs ( 800nm ) Conventional TFTs
Fig.5.9 The measured ON / OFF currnet ratio of conventional TFTs and Si / Ge T-gate TFTs with W = 10 µm and different channel length. The device channel thickness = 100nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( ID ) at VG = 20 V, VD = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I min ) at VD = 10 V.
TEOS Passivation W / L = 10µm/10µm Channel Thickness =100nm V
G-V
TH= 2V ~ 8V, Step = 2V
Drain Voltage V
D( V )
0 2 4 6 8 10 12 14 16 18 20 22
D ra in C u rr en t I
D( µ A )
0.0 20.0 40.0 60.0 80.0 100.0
Si/Ge 5 0 nm T-gate TFTs ( 400nm ) Si/Ge 5 0 nm T-gate TFTs ( 800nm ) Si/Ge 1 0 0 nm T-gate TFTs ( 400nm ) Si/Ge 1 0 0 nm T-gate TFTs ( 800nm ) Conventional TFTs
Fig.5.10 The output characteristics of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm. The device channel thickness = 100nm.
C hannel Thickness = 50nm VD= 10V
TEOS Passivation T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation for different drain biases at VG = -10V. W / L = 10 µm / 10 µm and device channel thickness = 50nm.
TEOS Passivation
Fig.5.13 The measured ON / OFF current ratio of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation in different channel length and constant channel width = 10 µm. The device channel thickness = 50nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( ID ) at VG = 20 V, VD = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I min ) at VD = 10 V.
T E O S P a ssiv a tio n
Fig.5.14 The output characteristics of conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiNX passivation. W / L = 10 µm / 10 µm and device channel thickness = 50nm.
Chapter 6
Characteristics of Poly-Si Thin-Film Transistor Nonvolatile Ge Nanocrystals Memories with
High Programming / Erasing Efficiency
6.1 Introduction
Polycrystalline silicon thin-film transistors (poly-Si TFTs) are very attractive for 3D integration of active devices and system on top of the panel (SOP) as devices performances improve further [6.1].The degree of circuit integration will continue to increase as device performances improve further. The entire system will include memories, such as SRAM and nonvolatile FLSAH Memories, solar cells, and touch sensors as well as driver circuits for AMLCDs [6.2]-[6.4]. Poly-Si TFTs have been used as the driving devices for pixel, if they can have nonvolatile memories function, then they are very attractive for 3D integration of active devices and SOP application in the future.
Nanocrystal floating-gate memories offer a number of potential advantages over FLASH devices, including improved scalability, retention, and cyclability, as well as lower voltage operation. In these devices the floating gate is composed of discrete, electrically-isolated particles (rather than a continuous film as in conventional FLASH) [6.5]. Recently, nonvolatile memory devices using Ge or Si nanocrystals (Ge-NCs or Si-NCs) as floating gate (FG) have been widely studied because of its excellent memory performance and high scalability. Ge has smaller
bandgap and similar electron affinity compared with Si. Nonvolatile memory devices using Ge-NCs instead of Si-NCs have superior retention properties [6.6]-[6.11]. In addition, Ge/Si-NCs have been reported to possess superior charge retention capability than Ge or Si-NCs [6.7]. Most of the Ge-NCs fabrication methods, including the thermal annealing of Ge and dielectric mixture, the oxidation of SiGe,
and Ge ion implantation all require annealing at high temperature [6.6], [6.9], [6.11].
In this chapter, the new poly-Si TFT nonvolatile Ge-NCs memories with low temperature annealing were proposed. The Ge-NCs embedded in oxide were formed by low-pressure chemical vapor deposition (LPCVD) at 370°C [6.10]. The size and density of Ge-NCs can be easily controlled by GeH4 deposition time and flow rate.
Furthermore, the programming / erasing (P/E) characteristics of thin film nonvolatile memory devices (SOI and TFTs) with floating body effect have been investigated [6.12]. We find that drain voltage is the key point to improve P/E efficiency in thin film nonvolatile memory devices. The mechanism is due to the floating body induced drain avalanche with parasitic n-p-n bipolar in the thin film devices. The drain voltage needs to adjust with different gate length and different channel thickness. We can reduce the applied drain voltage to achieve higher P/E efficiency by this floating body effect compared with bulk memory devices.
6.2 Experiment
Fig.6.1 shows the key process flows of poly-Si TFT nonvolatile Ge-NCs memories. First, a 50- or 100-nm amorphous silicon (a-Si) active region layer was deposited by LPCVD at 550°C on wet oxide and then was crystallized by solid phase crystallization (SPC) at 600°C for 24-hr. After the active region patterning, an 11-nm tetraethoxysilane (TEOS) tunneling oxide layer was deposited by LPCVD. Then a
stacked ultra thin a-Si capping layer / pure Ge-NCs / a-Si nuclei, a 44-nm TEOS blocking oxide layer, and a 200nm a-Si gate layer were deposited in sequence by LPCVD (Fig.6.1a). After deposition of a-Si nuclei, the pure Ge-NCs were directly deposited by using GeH4 at 370°C. The ultra thin a-Si capping layer can prevent the pure Ge-NCs from oxidation in subsequent processes. This way, the pure Ge-NCs embedded in oxide were easy to control the real thickness of tunneling oxide. After gate implantation and defining gate electrode, a self-aligned implantation was used to form the n+ S/D (Fig.6.1b). After passivation process, dopants were activated by furnace at 600°C for 12-hr. After contact and metallization processes (Fig.6.1c), NH3 plasma treatments were implemented after sintering at 400°C for 30-min.
6.3 Results and Discussion
6.3.1 Formation of Ge-NCs Embedded in Oxide
Figure 6.2 shows schematics of the two-step growth process of Ge-NCs. First, the a-Si nuclei were deposited by using SiH4 as a gaseous precursor at 550°C on tunneling SiO2 surface. This way, we were able to adjust the a-Si nuclei density and, hence, the density of the Ge-NCs was between 109 cm-2 and slightly less than 1012 cm-2. Second, once the a-Si nuclei were deposited, we stopped the SiH4 gas flow. The sample was left under low pressure CVD chamber without oxidizing the a-Si nuclei.
After cooling down CVD chamber temperature to 370°C, GeH4 was introduced to selectively grow Ge-NCs on the a-Si nuclei. This way, the a-Si nuclei were not oxidized because they were never exposed to oxygen. Indeed, no Ge-NCs would grow on oxidized a-Si nuclei [6.10].
Figures 6.3 show the atomic force microscope (AFM) microphotographs of Ge-NCs for (a) 80sec and (b) 120sec GeH4 deposition time at 370°C. The size of
Ge-NCs can be easily controlled by GeH4 deposition time. As shown in Fig. 6.3, the size of Ge-NCs was enlarged with increasing GeH4 deposition time. The low Ge-NCs deposition temperature is suitable for low temperature poly-Si TFTs applications.
Fig.6.4 displays the cross section Transmission Electron Microscope (TEM) microphotographs of poly-Si TFT nonvolatile Ge-NCs memories. A high resolution image of one typical Ge-NC is inserted for revealing the geometrical and crystal characteristics of the Ge-NC. Energy dispersive X-ray diffraction analysis shows that the dark dots between the two oxide layers are pure Ge. The blocking oxide and tunneling oxide thickness is about 44nm and 11nm respectively. The sizes of the Ge-NCs are about 9nm~12nm and the density of the Ge-NCs is about 2 ~ 4×1011cm-2. The pure Ge-NCs embedded in oxide are easy to control the real thickness of tunneling oxide. In NC nonvolatile memories, the size of NC is an important factor that affects electrical characteristics. The size of Ge-NC embedded in oxide should not be scaled below 5 nm, because the quantum confinement effect becomes very significant for such small Ge-NC [6.13], [6.14]. Large quantum confinement leads to the conduction band in the nanocrystal being much higher than that of the Si substrate resulting in enhanced leakage from NC and shorter retention time [6.6]. The TEM microphotographs of Ge-NCs suggest that the Ge-NCs embedded in oxide show good thermal stability after several thermal processing steps including source/drain anneal.
6.3.2 Channel Hot Electron Injection Programming Mechanism in Poly-Si TFTs
Figures 6.5 indicate the channel hot electron injection program mechanism in poly-Si TFTs with gate length = 1µm ~ 0.8µm. The floating body induced drain avalanche is biased at (a) VG = 0V, VD = 8~12V and (b) VG = 10V, VD = 8~12V. The additional electron injection is due to the floating body induced drain avalanche with
parasitic n-p-n bipolar in the thin film devices. The drain avalanche can be enhanced by floating body in the thin film devices [6.12]. Figures 6.6 show the measured floating body induced drain avalanche currents of poly-Si TFTs with different channel thickness and (a) gate length = 1µm (b) ate length = 0.8µm. With increasing drain voltage, the added drain current enhances impact ionization and parasitic bipolar junction transistor (BJT) effect, which leads to a premature breakdown in return [6.15], [6.16]. In the Fig.6.6, we can control the drain voltage before strong drain avalanche breakdown for different gate length and channel thickness in program region. Thesemodified drain voltages are used to achieve high channel hot electron injection efficiency in the program region.
Table 6.1 is the split table of the applied drain biases with different gate length and channel thickness in the program region from measured results of Fig.6.6. The applied drain voltage can be reduced with short gate length and thick channel thickness.
6.3.3 Programming and Erasing Characteristics of Poly-Si TFT Nonvolatile Ge-NCs Memories
The measured transfer characteristics of poly-Si TFT nonvolatile Ge-NCs memories in the P/E states are shown in Fig.6.7. The memory windows of poly-Si TFT nonvolatile Ge-NCs memories with W / L = 0.8µm / 0.8µm can be larger than 7~8V for (a) channel thickness = 50-nm and (b) channel thickness = 100-nm. The threshold voltages VTH is defined as ID = W / L × 100nA. The memory window is the threshold voltages shift between erase state and program state.
Next, we apply the drain voltage before strong drain avalanche breakdown for different gate length and channel thickness in program region. According to Table 6.1, the memories with channel thickness = 50-nm and W / L = 1µm / 1µm are biased at VD = 11V, 12V in the program region. Figures 6.8 show the measured programming
characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness
= 50-nm and W / L = 1µm / 1µm in the program region biased at (a) VG = 10V, VD = 11V, 12V and (b) VG = 12V, VD = 11V, 12V. In the Fig.6.8, the program speed of VD
= 12V is faster than that of VD = 11V for (a) constant VG =10V or (b) constant VG
=12V. According to Table 6.1, the memories with channel thickness = 50-nm and W / L = 0.8µm / 0.8µm are biased at VD = 10V, 11V in the program region. Figures 6.9 display the measured programming characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 50-nm and W / L = 0.8µm / 0.8µm in the program region biased at (a) VG = 10V, VD = 10V, 11V and (b) VG = 12V, VD = 10V, 11V. When gate length is scaled down to 0.8µm, the drain voltage is also scaled down to VD = 10V, 11V. The program speed of VD = 11V is faster than that of VD = 10V for (a) constant VG =10V or (b) constant VG =12V.
According to Table 6.1, the memories with channel thickness = 100-nm and W / L
= 1µm / 1µm are biased at VD = 10V, 11V in the program region. Figures 6.10 show the measured programming characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness = 100-nm and W / L = 1µm / 1µm in the program region biased at (a) VG = 10V, VD = 10V, 11V and (b) VG = 12V, VD = 10V, 11V. In the Fig.6.10, the program speed of VD = 11V is faster than that of VD = 10V for (a) constant VG =10V or (b) constant VG =12V. According to Table 6.1, the memories with channel thickness = 100-nm and W / L = 0.8µm / 0.8µm are biased at VD = 9V, 10V in the program region. Figures 6.11 display the measured programming characteristics of poly-Si TFT nonvolatile Ge-NCs memories with channel thickness
= 100-nm and W / L = 0.8µm / 0.8µm in the program region biased at (a) VG = 10V, VD = 9V, 10V and (b) VG = 12V, VD = 9V, 10V. When gate length is scaled down to 0.8µm, the drain voltage is also scaled down to VD = 9V, 10V. The program speed of VD = 10V is faster than that of VD = 9V for (a) constant VG =10V or (b) constant VG
=12V.
Table 6.2 is the program efficiency of poly-Si TFT nonvolatile Ge-NCs memories for different gate length and channel thickness in program region. The program efficiency can be significantly enhanced with increased VD. In the Table 6.2, the program VTH shifts are almost twice in program region for same gate length and
Table 6.2 is the program efficiency of poly-Si TFT nonvolatile Ge-NCs memories for different gate length and channel thickness in program region. The program efficiency can be significantly enhanced with increased VD. In the Table 6.2, the program VTH shifts are almost twice in program region for same gate length and