Thesis Organization - 應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究

Chapter 1 Introduction

1.5 Thesis Organization

This thesis is organized as follow:

In Chapter 1, the overview of poly-Si TFTs and applications of Ni-silicidation and germanium in poly-Si TFTs are described.

In Chapter 2, a self-aligned Schottky barrier source and ohmic body contact (SSOB) method was proposed to contact the body terminal of poly-Si TFTs and form the silicided source applicable to technologies that incorporate self-aligned silicide cladded junctions. The new structure provides a very effective body contact to suppress all undesirable floating-body effects. Various device parameters such as subthreshold characteristics, output characteristics, and breakdown voltage are compared with conventional poly-Si TFTs.

In Chapter 3, the n-channel and p-channel fully Ni- self-aligned silicided (fully Ni-salicided) source/drain and gate poly-Si thin-film transistors (n-channel and p-channel FSA-TFTs), whose source/drain and gate layer are completely silicided with Ni, have been successfully fabricated on a 40-nm thick channel layer. The low-resistance fully Ni-salicided source/drain and gate allow a significant recovery of the intrinsic characteristics of thin-channel TFTs. We found that the measured characteristics of FSA-TFTs significantly suppressed floating-body and parasitic BJT effects. Threshold voltage (V_TH) difference between in-situ n⁺doped gate and undoped gate n-channel FSA-TFTs was also discussed in this chapter.

In Chapter 4, the novel symmetric vertical channel poly-Si TFTs fabricated by Ni-silicide induced lateral crystallization technology (NSILC-VTFTs) were investigated. The NSILC-VTFTs were fabricated by combining NSILC process and

vertical poly-Si channel. The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. In the dual-gate devices, a n⁺ floating region is included in the channel region between S/D. The Ni-accumulation and grain boundaries induced from S/D sides can be centralized in the n⁺ floating region. The dual-gate structure is employed to eliminate the grain boundaries perpendicular to the current flow in the channel. In this work, the effects of grain boundaries in the vertical channel and n⁺ floating region crystallized by NSILC or MILC processes are studied.

The NSILC-VTFTs can eliminate metal contaminations on source and drain region due to the limited Ni source from Ni-silicided seeding window arranged on source and drain contact holes. When the device Lmask and Wmask are scaled down, the probability of the channel region in NSILC-VTFTs to cover grain boundaries in the length and width direction decreases significantly. The NSILC-VTFTs with small L_mask and W_mask have better device performance and higher uniformity. Furthermore, we have discovered that amorphous silicon was crystallized by two steps: first step lateral crystallization at 500°C for 12hr and second step rapid thermal annealing (RTA) at 700°C for 60-sec, the grain size of the resulting poly-Si can be significantly enhanced and device characteristics can be further improved. In order to investigate the impact of grain boundaries in the vertical channel and n⁺ floating region, all the devices were fabricated without further NH₃ plasma treatment. The measured results show the NSILC-VTFTs without NH3 plasma treatment have high field-effective mobility, small subthreshold swing (S.S.), and low off-state leakage current.

In Chapter 5, the novel self-aligned Si / Ge T-gate poly-Si TFTs (Si / Ge T-gate TFTs) were proposed and demonstrated. The Si / Ge T-gate was formed by selective wet etching of Ge gate layer. The Ge regions etched at the gate edges were refilled by low-pressure chemical vapor deposition tetraethoxysilane (LPCVD TEOS) oxide in the passivation process. The thick gate oxide layer at the gate edges and the

passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, LDD, spacer, and sub-gate bias. The lateral electric field within the channel can be lowered by using the lateral selective etching of Ge within the gate stack at the gate edges without extra fabrication cost in the Si / Ge T-gate TFTs. The Si / Ge T-gate TFTs have a reduced OFF-state leakage current at negative voltages, an improved ON / OFF current ratio, and a smaller drain conductance in saturation due to a reduced impact ionization at the drain end of the channel compared with conventional TFTs.

In Chapter 6, the new poly-Si TFT nonvolatile Ge-NCs memories with low temperature annealing were proposed. The Ge-NCs embedded in oxide were formed by low-pressure chemical vapor deposition (LPCVD) at 370°C [6.10]. The size and density of Ge-NCs can be easily controlled by GeH₄ deposition time and flow rate.

Furthermore, the programming / erasing (P/E) characteristics of thin film nonvolatile memory devices (SOI and TFTs) with floating body effect have been investigated. We find that drain voltage is the key point to improve P/E efficiency in thin film nonvolatile memory devices. The mechanism is due to the floating body induced drain avalanche with parasitic n-p-n bipolar in the thin film devices. The drain voltage needs to adjust with different gate length and different channel thickness. We can reduce the applied drain voltage to achieve higher P/E efficiency by this floating body effect compared with bulk memory devices.

Finally, conclusions as well as recommendation for further research are given in Chapter 7.

Chapter 2 Suppression of the Floating-Body Effect in Poly-Si Thin-Film Transistors with Self-Aligned

Schottky Barrier Source and Ohmic Body Contact Structure

2.1 Introduction

Polycrystalline silicon thin-film transistors (poly-Si TFTs) are key devices in active-matrix liquid crystal displays (AMLCDs). Due to the relatively-large field-effect mobilities in both n- and p-channel devices, poly-Si TFTs can be used to incorporate the integrated driving circuits in AMLCDs [2.1]. Recently, poly-Si TFTs are suitable for the pixel driving elements of active matrix organic light emitting diode (AM-OLED) [2.2], and the driving TFTs with a high output resistance are desirable.

However, the output characteristics exhibit an anomalous current increase in the saturation regime, often called “kink” effect [2.3], [2.4] due to an analogy with silicon- on-insulator (SOI) devices [2.5]. This phenomenon can be attributed to the floating- body effect [2.6] and the avalanche multiplication enhanced by grain boundary-traps [2.7]. The avalanche multiplication is caused by the high drain electric field and the presence of grain boundaries and traps enhances the kink effect in poly-Si TFTs [2.7]. The added drain current enhances impact ionization which leads to a premature breakdown in return [2.6]. Several structures such as lateral body

terminal (LBT) [2.8], low-barrier body-contact (LBBC) [2.9], and Schottky body contact [2.10] have been reported in order to reduce the kink current. However, LBT needs additional terminal for the body bias; LBBC needs additional implantation processes and thicker channel thickness for the body contact; and the high forward bias turn on voltage of Schottky diode was reported using Schottky body contact.

Among these structures, Schottky barrier MOSFETs (SB-MOSFETs) are thought to have some advantages over conventional MOSFETs, such as the reduction of parasitic resistance and capacitance, and the immunity to the short channel [2.11], latch-up, or silicon-on- insulator floating-body effects [2.12].

In this chapter, we have developed a self-aligned Schottky barrier source and ohmic body contact (SSOB) method for contacting the body terminal of poly-Si TFTs and forming the silicided source applicable to technologies that incorporate self-aligned silicide cladded junctions. The new structure provides a very effective body contact to suppress all undesirable floating-body effects. Various device parameters such as subthreshold characteristics, output characteristics, and breakdown voltage are compared with conventional poly-Si TFTs.

2.2 Experiment

The key processes to fabricate the SSOB-TFTs are shown in Fig. 2.1 First, a 50-nm or 100-nm amorphous silicon (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C on oxidized silicon wafers. Next, the a-Si layer was then recrystallized by solid phase crystallization (SPC) at 600°C for 24-hr. After the active region patterning, a 50-nm gate oxide layer was deposited by high-density plasma chemical vapor deposition at 350°C. Subsequently, a 150-nm in-situ n⁺doped a-Si layer and a 150-nm Si₃N₄ hard mask layer were deposited by

LPCVD. After defining gate electrode, the remaining oxide on source/drain regions was removed by diluted HF. A mask was used to perform the n⁺drain-side implantation with P⁺ to dose 5 × 10¹⁵cm^-2and energy 18 keV for channel thickness = 50-nm (energy 30 keV for channel thickness = 100-nm) (Fig. 2.1a). A 250-nm oxide sidewall spacer was formed by deposition and etching of TEOS oxide. A similar mask was used to perform the p⁺doped body-contact BF2 implantation with dose 5 × 10¹⁵ cm^-2and moderate energy 35 keV for channel thickness = 50-nm (energy 50 keV for channel thickness = 100-nm).This implantation serves to form a p⁺ junction below the Schottky barrier source for ohmic body contact and also improves the conductivity at the bottom of the source for better body current collection simultaneously (Fig. 2.1b).

Meanwhile, only source- side oxide spacer was removed by buffered oxide etch (BOE). After removing the photoresist of body-contact mask, the Si3N4 hard mask layer was then selectively etched in a hot phosphoric acid bath. A second 25-nm oxide sidewall spacer was again formed by deposition and etching of TEOS oxide. Dopants were activated by rapid thermal annealing (RTA) at 750°C for 20-sec. A Ni film of about 10-nm was deposited by sputtering after a dilute HF-dip and then Ni-salicidation was carried out at 500°C for 30-sec by one-step RTA in the N₂ ambient.

Unreacted Ni was removed in H2SO4 : H2O2 solution. The Schottky barrier source was formed by the Ni-salicidation (Fig. 2.1c). After contact and metallization processes, the resultant poly-Si TFT with SSOB was shown in Fig. 2.1d. Conventional devices with self-aligned n⁺ source/drain and without Ni-salicidation were also fabricated to serve as control ones. No further hydrogenation (NH3 plasma treatment) procedures were implemented after sintering at 400 °C for 30 min.

2.3 Results and Discussion

2.3.1 n

⁺

Drain - p

⁺

Source Poly-Si TFTs Structure

Figure 2.2 shows the measured transfer characteristics of the n⁺drain - p⁺source poly-Si TFTs without Ni-salicidation. The limited drain current is caused by tunneling current between the inversion layer and the p⁺ source [2.13]. When gate voltage is increased, the drain current is limited by the p⁺ source.

The measured transfer characteristics of the conventional and the SSOB-TFTs with W / L = 50µm / 5µm are shown in Fig. 2.3. The off-state leakage currents in the conventional TFTs are slightly higher than that in the SSOB-TFTs. The SSOB-TFTs and conventional TFTs are the approximate on-state currents. Figure 2.3 also displays that the threshold voltages VTH (defined as ID = W / L × 100nA) of SSOB-TFTs are more stable than these of conventional TFTs at small V_DS= 0.5V and large V_DS= 5V.

Since the hole accumulation at the channel increases the body potential and lowers the junction barrier at the source region, a large number of hole carrier may be collected by the source. The leakage current is the sum of the electron current by field-emission at the drain region and the hole current caused by p-n forward bias at source [2.8].

With this ohmic body contact, the hole accumulation in the body and parasitic bipolar effects can be eliminated, resulting in a stable V_TH [2.9], [2.14] and lower off-state leakage current in the SSOB-TFTs [2.15]. The benefit of the SSOB-TFTs also can be found on subthreshold swing (S.S.). The S.S. of the conventional and the SSOB-TFTs are about 1230 mV/dec. and 1100 mV/dec., respectively. We believe that it may be due to the shallow silicided source junction and p⁺ junction in the SSOB-TFTs.

The measured output characteristics of the conventional and the SSOB-TFTs are shown in Fig. 2.4. The kink effect of the SSOB-TFTs is considerably reduced compared with the conventional TFTs. Under high drain voltage, excessive holes are accumulated at the body region and the drain breakdown is reduced by the floating-body effect in the conventional TFTs [2.16], [2.17]. This hole accumulation

causes a profound kink effect, which in turn deteriorates the output characteristics and induces parasitic bipolar transistor action [2.18], [2.19]. Since the SSOB-TFTs effectively collect the hole current generated by impact ionization, the floating-body effect is significantly suppressed and breakdown voltage is increased.

2.3.2 p

⁺

Drain - n

⁺

Source Poly-Si TFTs Structure

Figure 2.5 demonstrates the output characteristics of the p⁺drain - n⁺source poly - Si TFTs without Ni-salicidation. The output characteristics exhibit a turn-on voltage of the drain-diode [2.20]. The drain voltage offset is approximately 0.5V~0.6V. The drain voltage offset is considered to arise from the barrier formed between the p⁺ drain and n⁺ inversion layer.

To prove asymmetric S/D embedded in our SSOB structure, devices were measured again with interchanged S/D, i.e., Schottky drain TFTs with Schottky barrier drain and n⁺ source. Figure 2.6 shows the transfer characteristics of the Schottky drain and the SSOB-TFTs with W / L = 50µm / 5µm. Notably, the subthreshlod and on-state transfer characteristics for both devices are almost the same, except for gate-induced-drain-leakage (GIDL)-like currents when V_G was at negative bias. Normally, GIDL-like currents were often found for Schottky drain TFTs due to holes tunneling to the channel from drain metal silicide [2.21]. The GIDL-like currents become significant at the stronger accumulation region and higher drain voltage in the Schottky drain TFTs. This GIDL-like current can be three-order of magnitude reduced by the n⁺ drain in the SSOB-TFTs.

The measured output characteristics of the Schottky drain TFTs and the SSOB-TFTs are shown in Fig. 2.7. The kink effect of the SSOB-TFTs is considerably reduced compared with the Schottky drain TFTs. Figure 2.7 also indicates that the output characteristics of the Schottky drain TFTs have a small finite drain voltage

offset (V_D offset < 0.5V) which is considered to arise from the Schottky barrier formed between the Schottky barrier drain and n⁺ inversion layer [2.22]. The low breakdown voltage (V_D ~ 15 V) and kink-like current for Schottky drain TFTs may result from the inherent p-i-n diode forward biased at VD > 0V.

2.3.3 SSOB-TFTs at Different Negative Source Voltage

The measured output characteristics of the conventional and the SSOB-TFTs at different negative source voltage are shown in Fig. 2.8 and Fig. 2.9 with channel thickness = 100-nm and channel thickness = 50-nm, respectively. The kink effect of the SSOB-TFTs is considerably reduced compared with the conventional TFTs at different negative source voltage. When the source voltage is more negative, the source to body junction is more forward bias and kink effect is more serious in conventional TFTs [2.19], [2.20].

2.4 Summary

We have developed a self-aligned SSOB structure for poly-Si TFTs to provide an effective body contact and suppress the floating-body effect. The GIDL-like currents occurred in the Schottky drain TFTs are reduced by the SSOB-TFTs. This SSOB-TFTs show reduced kink effect and increased breakdown voltage and are suitable for driving circuit application for high voltage gain.

Fig. 2.1 The key processes of the SSOB-TFTs, (a) n⁺drain-side implantation, (b) p⁺ body-contact implantation, (c) Ni-salicidation and Schottky barrier source formation, (d) The poly-Si TFTs with SSOB after contact and metallization processes.

(a) (b)

Fig. 2.2 The transfer characteristics of the n⁺drain - p⁺source poly - Si TFTs with channel thickness (a) 100nm and (b) 50nm before Ni salicidation. When gate voltage is increased, the drain current is limited by the p⁺ source.

(a)

n⁺Drain - p⁺Source W / L = 50µµµµm / 5µµµµm Channel Thickness = 100nm V_D = 0.5V, 5V

Gate Voltage V_G ( V )

0 5 10 15

Drain Current I D ( A )

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6

(b)

n⁺ D rain - p⁺ Source W / L = 50µµµµm / 5 µµµmµ C hannel T hickness = 50nm V_D = 0.5V , 5V

G ate Voltage V_G( V )

0 5 10 15

Drain Current I D ( A )

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6

Fig. 2.3 The transfer characteristics of the conventional and the SSOB - TFTs with channel thickness (a) 100nm and (b) 50nm. The SSOB-TFTs give low leakage currents and improved subthreshold characteristics compared with conventional TFTs.

(b)

C hannel T hickness = 100nm

V

= 0.5V , 5V

W / L = 5 0 µ µ µ m / 5 µ µ µ µ µ m (a ) C h a n n el T h ick n ess = 1 0 0 n m

V

- V

_{T H}

= 2 V , 4 V , 6 V

D ra in V o lta g e V

( V )

0 5 1 0 1 5 2 0

D r a in C ur re nt I

( m A )

0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6

S S O B - T F T s

C o n v en tio n a l T F T s

W /L = 5 0 µ µ µ µm / 5 µ µ µ µm (b ) C h ann el T h ickness = 50nm

V

- V

_{T H}

= 2V , 4V , 6V

D ra in V oltag e V

( V )

0 5 10 15 20

D ra in C ur r e n t I

( m A )

0 .00 0 .05 0 .10 0 .15 0 .20 0 .25 0 .30

S SO B - T F T s

C onv ention al T F T s

Fig. 2.4 The output characteristics of the conventional and the SSOB - TFTs with channel thickness (a) 100nm and (b) 50nm. Compared with conventional TFTs, SSOB-TFTs give reduced kink effect and increased breakdown voltage.

p

⁺

Drain - n

⁺

Source W / L = 50µ µ µ µm / 5µ µ µ µm Channel Thickness = 50nm V

-V

_TH

= 2V, 3V, 4V (V

offset = 0.5V)

Drain Voltage V

( V )

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

D ra in C u rren t I

(

µµµµ

A )

0 10 20 30 40 50

V

offset

Fig. 2.5 The output characteristics of the the p⁺drain - n⁺source poly - Si TFTs with channel thickness 50nm before Ni salicidation. The drain voltage offset is approximately 0.5V.

W / L = 50µ µ µ µm / 5µ µ µ µm Channel Thickness = 50nm V

= 0.5V, 5V

Gate Voltage V

( V )

-5 0 5 10 15

D r a in C ur r e nt I

( A )

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

SSOB -TFTs

Schottky Drain TFTs

Fig. 2.6 The transfer characteristics of the Schottky drain and the SSOB - TFTs with channel thickness 50nm. The large GIDL-like current is due to Schottky barrier drain.

W / L = 50µ µ µ µm / 5µ µ µm µ Channel Thickness = 50nm V

-V

_TH

= 3V, 4V, 5V

Drain Voltage V

( V )

0 1 2 3 4 5 6 7 8 9 1011121314151617181920 D ra in C u rr en t I

( mA )

0.00 0.05 0.10 0.15 0.20 0.25 0.30

SSOB -TFTs

Schottky Drain TFTs ( small V

offset )

Fig. 2.7 The output characteristics of the Schottky drain and the SSOB - TFTs with channel thickness 50nm. The Schottky drain TFTs have a small drain voltage offset (<

0.5V).

(a)

channel thickness 100nm at different negative source voltage. When the source voltage is more negative, the source to body junction is more forward bias and kink effect is more serious in conventional TFTs.

(a)

Fig.2.9 The output characteristics of (a) the SSOB - TFTs and (b) the conventional TFTs with channel thickness 50nm at different negative source voltage. When the source voltage is more negative, the source to body junction is more forward bias and kink effect is more serious in conventional TFTs.

Chapter 3 Characteristics of n-Channel and p-Channel Fully Ni-Self-Aligned Silicided S/D and Gate

Poly-Si Thin-Film Transistors

3.1 Introduction

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in many potential applications including 3D integration high density flash memories, pixel driving elements of active matrix organic light emitting diode (AM-OLED), and integrated peripheral driving circuits and addressing elements of active-matrix liquid crystal displays (AMLCDs) [3.1]-[3.4].

However, the output characteristics exhibit an anomalous increase of current in the saturation regime, often called “kink” effect due to an analogy with silicon-on-insulator (SOI) devices [3.5]-[3.7]. This phenomenon can be attributed to the floating-body effect [3.8] and the avalanche multiplication enhanced by grain boundary-traps [3.6], particularly in n-channel TFTs. With increasing drain voltage, the added drain current enhances impact ionization and parasitic bipolar junction transistor (BJT) effect, which leads to a premature breakdown in return [3.8]. In the floating-body thin-film devices, the improved parasitic BJT effect can be achieved by using deep salicidation and fully silicided source/drain structure [3.9], [3.10].

Due to low hole field-effect mobility, p-channel TFTs have lower on-state current compared with n-channel TFTs. Nevertheless, the p-channel TFTs have some

advantages, such as low off-state leakage current, slight floating-body effect and kink effect, weak drain impact ionization and high hot carrier reliability. In addition, the thin-channel poly-Si TFTs have the improved device characteristics such as small leakage current and suppressed floating-body effect compared with the thick-channel poly-Si TFTs [3.11]. Thin channel film also leads to increased source and drain parasitic resistance. The parasitic S/D resistances become increasingly a serious issue in the thin-channel poly-Si TFTs and SOI devices. Several methods such as self-aligned silicide, selective tungsten-clad and metal-replaced junction technology were proposed to reduce parasitic S/D resistance for thin-channel SOI devices and poly-Si TFTs [3.12]-[3.15]. Furthermore, silicided and metal gates have a higher capacitance than poly-Si gates due to the elimination of poly-Si depletion [3.16]. The field-effect mobility and on-state current can be improved by reducing parasitic S/D resistance and increasing gate capacitance [3.14], [3.15].

In this chapter, the n-channel and p-channel fully Ni- self-aligned silicided (fully Ni-salicided) source/drain and gate poly-Si thin-film transistors (n-channel and p-channel FSA-TFTs), whose source/drain and gate layer are completely silicided with Ni, have been successfully fabricated on a 40-nm thick channel layer [3.17]. The low-resistance fully Ni-salicided source/drain and gate allow a significant recovery of the intrinsic characteristics of thin-channel TFTs. We found that the measured characteristics of FSA-TFTs significantly suppressed floating-body and parasitic BJT effects. Threshold voltage (V_TH) difference between in-situ n⁺doped gate and undoped gate n-channel FSA-TFTs was also discussed in this chapter.

3.2 Experiment

Figure 3.1 shows the main fabrication process steps of FSA-TFTs. First, a 40-nm

amorphous silicon (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C on oxidized silicon wafers. Next, the a-Si layer was then crystallized by solid phase crystallization (SPC) at 600°C for 24-hr. After the

在文檔中應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究 (頁 32-0)