Comparison of NSILC-VTFTs and NSILC-VTFTs (RTA)

Chapter 4 Novel Symmetric Vertical n-Channel Poly-Si Thin-Film Transistors

4.3.6 Comparison of NSILC-VTFTs and NSILC-VTFTs (RTA)

Figure 4.14 displays the transfer characteristics of the NSILC-VTFTs and NSILC-VTFTs (RTA) with W_mask / L_mask = 0.8µm / 0.8µm. The NSILC-VTFTs (RTA) have steeper S.S., and larger on-state current compared with NSILC-VTFTs. The second step RTA is performed on the NSILC-VTFTs to further improve the device characteristics. Secondary grain crystallization by the second step RTA is the process responsible for the grain size enhancement and crystal integrity improvement [4.11]-[4.13].

In this chapter, the reduction of Wmask is more important for getting a single grain TFT. The transfer characteristics of the NSILC-VTFTs (RTA) with constant W_mask= 0.8µm and different L_mask are shown in Fig.4.15. The NSILC-VTFTs (RTA) with Wmask / Lmask = 0.8µm / 0.8µm have the smallest S.S. and the largest on-state current.

When the Lmask is decreasing, the series resistance of n⁺ floating region is decreasing.

The high on-state current of NSILC-VTFTs (RTA) with short L_mask is due to the low series resistance in the n⁺ floating region.

Table 4.5 is summary of measured devices parameters from NSILC-VTFTs (RTA) with constant W_mask= 0.8µm and different L_mask. The S.S. characteristics and field effect mobility can be improved significantly with L_mask scaling down. The NSILC-VTFTs (RTA) with W_mask / L_mask = 0.8µm / 0.8µm have the smallest S.S., the highest field effect mobility. The second step RTA can be utilized to enhance the grain size significantly in both the length and the width direction. Furthermore, the NSILC-VTFTs (RTA) with Wmask / Lmask = 0.8µm / 5µm have the lowest Ioff current and largest Ion / Ioff current ratio. The grain size of the n⁺ floating region can be enhanced by the second step RTA and the grain boundary induced leakage current can be suppressed by the secondary grain crystallization [4.12]. The NSILC-VTFTs (RTA)

are equivalent to dual-gate device structures. It can suppress the electrical field in the drain depletion region, significantly reducing the leakage current of the, increasing the Ion / Ioff current ratio [4.9], [4.14]. In the NSILC-VTFTs (RTA), the off-state leakage can be improved by increasing appropriate Lmask. The poor electrical characteristics of NSILC-VTFTs with a long Lmask =10µm is due to the large series resistance in the n⁺ floating region.

4.4 Summary

The novel symmetric vertical channel poly-Si TFTs fabricated by NSILC technology have been proposed to fabricate the high performance TFTs. The NSILC-VTFTs have the symmetric S/D structure without additional MILC window mask. NSILC process can reduce metal contaminations and improve poly-Si TFTs characteristics. One step NSILC (500^oC, 12-hr) is controlled to study the effects of grain boundaries on the vertical channel and n⁺ floating region. The NSILC-VTFTs with small Wmask and Lmask have improved device characteristics due to less poly-Si grain boundaries. Two step NSILC (1_th step: 500^oC, 12-hr and 2_th step: RTA 700^oC, 60-sec.) has been introduced to enhance the grain size and improve the crystal integrity through secondary recrystallization. Significant improvements in TFT performance have been observed even for large devices with multiple grains in the channel. The novel NSILC-VTFTs without NH₃ plasma treatment have good S.S.

characteristics, low off-state leakage current and high field-effective mobility.

p type Si-sub

(a) The MILC-VTFTs were fabricated without RTA Ni-silicidation processes. In the NSILC-VTFTs, The Ni-silicidation of NSILC was achieved by RTA at 450 ^oC for 30 sec before lateral crystallization.

Unreacted Ni was removed in H₂SO₄: H₂O₂ solution after RTA Ni-silicidation processes.

(b) Crystallized poly-Si after NSILC and MILC at 500^oC for 12hr.

p type Si-sub

S/D Self-Aligned Ion Implantation contact, and metallization processes, all the devices were fabricated without NH3 plasma treatment for studying influences of grain boundaries in the vertical channel and n⁺ floating region.

Fig. 4.1 The key process flows of NSILC-VTFTs and MILC-VTFTs.

500 ° C, 12hr

Table 4.1 The split table of the devices. The NSILC-VTFTs and MILC-VTFTs were only crystallized by first step lateral crystallization (500°C for 12hr). The NSILC-VTFTs (RTA) were crystallized by first step lateral crystallization (500°C for 12hr) and second step RTA (700°C for 60sec). In order to investigate the impact of grain boundaries in the channel crystallized by NSILC or MILC processes, no further NH3 plasma treatment procedure was implemented in our experiment.

Fig.4.2 The schematic device cross-section structure of NSILC-VTFTs. The NSILC-VTFTs are equivalent to dual-gate device structures. The effective channel length of NSILC-VTFTs is defined by thickness of poly-Si gate and gate oxide.

n

⁺

Source n

⁺

Floating Region n

⁺

Drain Gate

n

⁺

Source n

⁺

Floating Region n

⁺

Drain Gate

1/2 L_eff 1/2 L_eff

L_mask

p type Si-sub Wet Oxide

Gate Oxide

n⁺Drain n⁺Source

n⁺ Floating Region

Vertical Channel Vertical Channel

n⁺ Poly-Si Gate

1/2 L_eff 1/2 L_eff

L_mask

p type Si-sub Wet Oxide

Gate Oxide

n⁺Drain n⁺Source

n⁺ Floating Region

Vertical Channel Vertical Channel

n⁺ Poly-Si Gate

⁺⁺

Floating Region Floating Region

n n

⁺⁺

S/D Region S/D Region Gate Oxide 500 Gate Oxide 500Å Å

Wet Oxide Wet Oxide

2500 2500 Å Å

Undercut 1000 Undercut 1000 Å Å

n n

⁺⁺

Poly- Poly -Si Si Gate Gate Vertical Poly

Vertical Poly - - Si Si Channel 500 Channel 500Å Å

n n

⁺⁺

Floating Region Floating Region

n n

⁺⁺

S/D Region S/D Region Gate Oxide 500 Gate Oxide 500Å Å

Wet Oxide Wet Oxide

2500 2500 Å Å

Undercut 1000 Undercut 1000 Å Å

(a)

(b)

(a) MILC, 500 ^o C, 24hr

(b) NSILC, 500 ^o C, 12hr

Fig. 4.5 (a) The plan view optical microscope microphotograph of test key after MILC process at 500°C for 24hr and (b) the plan view optical microscope microphotograph of test key after NSILC process at 500°C for 12hr. The Ni accumulation of grain boundaries is found in the MILC process but it is not found in the NSILC process.

Gate

Source Drain

0 10µ µ µ µm

Ni accumulation

Gate

Source Drain

0 10µ µ µ µm

Ni accumulation

(a) MILC-VTFTs

10µ µ µ µm 0

Gate

Source Drain

10µ µ µ µm 0 10µ 10µ µ µ µm µ µ µm 0

Gate

Source Drain

(b) NSILC-VTFTs

Fig.4.6 (a) The plan view optical microscope microphotograph of MILC-VTFTs after annealing at 500°C for 12hr and (b) the plan view optical microscope microphotograph of NSILC-VTFTs after annealing at 500°C for 12hr. The Ni accumulation of the n⁺ floating region is found in the MILC-VTFTs but it is not found in the NSILC-VTFTs.

V

=0.1V, L

_{e f f}

= 0.6µ µ µm µ Without NH

₃

Plasma Treatment

-2 0 2 4 6 8 10 12 14 16 18 20

Dr ai n Cu rr en t I

( A )

_{e f f}

= 0.6µ µ µ µm W

_mask

/ L

_mask

= 0.8µ µ µ µm / 0.8µ µ µm µ Without NH

₃

plasma Treatment

Gate Voltage V

( V )

-2 0 2 4 6 8 10

D ra in C u rr e n t I

( A )

=0.6µ µ µ µm V

( V ) D r a in C u rr en t I

( A )

Fig.4.9 The transfer characteristics of NSILC-VTFTs with constant Lmask = 0.8µm and different Wmask. The effective channel length of NSILC-VTFTs is 0.6µm.

3.08x10 ⁶

the highest field effect mobility.

Ni Seeding Hole

Wide Channel Width (W

_mask

)

Narrow Channel Width (W

_mask

) Grain Boundary

Ni Seeding Hole

Wide Channel Width (W

_mask

)

Narrow Channel Width (W

_mask

) Grain Boundary

Fig.4.10 The illustration of Ni induced lateral crystallization in wide channel width (Wmask) and narrow channel width (Wmask).

Gate Voltage V

( V )

-2 0 2 4 6 8 10

_mask

=10µ µ µ µm

Without NH

₃

Plasma Treatment

Fig.4.11 The transfer characteristics of NSILC-VTFTs with constant Lmask =10µm and different Wmask. The effective channel length of NSILC-VTFTs is 0.6µm.

Gate Voltage V

( V )

effective channel length of NSILC-VTFTs is 0.6µm.

NSILC-VTFTs, L

_{e f f}

=0.6µ µ µm µ V

= 0.1V, W

_mask

=0.8µ µ µ µm Without NH

₃

Plasma Treatment

Gate Voltage V

( V )

-2 0 2 4 6 8 10

1.05x10 ⁶

the highest field effect mobility.

V

=0.1V, L

_{e f f}

= 0.6µ µ µ µm W

_mask

/ L

_mask

= 0.8µ µ µ µm / 0.8µ µ µ µm Without NH

₃

plasma Treatment

Gate VoltageV

( V )

-2 0 2 4 6 8 10

D ra in C u rr en t I

( A )

Fig.4.14 The transfer characteristics of the NSILC-VTFTs and NSILC-VTFTs (RTA) with W_mask / L_mask = 0.8µm / 0.8µm. The effective channel length is 0.6µm.

NSILC-VTFTs ( RTA )

V

= 0.1V, L

_{e f f}

=0.6µ µ µ µm, W

_mask

=0.8µ µ µ µm Without NH

₃

Plasma Treatment

Gate Voltage V

( V )

-2 0 2 4 6 8 10

8.6x10 ⁶

constant W_mask= 0.8µm and different L_mask. The effective channel length of NSILC-VTFTs (RTA) is 0.6µm. The NSILC-TFTs (RTA) with W_mask / L_mask = 0.8µm / 0.8µm have the highest field effect mobility. The NSILC-TFTs (RTA) with W_mask / L_mask = 0.8µm / 5µm have the largest Ion / Ioff current ratio.

Chapter 5 Characteristics of Self-Aligned Si / Ge T-Gate Poly-Si Thin-Film Transistors with High

ON/OFF Current Ratio

5.1 Introduction

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in many potential applications including high density flash memories, active matrix organic light emitting diode (AM-OLED), and active-matrix liquid crystal displays (AMLCDs) [5.1]-[5.4]. Poly-Si TFTs are considered to be promising devices for display system-on-panel applications [5.5].

However, the large OFF-state leakage current and device instability of poly-Si TFTs are hindrances to the high-performance and high reliability circuit applications.

It is well known that the dominant mechanism of the OFF-state leakage current is the field emission via grain boundary traps due to a high electric field in the drain depletion region. The leakage current is increased with increasing gate and drain voltages which enhance the field emission via grain boundary traps in the depletion region near the drain [5.6], [5.7]. In order to increase the reliability and reduce the leakage current, poly-Si TFTs with offset gated, lightly doped drain (LDD), gate-overlapped LDD, floating gate spacer, air cavities, or field-induced drain (FID) structures have been suggested to reduce the electric field near the drain [5.8]-[5.14].

In this chapter, the novel self-aligned Si / Ge T-gate poly-Si TFTs were proposed

and demonstrated. The Si / Ge T-gate was formed by selective wet etching of Ge gate layer. The Ge regions etched at the gate edges were refilled by low-pressure chemical vapor deposition tetraethoxysilane (LPCVD TEOS) oxide in the passivation process.

The thick gate oxide layer at the gate edges and the passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, LDD, spacer, and sub-gate bias. The lateral electric field within the channel can be lowered by using the lateral selective etching of Ge within the gate stack at the gate edges without extra fabrication cost in the Si / Ge T-gate TFTs. The Si / Ge T-gate TFTs have a reduced OFF-state leakage current at negative voltages, an improved ON / OFFcurrent ratio, and a smaller drain conductance in saturation due to a reduced impact ionization at the drain end of the channel compared with conventional TFTs.

5.2 Device Structure Design and Simulation 5.2.1 Si / Ge T-gate Structure Design

Figure 5.1 shows the schematic cross-sectional device structures of (a) Si / Ge T-gate TFTs and (b) conventional TFTs. Both devices have the same photo-mask gate length and perform the same S / D implantation condition. The experimental split table of Si / Ge T-gate TFTs and conventional TFTs is defined in Table I. In Si / Ge T-gate TFTs, the thickness of thick gate oxide layer at the gate edges are controlled by the thickness of Ge gate layer (50-nm and 100-nm) and the Ge lateral undercut distances (400-nm and 800-nm) are controlled by the time of selective wet etching.

For example, the Si / Ge 50nm T-gate TFTs (400nm) have a 150-nm / 50-nm stacked Si / Ge gate layer and a 400-nm Ge lateral undercut distance. The total thickness of

stacked Si / Ge gate layer is 200-nm for all devices.

The Si / Ge T-gate TFTs can reduce the vertical electric field near the drain due to the thick gate oxide layer at the gate edges [5.12]. The poly-Si region under thick gate oxide can be considered as an offset region and the gate edge over the thick gate oxide serve as a field plate connected with the gate, so that the proposed TFTs operate like field-induced drain TFTs ( FID TFTs ) except a sub-gate bias [5.13]. In the OFF-state, the lateral electric field near the drain can be reduced due to the thick gate oxide layer at the gate edges [5.12]. In the ON-state, a sufficient inversion layer can be induced by the thick gate edge oxide near the source [5.14].

5.2.2 Lateral Electric Field Simulation in Si / Ge T-gate TFTs

In order to demonstrate the reduction in drain lateral electric field in the Si / Ge T-gate TFTs. The electric fields in the TFTs were simulated by using a commercial two-dimensional (2-D) numerical simulator for semiconductor devices. Figures 5.2 show the simulated lateral electric field distribution along the channel / gate oxide interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiN_X passivation at V_G= 0 V and V_D= 15 V. Figures 5.3 show the simulated lateral electric field distribution along the channel / gate oxide interface for conventional TFTs and Si / Ge T-gate TFTs with (a) TEOS passivation and (b) SiN_X passivation at VG = -10 V and VD = 10 V. The simulated result demonstrates that lateral electric field near the drain can be effectively reduced by the Si / Ge T-gate structure. The high κ gate dielectric SiN_X at the gate edges in Si / Ge T-gate TFTs with SiN_X passivation have larger the lateral drain electric field compared with Si / Ge T-gate TFTs with TEOS passivation. The Si / Ge T-gate TFTs with 100-nm Ge gate layer have the lowest lateral electric field near the drain due to the thickest gate oxide at the gate edges [5.12].

5.3 Experiment

Figure 5.4 shows the main fabrication process steps of Si / Ge T-gate TFTs. First, a 100-nm or 50-nm amorphous silicon (a-Si) layer was deposited by LPCVD at 550°C on oxidized silicon wafers and then was crystallized by solid phase crystallization (SPC) at 600°C for 24-hr. After the patterning of active region, a 50-nm TEOS gate oxide layer was deposited by LPCVD. Subsequently, a stacked a-Si / a-Ge gate layer was deposited by LPCVD at 550°C / 370°C. The thickness of thick gate oxide layer at the gate edges were controlled by the thickness of Ge gate layer (50-nm and 100-nm).

A phosphorus gate implantation with dose 5 × 10¹⁵cm^-2and energy 60keV was used to form the n⁺gate (Fig.5.4a). After defining gate electrode, the Si / Ge T-gate was formed by selective wet etching (H2O: H2O2 solution) of Ge gate layer at 75°C. The Ge lateral undercut distances (400-nm and 800-nm) of Si / Ge T-gate were controlled by the time of wet etching. Then, the remaining oxide on the S / D region was removed by diluted HF. A self-aligned phosphorusimplantation with dose 5 × 10¹⁵ cm^-2and energy 25keV was used to form the n⁺S / D (Fig.5.4b). The Ge undercut regions were refilled by LPCVD TEOS oxide or LPCVD SiN_X in the passivation process and dopants were activated by furnace at 600°C for 12-hr. After contact and metallization processes (Fig.5.4c), NH₃ plasma treatments were implemented after sintering at 400°C for 30-min. Conventional TFTs with self-aligned n⁺ S / D and TEOS passivation were also fabricated to serve as control ones.

5.4 Results and Discussion

5.4.1 Cross-Sectional TEM microphotograph of Si / Ge T-gate TFTs

Figure 5.5 shows the cross-sectional transmission electron microscope (TEM)

microphotograph of Si / Ge T-gate TFTs with TEOS passivation. The Si / Ge T-gate was successfully obtained on the gate oxide and the interfacial oxide was not observed in the stacked Si / Ge interface. The Si gate layer and Ge gate layer were inter-alloyed between the stacked Si / Ge interface due to subsequent processes annealing. The undercut regions were fully refilled by LPCVD TEOS oxide in the passivation process and the thickness of thick gate oxide at the gate edges were controlled by the thickness of Ge gate layer. In the Fig.5.5, the thickness of Ge gate layer is about 100-nm and the Ge lateral undercut distance of Si / Ge T-gate is about 400-nm. The poly-Si at the gate edges was bent upward by subsequent processes-induced thermal stresses. The bending poly-Si at the gate edges brings about gradual variation in thickness of gate oxide at the gate edges and the thickest gate oxide is near the drain. The vertical and lateral electric fields at drain can be effectively reduced by a thick gate oxide at the gate edges. In addition, the bending poly-Si at the gate edges can promote the refilling ability of LPCVD TEOS. Figure 5.6 illustrates the composition of pure Ge gate layer extracted from the energy dispersive x-ray spectrometer analysis. The pure Ge gate layer of Si / Ge T-gate can be easily etched by the wet etching H₂O: H₂O₂(100 : 1) solution at a low temperature of 75°C. The etching rate is about 2.5 nm/s.

5.4.2 Si / Ge T-gate TFTs with TEOS Passivation

Figures 5.7 exhibitthe measured transfer characteristics of conventional TFTs and Si / Ge T-gate TFTs with (a) W / L = 10 µm / 10 µm and (b) W / L = 10 µm / 5 µm.

The device channel thickness is 100-nm. The OFF-state leakage currents of Si / Ge T-gate TFTs are significantly lower than those of conventional TFTs. This is due to that the lateral electric field near the drain can be effectively reduced by the Si / Ge T-gate structure. Since the thick gate oxide at the gate edges greatly suppress the

lateral drain electric field, the anomalous OFF-state leakage currents of poly-Si TFTs can be controlled by the thickness of Ge gate layer and the Ge lateral undercut distances [5.14]. The Si / Ge_100nm T-gate (800 nm) TFTs have the lowest OFF-state leakage currents in the Si / Ge T-gate TFTs. The ON-state currents of Si / Ge T-gate TFTs are slightly lower than those of conventional TFTs. A sufficient inversion layer can be induced by the thick gate edge oxide near the source. For the Si / Ge T-gate TFTs, the ON-state currents are slightly reduced with increasing thickness of Ge gate layer and Ge lateral undercut distances. The Si / Ge50nm T-gate (400 nm) TFTs have the highest ON-state currents among the all Si / Ge T-gate TFTs.

Figure 5.8 displays the measured OFF-state leakage currents of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm for different drain biases at VG = -10 V. The device channel thickness is 100-nm. The OFF-state leakage currents of Si / Ge T-gate TFTs are significantly lower than those of conventional TFTs. The OFF-state leakage current is increased with increasing gate and drain voltages which enhance the field emission via grain boundary traps in the depletion region near the drain [5.6], [5.7]. In the Si / Ge T-gate TFTs, the lateral electric field near the drain can be greatly reduced due to the thick gate oxide layer at the gate edges and the OFF-state leakage currents are greatly decreased with increasing thickness of Ge gate layer and the Ge lateral undercut distances.

Figure 5.9 illustrates the measured ON / OFF current ratio of conventional TFTs and Si / Ge T-gate TFTs with W = 10 µm and different channel length. The device channel thickness is 100-nm. The ON / OFF current ratio is defined as the ratio of the ON-state current to the minimum OFF-state leakage current. The ON-state current is defined as drain current ( I D ) at VG = 20 V, VDS = 10 V and the minimum OFF-state leakage current is defined as minimum drain current ( I _min) at V_DS = 10 V. The Si / Ge T-gate TFTs not only reduce the OFF-state leakage current, but also maintain a high

ON-state current. The Si / Ge T-gate TFTs with 100-nm Ge gate layer have the highest ON / OFF current ratio than those with 50-nm Ge gate layer due to the lowest OFF-state leakage currents. On the other hand, the Si / Ge T-gate TFTs with 100-nm Ge gate layer can maintain a high ON-state current even though gate length is scaled down to 3 µm. Hence, to optimize the Si / Ge T-gate TFTs, the thickness of Ge gate layer should be considered first.

The Si / Ge T-gate TFTs are different from conventional FID TFTs. The conventional FID TFTs need an additional sub-gate electrode, a large sub-gate bias, and an additional sub-gate mask compared with Si / Ge T-gate TFTs. In addition, the conventional FID TFTs have the farther separation of n⁺ S / D junction compared with conventional TFTs. In the conventional FID TFTs with a SiO₂ interlayer, a typical sub-gate bias of more than 60V is necessary to obtain a high ON / OFF current ratio [5.13]. The Si / Ge T-gate TFTs and conventional TFTs were fabricated with the same photo-mask gate length and the same S / D implantation condition. The Si / Ge T-gate TFTs and conventional TFTs have the identical position of S / D junction. The Si / Ge T-gate TFTs only need one gate electrode to obtain a high ON / OFF current ratio.

Figure 5.10 displays the output characteristics of conventional TFTs and Si / Ge T-gate TFTs with W / L = 10 µm / 10 µm. The device channel thickness is 100-nm.

The Si / Ge T-gate TFTs have more saturated output characteristics compared with conventional TFTs. The kink current of Si / Ge T-gate TFTs is reduced considerably compared with that of conventional TFTs. The Si / Ge T-gate TFTs with 100-nm Ge gate layer have the most saturated output characteristics due to the lowest lateral

在文檔中應用鎳矽化物與鍺於新穎結構複晶矽薄膜電晶體之研究 (頁 84-0)

Comparison of NSILC-VTFTs and NSILC-VTFTs (RTA)

Chapter 4 Novel Symmetric Vertical n-Channel Poly-Si Thin-Film Transistors

4.3.6 Comparison of NSILC-VTFTs and NSILC-VTFTs (RTA)

4.4 Summary

p type Si-sub

p type Si-sub

500 ° C, 12hr

n

Source n

Floating Region n

Drain Gate

n

Source n

Floating Region n

Drain Gate

p type Si-sub Wet Oxide

p type Si-sub Wet Oxide

L

W

10µ µ µ µm 0

Gate

Source Drain

L

W

10µ µ µ µm 0 10µ µ µ µm 0

Gate

Source Drain

n n

Poly- Poly -Si Si Gate Gate Vertical Poly

Vertical Poly - - Si Si Channel 500 Channel 500Å Å

n n

Floating Region Floating Region

n n

S/D Region S/D Region Gate Oxide 500 Gate Oxide 500Å Å

Wet Oxide Wet Oxide

2500 2500 Å Å

Undercut 1000 Undercut 1000 Å Å

n n

Poly- Poly -Si Si Gate Gate Vertical Poly

Vertical Poly - - Si Si Channel 500 Channel 500Å Å

n n

Floating Region Floating Region

n n

S/D Region S/D Region Gate Oxide 500 Gate Oxide 500Å Å

Wet Oxide Wet Oxide

2500 2500 Å Å

Undercut 1000 Undercut 1000 Å Å

(a)

(b)

(a) MILC, 500 o C, 24hr

(b) NSILC, 500 o C, 12hr

Gate

Source Drain

0 10µ µ µ µm

Ni accumulation

Gate

Source Drain

0 10µ µ µ µm

Ni accumulation

(a) MILC-VTFTs

10µ µ µ µm 0

Gate

Source Drain

10µ µ µ µm 0 10µ 10µ µ µ µm µ µ µm 0

Gate

Source Drain

(b) NSILC-VTFTs

V

=0.1V, L

= 0.6µ µ µm µ Without NH

Plasma Treatment

-2 0 2 4 6 8 10 12 14 16 18 20

Dr ai n Cu rr en t I

( A )

10

10

10

10

10

10

(a) MILC, 500 ^o C, 24hr

(b) NSILC, 500 ^o C, 12hr

3.08x10 ⁶