Chapter 3 Low Power Double-Balanced Mixer
3.6 Summary
A 5-GHz double-balanced mixer is designed and fabricated in 0.18 CMOS technology. The circuit architecture is chosen available for the application of low supply voltage and low power consumption. The circuit consists a transconductance stage and PMOS switching pairs in a folded topology. Phase splitting function is integrated in the transconductance stage, which is composed of a common gate and common source transistors to save power consumption and to benefit from the double–balanced topology. Output balanced condition and noise of the transconductance stage are analyzed.
The measured input return loss and voltage conversion gain are 11dB and 10.4dB, respectively. The input third-order intercept point (IIP3) is 3.8dBm while consuming only 2mW from a 1V supply. Table I summaries the measured results of this work and compares the performance with other two circuits. Among these, [12] is a differential input mixer, and the power consumption must be increased since a phase splitting stage has to be added for single-ended input. As compared to the two circuits, this work has comparable gain and linearity while consuming the lowest power and lower supply voltage.
TABLE 3.1
Summary of measured performance and comparison to other mixers.
Item This Work Ref[10] Ref[12]
Technology CMOS 0.18um CMOS 0.18um CMOS 0.18um
RF Frequency (GHz) 5.5 2.4 2.4
DC Supply Voltage (V) 1.0 1.8 1
LO power (dBm) 2 - 0.5 Vp
Conversion Gain (dB) 10.4 16.5 11.9
IIP3 (dBm) 3.8 9 -3
Noise Figure (dB) 9.9 (simulate) 14.2 (DSB) 13.9 (SSB)
Power Dissipation (mW) 2 5.4 3.2
Chapter 4
Low-Power Front-End Circuit
4.1 IntroductionTo meet the low supply voltage requirement, the conventional cascode topology is dismissed, a single transistor structure is adopted instead for the LNA. The issue of this structure is the stability problem, and it has been tackled in our design. A figure of merit is also presented to find an optimum biasing point for transistors under low supply voltage as low as 0.6V.
Transformer ac coupling is an effective way to realize a low power front-end circuit.
It can not only cut down the supply voltage [13], but also do the phase transformation
IF- IF+
LO- LO+
LO+
VDD
M1
Ld LS1
RFin Lg
Ls Cex
LS2
Fig. 4.1 Receiver front-end circuit schematic.
without extra power consumption [14]. The transformer design relates to many design variables, to analyze and design with a quick convergence to the optimum condition is realistic for fabrication. In this work, based on resonant operation idea [15], a transformer is designed to transform single-ended signal from the LNA into differential current with current conversion gain to realize a low power receiver front-end circuit.
Fig. 4.1 shows the circuit schematic of this receiver front-end. The design consideration of each stage is discussed in the following sections.
4.2 Low Noise Amplifier
4.2.1 MOSFET I-V Model
A semi-empirical, single-piece expression that provides good accuracy in moderate inversion and acceptable accuracy in weak and strong inversion is given by [16]
}
φ is the thermal voltage. The parameter n whose value depends on the
process describes the rate of exponential incrase of Ids with Vgs in the subthreshold region. Its value varies from 1.1 to 1.9 which is higher for short channel devices.
When MOSFET operates in weak inversion region, the exponential terms in (4-1) are small and with log(1+x)≈x for x<<1, (4-1) reduces to
t for linear region, and it is simplified to
n for strong inversion where MOSFET in the linear RF blocks are usually biased. In the
saturation region, the second exponential in (4-1) becomes negligible, and (4-1) reduces to
2
2 )]
1
{[ln( t
th gs
n V V
do
ds I e
I φ
−
+
= (4-5) From the semiconductor concept, the MOSFET’s operation region makes a transition from weak to moderate inversion region if both the minority and the majority carrier concentrations become equal. To determine the bias transition from the I-V relation of MOSFET, the exponential part of (4-5) is approximated as(Vgs −Vth)2 when Vgs −Vth >>2nφt. Thus, the upper limit of moderate inversion
region is roughly defined as the gate-source voltage at which 2 =10
−
t th gs
n V V
e φ or
Vgs-Vth=4.6nφt [17]. The boundary value for the transition for n as 1.1 to 1.9 ranges
from Vgs-Vth=0.131 to Vgs-Vth=0.226.
4.2.2 Optimum Design- New Figure of Merit
LNA typically consumes much more power than that of the other parts to provide enough gain to the receiver front-end circuit. In order to maintain low power consumption, the biasing current of the LNA is desired to be as low as possible.
Therefore, there exists a compromise between the current consumption, ID, and the transconductance, gm, of the MOSFET to keep the gain of the circuit. A conventional
the frequency response of a device into consideration. Another figure of merit, gmft/ID, [17] which adds unit gain frequency into it to evaluate the frequency response of the MOSFET is therefore defined and an optimum design point is found by using this parameter, which is moderate inversion region of a MOS transistor.
But this figure of merit is not effective as the supply voltage level goes down. As shown in fig. 4.2, where the x axis is the biasing current, ID, and the y axis is the production of gm and ft divided by ID, both of which are not normalize but it has no effect on the conclusion. Fig. 4.2(a) takes supply voltage, VDD, as 1 V and 0.8 V, respectively. Sweep the bias voltage, Vgs, from zero to VDD, a maximum value of the figure of merit is reached when Vgs is about 0.6V. But when the supply voltage is lowered further to 0.6V, as shown in fig. 4.2(b), no optimum point would exist. The value of the figure of merit keeps flat when Vgs approaches VDD, 0.6V.
To decide an optimum design point around 0.6V, linearity of the MOS transistor is
0 1 2 3 4 5
-0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
g mf t/I D
ID (mA)
VDD=0.8V VDD=1V Vgs=0.6V
0.0 0.1 0.2 0.3 0.4 0.5
-0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
gmft/ID
ID (mA)
VDD=0.6V
(a) (b)
added to define a figure of merit for MOSFET: which has been used as a figure of merit for LNA. As shown in fig. 4.3(a), IIP3 has an optimum value around that flat region. Fig. 4.3(b) shows the new figure of merit.
Therefore, the bias condition of LNA is chose as 0.58V.
However, the load impedance affects the position of the IIP3 peak and should be taken into consideration as discussed in section 4.4. Therefore, a modified version of this circuit was re-taped out. The second chip of the front-end trades little gain while has better linearity and lower power consumption.
-5
0.10 0.15 0.20 0.25 0.30 0.35 0.40 -0.2
Fig. 4.3 Character of a transistor (a) Parameters variation of a transistor (b) Several figure of merits for a transistor.
4.2.3 LNA Stabilization
Cascode configuration shown in Fig. 4.4(a) is conventionally adopted for LNA design. It has good isolation between the input and output port. However, as the supply voltage goes down, cascode configuration is not applicable. A single transistor configuration as shown in Fig. 4.4(b) is preferred. The Cgd feedback path causes the circuit isolation become poor. The load inductance connected to the drain of the transistor falls into the unstable region for a common source transistor. Therefore, an effort is needed to make sure the circuit is stable.
Fig. 4.5 is the source and load stability circle of a single transistor from 0.1GHz to 10GHz. As shown in this figure, the load stability circle of a common source transistor typically cuts the upper region of the smith chart. There is no stability issue for the cascode topology since the load of the common source transistor is usually
Vdd
Cgd
(a) (b)
Fig. 4.4 Topologies of LNA (a) Cascode configuration (b) Single transistor topology.
capacitive and locates at the stable region. However, the load in our design is potentially inductive. To improve the stability of the two port network, a small signal model shown in Fig. 4.6(b) is used to calculate the input resistance when an inductor being its load and two passive components added as in Fig. 4.6(a). The input impedance is derived as
)]
To make sure the real part of the input resistance is positive, ac+bd must be positive.
indep(L_StabCircle1) (0.000 to 51.000)
L_StabCircle1
indep(S_StabCircle1) (0.000 to 51.000)
S_StabCircle1
Fig. 4.5 Load and source stability circle of a single transistor
After some calculation, the equation is given as 0
) 1
)(
(CgsLs −CgdLd −CgdLdw2 > (4-9)
The input resistance might be negative due to the inductive load. The second term in (4-9) would not be negative up to several tens of gigahertz. Therefore, the multiplication of Cgs and Ls must be larger than CgdLd to improve the circuit stability.
The result is quite intuitive since the gain of the circuit degrades due to these added components. The above analysis gives a hint to improve stability, though it is not complete. The output port should also be checked. However, as shown in Fig. 4.5, the source stability circle cuts less to the Smith chart and the source impedance is typically 50 Ohms which is far out of the stability circle.
Cex Ls Vdd
Ld Cd
(a) (b)
Fig. 4.6 Schematic and small signal model of proposed LNA (a) The transistor with stabilization elements.
(b) small signal model of (a).
Fig. 4.7(a) depicts the simulation result of load stability circle’s variation when these two passive components are added to a single transistor. Fig. 4.7(b) shows the variation of K for Cex and Ls. The K does grow high as LsCex gets higher. The K is still less than 1, so the circuit is still conditionally stable. But as Fig. 4.7(a) shows, the stability circle does moves more out before stabilization.
Since the higher the Cex and Ls is, the lower the gain and the higher the NFmin
would be, these values are chosen to be properly large to make sure the load impedance locates outside the stability circle for all the frequencies. As shown in Fig.
4.8, the Ls is 0.9nH and Cex is 100fF.
MOS only Ls added
Ls and Cex added
Stability Circle (5.5GHz)
0.17 0.25
0.34 0.42
0.51 0.59
0.68 0.76 0.85
50 100 150 200 250 300
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
L s (nH)
Cex (fF)
K@5.5GHz (Q of L
s = 10)
(a) (b)
Fig. 4.7 Stability variation with stabilization (a) Stability circles before and after stabilization (b) K of a transistor with Ls and Cex
4.3 Mixer Consideration
The transconductor of the mixer is the transformer stage. The transformer converts input signal into differential current output and then sends into the mixing stage. The design consideration for the first chip of the front-end circuit is based on the idea discussed in Section 3.4. However, the mixing stage has to be activated by large LO power which dose not conform to the idea of low power consumption. Therefore, the modified version re-considers the design procedure. Gate bias voltage, LO power, and load resistance RL are the design variables. The conversion gain begins to decrease when the MOSFET operation suffered from compression, which is about 0.2 to 0.3V for drain to source voltage VDS.
indep(L_StabCircle1) (0.000 to 51.000)
L_StabCircle1
freq (1.000GHz to 10.00GHz)
_20070525_new_loading..S(1,1)
Frequncy from 1GHz to 10GHz
Load stability circle
Load impedance
indep(L_StabCircle1) (0.000 to 51.000)
L_StabCircle1
freq (1.000GHz to 10.00GHz)
_20070525_new_loading..S(1,1)
Frequncy from 1GHz to 10GHz
Load stability circle
Load impedance
Fig. 4.8 Frequency response of load stability circle and load impedance
Therefore, for larger RL, the LO power for highest gain is smaller while the power consumption is smaller. And for lower gate bias voltage, or said larger VSG for PMOS, the LO power for highest gain is also smaller. Fig. 4.9 depicts the current to voltage conversion gain of the mixing stage with different RL for a given gate bias voltage 0.16V. Since the gain gets saturated when RL large, the selected RL is 1600 Ohm and the LO power is -7.5dBm.
-10 -8 -6 -4 -2 0
34 36 38 40 42 44 46 48 50
A IR L (dB)
LO power (dBm)
RL=1200 RL=1600 RL=2000 RL=800 RL=400
Fig. 4.9 Conversion gain versus LO power for different load resistance.
4.4 Transformer Design
Transformer is used as the phase splitter stage for this circuit. Differential current has been generated from a single-ended input for the following stage with no extra power consumption. However, the conversion loss of a conventional transformer design trades the benefit of power, since a higher power consumption of LNA is required to overcome the loss. Based on the idea of resonant operation mentioned in [15], two coupled resonant networks, each of which composed of a capacitor and an inductor, have resonant frequency w1 and w2, respectively, can result in a high current gain of the transformer. In this way, there is no need to increase the power of the LNA stage and the phase splitting can be done with current conversion gain under no extra power consumption so that low power consumption is achieved. Moreover, the AC coupled DC blocked character makes LNA and Mixer connected in a folded topology.
Low supply voltage is therefore realized.
4.3.1 Equivalent Model for the Transformer
There are some main parameters regarding to describe a transformer. One of them is turn ration n:
1 2
n L
= L (4-10) where L1 and L2 are the self-inductances of the primary and secondary windings,
respectively.
The self-inductance, which is relates the voltage induced in a winding by a time-varying current in the same winding, is extracted at the terminals with other windings open-circuited. For monolithic transformers, the turn ratio value is not equal to the turn ratio of the layout, since the physical length of the inside and outside turns are not equal. Besides, the arrangement of the alternative windings affects the self-inductance of each winding.
Another is the magnetic coupling coefficient k:
1 2
k M
= L L (4-11) where M is the mutual inductance, which is the ability of one inductor or segment to induce a voltage across the neighboring inductor or segment when they are close enough.
There are mutual inductance between two inductors and different segments of a single inductor. The mutual inductance linking these two could be positive or negative to the total inductance of each of them. For two segments with current flow in the same direction, the mutual inductances are positive. But for two segments with current flow in opposite direction, the mutual inductances are negative. k is a measure of the magnetic coupling between two windings and ranges from zero, uncoupled condition, to unity, perfect coupling. For passive elements, the magnitude of the
coupling coefficient may not exceed unity.
Fig. 4.10(a) is a figure of transformer with loads Z1 and Z2 and Fig. 4.10(b) is a simple equivalent model for the transformer. L1 and L2 are the self-inductances of the windings. M is the mutual inductance between the two windings. Rs1 and Rs2 are the ohmic losses of the windings. Z1 and Z2 are not only the source and load impedances but also have to include parasitic capacitances of the transformer, as the model adopted later. The input impedance Zin1 can be derived as
2 2
1 1 1
2 2 2
= + +
+ +
in s
s
Z R SL w M
Z R SL (4-12) For an ideal transformer, which is defined to has unity coupling coefficient, and infinite self-inductances with no loss, the input impedance is
M
L1 L2
Rs1 Rs2
Z2 Z1
(a)
M
RS1 L1-M L2-M RS2
Zin1 Zin2
Z1 Z2
(b)
Fig. 4.10 Transformer model (a) a figure presents transformer (b) a small signal model of (a)
2
in1 2
Z =Z n (4-13) which is quite different from the input impedance derived for non-ideal case. Though both of them depict the ability of impedance transformation, the n2 ratio may not be realistic in reality and depends on the inductances and mutual inductances.
4.3.2 Derivation and Design of Resonant Operation
for Current Gain
Before calculating for the current transfer equation, let’s take a look at resonant network[15] which is composed of two LC resonant circuits with some mutual coupling between them as shown in Fig. 4.11. The resonant frequencies are w1 and w2, respectively.
2 2 2
1 1 1
, 1 1
C L C
L =
= ω
ω
(4-14)
Let w =mw . The two resonant frequencies of this system can be derived as
Fig. 4.11 Resonant system
2 4 2 2 2
For two resonators of the same frequency wo, m=1, when there exists some coupling between them, the coupled system’s resonant frequency will depart from wo
due to the coupling coefficient. For two resonators of different resonant frequency, the systems resonant frequency will depend not only on k, but also on their separate resonant frequencies. When the resonant system resonant at the desired frequency, no matter it is of the higher resonant frequency or the lower one, the current gain can be relatively high.
Let’s consider for the model to calculate for the current transfer equation of the fabricated transformer. Since the signal is differential at the second turn, there exists a virtually short point for the transformer, the center tape, and two of the switching pairs of the front-end circuit are turned on by the LO signal. The simplified equivalent
circuit for the half path of Fig. 4.1 can be shown as Fig. 4.12. Rs and RL are the source and load impedances which are extracted from the former stage, LNA, and the following stage, switching stage, respectively. C1 and C2 are the parallel combination of the parasitic capacitances of transformer and that of the stages connected to it. With the definition of following coefficients, the transfer function would be a function of five variables, m, k, n, L1, and C1 when Rs, RL, w, and α are defined.
The current transfer function is (4-18) which is given as:
)]}
To design the transformer for resonant operation, (4-16) are assumed equal to operation frequency in turn and w is therefore solved for given m and k condition.
Iin RS C1 M C2
RS1 L1-M L2-M RS2 Iout
RL
Fig. 4.12 small signal model for current transfer function calculation
Once w2 is found, w1 is also known. The remained unknowns are the L1 and L2 values, which is equivalent to L1 and n, and C1 and C2, the last two unknowns, can be derived after these two values are defined. There are lots of possible solutions for L1 and n.
All these solutions satisfy the resonant operation condition. But among them, the rules of L1 and n combination which gives the highest possible gain need to be found out.
Since the target of the design is to find high gain solution, (4-18) is calculated for sets of L1 and n. Fig. 4.13 to Fig. 4.15 are the gain variation condition with solutions of L1
and n under certain m and k combination. The current gain is calculated for:
Rs=7.675kΩ, RL=276Ω, α=1Ω/nH case. Rs and RL is the extracted ro of LNA and operation parallel 1/gm of the switching pair.
1.07
Assumed three conditions: m=0.6 (m<1), m=1, m=1.4 (m>1) and set lower resonant frequency fL as 5.5GHz. The condition for higher gain is limited to certain turn ratio and the calculated gain becomes saturated for that turn ratio as L1 gets larger.
For larger m (w1 is higher than w2), the turn ratio for higher gain is moved to larger region than smaller m case. The current gain gets higher as k larger. No matter what the m value is, the current gain has close order of magnitude. But for m<1 and
0.239 0.761
0.935 1.11 1.28 1.46
1.63 0.587
0.413
1 2 3 4 5 6 7 8 9 10
0 1 2 3 4 5 6 7 8 9 10
Turn Ratio n
L1 (nH)
m=1.4, k=0.45, α=1 fH=10.0, f1=f2=5.92
Fig. 4.15 Current gain relative to n and L1. Set fL=5.5GHz. m=1.4, k=0.45
fL=5.5GHz case, the current gain can be larger than the turn ratio due to the resonant operation mode. Moreover, for m>1 and lower resonant frequency fH=5.5GHz case, the current gain can also be larger than the turn ratio as shown in Fig. 4.16.
For k higher, the current gain is getting lower for fH equal to 5.5GHz case. Although the current gain larger than turn ratio for m>1 case, the magnitude under this case is much lower than setting fL to 5.5GHz cases. Therefore, it is better to design fL as the
0.137
As mentioned in last few paragraphs, for fL=5.5GHz case, the current gain for different m is quite close and the gain is higher for larger k, how to make decision for these parameters? The constraint is given by the unavoidable parasitic capacitance of the transformer and that of the stages connected to transformer. C1 is typically the limit since the turn ratio larger than one means smaller L2, then calculated C2 is usually quite large. Fig. 4.17 shows the calculated C1 value for Fig. 4.13 (a) and (b).
When the coupling coefficient gets larger, the calculated resonant frequency w2
500
Fig. 4.17 Calculated C1 for different solutions (a) m=0.6, k=0.45 (b) m=0.6, k=0.65 (c) m=1, k=0.45.
becomes larger which means a larger w1. Then the C1 would become smaller as shown in Fig. 4.17(a) and (b). When m is larger, even though w2 is smaller, w1=mw2
is not necessary smaller since m increases. The m large case’s gain is limited by the C1 and achievable gain might be low.
By the inductor model of TSMC, one can estimate the parasitic capacitance of the transformer and then decide the parameters. Fig. 4.18 shows the frequency response of several inductors, by the resonant frequency of the inductor, the parasitic
By the inductor model of TSMC, one can estimate the parasitic capacitance of the transformer and then decide the parameters. Fig. 4.18 shows the frequency response of several inductors, by the resonant frequency of the inductor, the parasitic