Chapter 1 Introduction
1.3 Thesis Organization
In Chapter 2, fundamentals about noise theory and stability considerations in RF design will be introduced. In Section 2.1 the basics including the noise model of MOSFET, noise factor, and optimum source impedance are introduced. The stability concept about amplifier design is discussed in Section 2.2.
In Chapter 3, the design of a low-power double-balanced mixer is presented. The output balanced condition and noise analysis are given in Section 3.2. In Section 3.3 and 3.4, described are the design for folded structure and mixing pairs, respectively.
In Section 3.5, the implementation and measured result of the mixer is presented. A short conclusion of this mixer is given in Section 3.6.
Chapter 4 presents the design of a low-voltage low-power receiver front-end circuit.
In Section 4.2, the design consideration for a LNA is proposed. The I-V curve of MOSFET, a figure of merit for bias design, and stabilization of LNA are included.
Section 4.3 discusses the design consideration of mixing stage. Section 4.4 relates to the transformer design. The equivalent model for the transformer, resonant operation derivation and analysis, and the design of physical dimension of the transformer are all discussed. Section 4.5 reports the implementation and measured result of the circuit. Section 4.6 is a conclusion of this front-end circuit. A summary of the thesis and future work on this topic are given in the last chapter, Chapter 5.
Chapter 2
Fundamentals in RF Design
2.1 Noise Basic
2.1.1 Noise Model of MOSFET
Thermal noise is a consequence of Brownian motion: thermally agitated charge carriers in a conductor contribute a randomly varying current that give rise to a random voltage which has a zero average value, but a nonzero mean-square value.
The noise of a resistor can be modeled as a noise voltage generator in series with the resistor itself or a noise current source shunting the resistor with value given as
2 4
vn = kTR f∆ and 2 4
n i kT f
R
= ∆ , respectively. Because the noise arises from the
random agitation of charge in the conductor, the noise does not have a particular constant polarity and the polarity in model is simply a references.
Since MOSFET is essentially a voltage-controlled resistor, it exhibits thermal noise.
The dominant noise source in CMOS devices is channel thermal noise. The expression for this drain current noise of MOSFET is given by [3]
f g kT
ind2 =4 γ d0∆ (2-1)
device. γ is one for zero VDS and decreases toward 2/3 in saturation in long channel devices.
Another source of drain noise is flicker noise which is usually explained by charge trapping phenomena [3]. The trapping times by some types of defects and certain impurities especially at the surface are distributed in a way that can lead to a 1/f noise spectrum. Larger MOSFETs exhibit less 1/f noise because the large gate capacitance smoothes the fluctuation in channel charge. The 1/f drain noise source is given by [3]
WLC f g f i K
ox m
nd2 = ⋅ 2 2 ⋅∆ (2-2)
where K is a device-specific constant. For PMOS, K is typically about 1/50 times of that of NMOS.
For frequency as high as radio frequencies, the thermal agitation of channel charge leads to a non-negligible amount of noisy gate current to the MOSFET. The gate noise is produced by the fluctuations in the channel charge that induce a physical current in the gate terminal due to capacitive coupling. This source of noise is modeled as a shunt current source between gate and source terminal with a shunt conductance gg, and may be expressed as [3]
f g kT
ing2 =4 δ g∆ (2-3)
where
0 2 2
5 d
gs
g g
g ω C
= and δ is the gate noise coefficient, classically equal to 4/3 for
long-channel devices while 4 to 6 in short channel one. Since the gate noise and
channel thermal noise both stem from the thermal fluctuations in the channel, they are correlated with each other. The magnitude of the correlation can be expressed as [4]
j
where the value of -0.395j is exact for long channel devices. The gate noise can then be expressed as the sum of two components, one of which is fully correlated with the drain noise and the second of which is uncorrelated with the drain noise. It is
)
Fig. 2.1 depicts a standard MOSFET noise model. In this model, several noise sources mentioned are included: ind2 is the drain noise source, ing2 is the gate noise
Fig. 2.1 A standard noise model of MOSFET.
2.1.2 Noise Factor of a Tow-Port Network
Noise factor F is a useful measure of the noise performance of a system. It is defined as the ratio of the available noise power Pno at its output divided by the product of the available noise power at its input Pni times the networks’s numeric gain G or equivalently defined as the ratio of the signal to noise power at the input to the signal to noise power at the output [5]. Thus
o
The noise factor is a measure of the degradation in signal to noise ratio due to the noise from the system itself. Since the noise factor relates to the input noise power, a standardized definition of noise source has been setup: a resistor at 290K. A more general expression of noise factor NF is called noise figure which is just noise factor expressed in decibels:
F
NF =10log (2-7) When several networks are cascaded each having its own gain Gi and noise factor Fi, the total output noise is composed of all the noise from each stage but with different amount of contribution to the noise performance. The noise factor of a cascade networks is given as
1 ... From (2-8), the noise factor of the first stage is most critical and must be keep as
low as possible and the gain of it should be as large as possible to suppress the noise of the following stage. The result is intuitive since the noise’s interference has less effect when the signal level is high.
2.1.3 Optimum Source Impedance for Noise Design
The noise factor of a two port network can be given as [5]
2 min 2
| 1
| )
|
| 1 (
| 4 |
opt s
opt s
o n
Z F R
F − Γ +Γ
Γ
− + Γ
= (2-9)
where Rn is the correlation resistance which tells us the relative sensitivity of the noise figure to departures from the optimum conditions and Zo is the characteristic impedance of the system. This equation expresses that there exists an optimum source reflection coefficient, Γ , or equivalently an optimum source impedance, opt Zopt, at the input of the network in order to deliver lowest noise factor, Fmin. The value of Γ s
that provides a constant noise factor value forms non-overlapping circles on the Smith chart. It is usually the case that the optimum noise performance trades with the maximum power gain.
2.2 Amplifier Stability
The stability of an amplifier, or its resistance to oscillate, is a very important consideration in a design and can be determined from the S parameters, the matching networks, and the terminations [6]. The non-zero S12 parameter of a two port networks as shown in Fig. 2.2 provides a feedback path by which the power transferred to the output can be feedback to the input and combined together.
Oscillation may occur when the magnitude of reflection coefficient Γ or IN ΓOUT,
defined as the ratio of the reflected to the incident wave, exceeds unity. It is expected that a properly designed amplifier will not oscillate no matter what passive source and load impedances are connected to it [5], which is said to be unconditionally stable and the reflection coefficient is given as
1
conditionally stable. In such a case, input and load stability circles, the contour of
Γ =1 and IN ΓOUT=1 for certain frequencies on the Smith chart, are useful to fine the boundary line for load and source impedances that cause stable and unstable condition.
The stability circles can be calculated directly from the S parameters of the two port network, so another convenient parameter, stability factor K, is defined and given as
|
| 2
|
|
|
|
|
| 1
21 12
2 2
22 2 11
S S
S
K = − S − + ∆ (2-11)
where
2 21 12 22 11
2 | |
|
|∆ = S S −S S
The amplifier is unconditionally stable provided that
>1
K and |∆|2<1 (2-12) or equivalently
>1
K and B1 <1 (2-13) where B1=1+|S11|2 −|S22 |2 −|∆|2.
Fig. 2.2 Stability of two-port networks embedded between source and load.
Chapter 3
Low Power Double-Balanced Mixer
3.1 IntroductionMixer is an essential part of RF front-end circuits. Double balanced type mixer is more desirable than single-ended one for its better port-to-port isolation and even-order terms rejection. The received signal from the antenna is usually single ended. A phase splitter is needed to transform the signal from the proceeding stage, low noise amplifier (LNA), into a differential form to benefit from the double-balanced structure. To avoid unwanted signal loss, an active phase splitter is usually adopted [7][8]. However, the active phase splitter contributes limited gain and consumes lots of power. Therefore, in this work the phase splitter and transconductance stage are combined to a single stage to largely save power consumption. It consists of common gate and common source transistors which is claimed in [9] to have averagely good performance over other inspected types. The output balanced condition, the input matching, and the noise performance of the transconductance stage has been analyzed. PMOS switching stage with large size has bee selected for performance consideration.
The mixer under consideration is composed in an LC folded cascode structure [10]
as shown in Fig. 3.1. Folded structure is a good configuration for low supply voltage and provides enough voltage headroom for transistors. The proposed structure of the mixer can not only meet the 1V supply requirement but also allow further reduction in the supply voltage level. Moreover, LC resonating removes unwanted harmonic signals so the linearity can be improved.
Fig. 3.1 Circuit Architecture of mixer.
3.2 Transconductance Stage
3.2.1 Balanced Output Design
The transconductance stage consists of two transistors, a common gate transistor M1 and a common source transistor M2 as shown in Fig. 3.2(a). The RF input signal Vi is transformed into differential current by M1 and M2, respectively. The output differential current is then connected to the switching stage for current commutation, which loads the transconductor stage and makes the current into voltage Vo1 and Vo2
at drain nodes. In the analysis, the parasitic capacitance Cgd1 and Cgd2 are not neglected and ro1 and ro2 are also taken into consideration.
(a) (b)
(c)
Fig. 3.2 Common-gate common-source transconductance stage (a) schematic (b) small signal model of common gate and (c) common source parts.
Applying KCL to the small signal models shown in Fig. 3.2, the equations of output voltages to input voltage Vi is obtained as:
L
Where ZL models the loading impedance of the switching pairs and Vi’ is assumed close to Vi at the operating frequency for the large capacitance Cb which is added to do the dc blocking. The large resistor Rb is used to give dc bias voltage and neglected in the analysis.
(3-1) and (3-3) must be equal in magnitude and out of phase at the operation frequency. Assume a pure resistance loading, ZL=RL, and equal size for the two transistors. The magnitude and phase of the two equations is extracted:
2
2 adjust the magnitude balance condition without any impact on the phase difference.
Moreover, from (3-5), the phase difference of the two equations could be adjusted by one coefficient Cgd1 by adding a parallel capacitance Cex to the gate to drain capacitance of M1. Since Cgd1 will affect both the phase and gain difference, the Cex is defined to make the phase balanced first, then to adjust gm1 to meet the magnitude condition. The bias voltages of CG and CS stage are separated, so gm1 can be adjusted by gate voltage independently. The value of gm1 and gm2 would not be far apart, and the values of ro1 and ro2 are expected to be almost equal.
The input admittance Yin of the mixer can also be derived from the small signal model shown in Fig. 3.2:
Where Yin_CG is the input admittance of the common gate transistor M1 only and Yin_CS
is the input admittance seen into the gate of the common source transistor M2. The real
part of the input impedance is mainly the parallel combination of 1/gm1 and Zs1. By Zs1, the gm value can be much more released, that is the power consumption can be much lower when making the input impedance matches to the source resistance.
3.2.2 Noise Analysis
Noise is analyzed in a simplified model which neglects both Cgs and Cgd, Zs1 is assumed to be Rs1 to evaluate the noise contribution of every part of the transconductance stage, especially Rs1 that is used to help input matching and power consumption. Only the drain current noise of the MOSFET and thermal noise of each resistor are taken into consideration. Based on Fig. 3.3, the noise power of each noise source contributes to the output is derived respectively. When calculate the noise
1
RL RL2
(a) (b)
Fig. 3.3 Schematic for noise analysis (a) schematic (b) small signal model for (a)
Consider for the thermal noise of Rs only:
From (1) to (4), the output noise current can be derived as:
2 equation is able to be written down immediately from (5). It is given as
2 M2 contributes directly to the output:
2
when the parallel combination of Rs and Rs1 is approaching to 1/gm2. Take some values to give an approximate evaluation of each noise contribution. For Rs=50,
gm1=gm2=0.015, γ/α=1, and Rs1=200, (3-17) would be dB
F≈1+0.25+0.08+1.33=2.66=4.25 (3-18) The noises contribute by M2 is the main noise sources. The drain noise of M1
generates much less output noise as compared to M2 for its negative feedback function. However, if gm2 is increased to make the term be zero, the noise contributes by M2 is also increased. Moreover, the noise contributed by Rs1 is much large than that from M1.
3.3 LC-Folded Structure
The folded topology is a typical structure for low supply voltage consideration. The supply voltage of connected stages could be given respectively. An stacked structure
stage could be set differently. Though their biasing condition is independent, they are fully connected at high frequency for the frequency characteristic of LC tank. The LC tank is designed to resonate at the operation frequency. It is almost short at zero frequency so that DC supply voltage could be added through it. At the operating frequency, it provides very high impedance so that it will not degrade the differential current. Complete current could be transmitted to the switching stage for current commutation. At frequencies higher or lower to the center frequency, the impedance of LC tank is low. Therefore its resonate behavior forms a good filter to unwanted signals.
3.4 Mixing Stage
In this work, the proposed mixer utilizes current commutation for frequency mixing.
A mixing stage is constructed to transform the incoming RF signal to a lower frequency. The non-ideal switching character and noise contribution will alleviate the circuit performance. To make the switching behavior more ideal, MOSFET of larger size is chosen and biasing point is set near threshold voltage. As pointed out in the beginning of this paper, the effort to convert signal into differential form is to make mixer in double-balanced structure. The issues of even-order distortion and LO-IF feedthrough are diminished in the double-balanced mixer.
Moreover, PMOSFET is chosen for its lower flicker noise. The flicker noise of MOSFET is appeared in low frequency range around DC, much lower than LO frequency, it can be effectively modeled as interference at the gate terminal of switching component. This slowly varying offset voltage disturbs the switching time, advancing or retarding the time of zero crossing. Mixed with the LO signal, the low frequency noise is up-converted to frequency around the LO frequency which degrades the function of mixing [11]. Therefore, the mixer topology is chosen as PMOS pairs. The complete circuit schematic is shown in Fig. 3.4.
Fig. 3.4 Complete circuit schematic of the mixer.
3.5 Chip Implementation and Measured Result
The die micrograph of the mixer fabricated in 0.18-um RF CMOS technology is shown in Fig. 3.5. The size of the chip is 1.04 x 0.67 mm2 including bonding pads.
Measurements were conducted by chip-on-board setup as shown in Fig. 3.6. RF input and LO signals are applied through on-wafer probing with a GSG probe and GSGSG probes, respectively. A hybrid coupler is utilized to generate the LO differential signal from a single-ended signal. DC pads are wire-bonded on a PCB board, so as the differential IF signal. The output IF signal is buffered by an on-board unit gain operational amplifier circuit to convert to a single-ended form. Not to affect the IF loading condition, the differential input impedance of the OP amplifier is chosen as 16
LO+
LO-RFin
Fig. 3.5 Micrograph of the mixer.
Kohm. A 50-ohm resistor is connected in series at the OP amplifier output for impedance matching to measurement system. Therefore, 6dB voltage gain shall be compensated in all the gain measurement.
The supply voltage Vdd is set as 1V in the measurements. The total DC power consumption is only 2 mW. The measured and the simulated input return loss centered at 5.5 GHz are shown in Fig. 3.7(a). The measured S11 is better than -10 dB within the wanted frequency band but for frequency higher than 4GHz, the measured S11 is worse than the simulated data. If is found on the Smith chart that the impedance is higher than 50Ohm. The input matching condition could be improved with higher bias voltage for larger gm. The RF signal is downconverted to 1 MHz. The measured conversion gain is 10.4 dB and the P1dB point is -6.8 dBm as depicted in Fig. 3.7(b).
It is about 3.5 dB short as compared to the simulation. Two-tone test is done for measuring third-order intermodulation distortion. The maximum gain is corresponding to LO power equal to 2dBm as shown in Fig. 3.7(c). Fig. 3.7(d) shows that the measured IIP3 is about 3.8 dBm while the simulated IIP3 is about 0dBm. The noise figure is not tested for now and the simulated result is 9.9 dB.
RF port Probe
G G S
G
G G S S
LO port Probe
Bond wire
Vg1 Vg2 VDD Vgmixer DC Bias
IF Output Buffer
RF port Probe
G G S
G
G G S S
LO port Probe
Bond wire
Vg1 Vg2 VDD Vgmixer DC Bias
IF Output Buffer
Fig. 3.6 Setup for mixer measurement.
1 2 3 4 5 6 7 8 9 10 Fig. 3.7 Mixer measured result (a) Input return loss (b) Conversion Gain (c) Conversion gain versus Lo
3.6 Summary
A 5-GHz double-balanced mixer is designed and fabricated in 0.18 CMOS technology. The circuit architecture is chosen available for the application of low supply voltage and low power consumption. The circuit consists a transconductance stage and PMOS switching pairs in a folded topology. Phase splitting function is integrated in the transconductance stage, which is composed of a common gate and common source transistors to save power consumption and to benefit from the double–balanced topology. Output balanced condition and noise of the transconductance stage are analyzed.
The measured input return loss and voltage conversion gain are 11dB and 10.4dB, respectively. The input third-order intercept point (IIP3) is 3.8dBm while consuming only 2mW from a 1V supply. Table I summaries the measured results of this work and compares the performance with other two circuits. Among these, [12] is a differential input mixer, and the power consumption must be increased since a phase splitting stage has to be added for single-ended input. As compared to the two circuits, this work has comparable gain and linearity while consuming the lowest power and lower supply voltage.
TABLE 3.1
Summary of measured performance and comparison to other mixers.
Item This Work Ref[10] Ref[12]
Technology CMOS 0.18um CMOS 0.18um CMOS 0.18um
RF Frequency (GHz) 5.5 2.4 2.4
DC Supply Voltage (V) 1.0 1.8 1
LO power (dBm) 2 - 0.5 Vp
Conversion Gain (dB) 10.4 16.5 11.9
IIP3 (dBm) 3.8 9 -3
Noise Figure (dB) 9.9 (simulate) 14.2 (DSB) 13.9 (SSB)
Power Dissipation (mW) 2 5.4 3.2
Chapter 4
Low-Power Front-End Circuit
4.1 IntroductionTo meet the low supply voltage requirement, the conventional cascode topology is dismissed, a single transistor structure is adopted instead for the LNA. The issue of this structure is the stability problem, and it has been tackled in our design. A figure of
To meet the low supply voltage requirement, the conventional cascode topology is dismissed, a single transistor structure is adopted instead for the LNA. The issue of this structure is the stability problem, and it has been tackled in our design. A figure of