Chapter 2 Fundamentals in RF Design
2.2 Amplifier Stability
The stability of an amplifier, or its resistance to oscillate, is a very important consideration in a design and can be determined from the S parameters, the matching networks, and the terminations [6]. The non-zero S12 parameter of a two port networks as shown in Fig. 2.2 provides a feedback path by which the power transferred to the output can be feedback to the input and combined together.
Oscillation may occur when the magnitude of reflection coefficient Γ or IN ΓOUT,
defined as the ratio of the reflected to the incident wave, exceeds unity. It is expected that a properly designed amplifier will not oscillate no matter what passive source and load impedances are connected to it [5], which is said to be unconditionally stable and the reflection coefficient is given as
1
conditionally stable. In such a case, input and load stability circles, the contour of
Γ =1 and IN ΓOUT=1 for certain frequencies on the Smith chart, are useful to fine the boundary line for load and source impedances that cause stable and unstable condition.
The stability circles can be calculated directly from the S parameters of the two port network, so another convenient parameter, stability factor K, is defined and given as
|
| 2
|
|
|
|
|
| 1
21 12
2 2
22 2 11
S S
S
K = − S − + ∆ (2-11)
where
2 21 12 22 11
2 | |
|
|∆ = S S −S S
The amplifier is unconditionally stable provided that
>1
K and |∆|2<1 (2-12) or equivalently
>1
K and B1 <1 (2-13) where B1=1+|S11|2 −|S22 |2 −|∆|2.
Fig. 2.2 Stability of two-port networks embedded between source and load.
Chapter 3
Low Power Double-Balanced Mixer
3.1 IntroductionMixer is an essential part of RF front-end circuits. Double balanced type mixer is more desirable than single-ended one for its better port-to-port isolation and even-order terms rejection. The received signal from the antenna is usually single ended. A phase splitter is needed to transform the signal from the proceeding stage, low noise amplifier (LNA), into a differential form to benefit from the double-balanced structure. To avoid unwanted signal loss, an active phase splitter is usually adopted [7][8]. However, the active phase splitter contributes limited gain and consumes lots of power. Therefore, in this work the phase splitter and transconductance stage are combined to a single stage to largely save power consumption. It consists of common gate and common source transistors which is claimed in [9] to have averagely good performance over other inspected types. The output balanced condition, the input matching, and the noise performance of the transconductance stage has been analyzed. PMOS switching stage with large size has bee selected for performance consideration.
The mixer under consideration is composed in an LC folded cascode structure [10]
as shown in Fig. 3.1. Folded structure is a good configuration for low supply voltage and provides enough voltage headroom for transistors. The proposed structure of the mixer can not only meet the 1V supply requirement but also allow further reduction in the supply voltage level. Moreover, LC resonating removes unwanted harmonic signals so the linearity can be improved.
Fig. 3.1 Circuit Architecture of mixer.
3.2 Transconductance Stage
3.2.1 Balanced Output Design
The transconductance stage consists of two transistors, a common gate transistor M1 and a common source transistor M2 as shown in Fig. 3.2(a). The RF input signal Vi is transformed into differential current by M1 and M2, respectively. The output differential current is then connected to the switching stage for current commutation, which loads the transconductor stage and makes the current into voltage Vo1 and Vo2
at drain nodes. In the analysis, the parasitic capacitance Cgd1 and Cgd2 are not neglected and ro1 and ro2 are also taken into consideration.
(a) (b)
(c)
Fig. 3.2 Common-gate common-source transconductance stage (a) schematic (b) small signal model of common gate and (c) common source parts.
Applying KCL to the small signal models shown in Fig. 3.2, the equations of output voltages to input voltage Vi is obtained as:
L
Where ZL models the loading impedance of the switching pairs and Vi’ is assumed close to Vi at the operating frequency for the large capacitance Cb which is added to do the dc blocking. The large resistor Rb is used to give dc bias voltage and neglected in the analysis.
(3-1) and (3-3) must be equal in magnitude and out of phase at the operation frequency. Assume a pure resistance loading, ZL=RL, and equal size for the two transistors. The magnitude and phase of the two equations is extracted:
2
2 adjust the magnitude balance condition without any impact on the phase difference.
Moreover, from (3-5), the phase difference of the two equations could be adjusted by one coefficient Cgd1 by adding a parallel capacitance Cex to the gate to drain capacitance of M1. Since Cgd1 will affect both the phase and gain difference, the Cex is defined to make the phase balanced first, then to adjust gm1 to meet the magnitude condition. The bias voltages of CG and CS stage are separated, so gm1 can be adjusted by gate voltage independently. The value of gm1 and gm2 would not be far apart, and the values of ro1 and ro2 are expected to be almost equal.
The input admittance Yin of the mixer can also be derived from the small signal model shown in Fig. 3.2:
Where Yin_CG is the input admittance of the common gate transistor M1 only and Yin_CS
is the input admittance seen into the gate of the common source transistor M2. The real
part of the input impedance is mainly the parallel combination of 1/gm1 and Zs1. By Zs1, the gm value can be much more released, that is the power consumption can be much lower when making the input impedance matches to the source resistance.
3.2.2 Noise Analysis
Noise is analyzed in a simplified model which neglects both Cgs and Cgd, Zs1 is assumed to be Rs1 to evaluate the noise contribution of every part of the transconductance stage, especially Rs1 that is used to help input matching and power consumption. Only the drain current noise of the MOSFET and thermal noise of each resistor are taken into consideration. Based on Fig. 3.3, the noise power of each noise source contributes to the output is derived respectively. When calculate the noise
1
RL RL2
(a) (b)
Fig. 3.3 Schematic for noise analysis (a) schematic (b) small signal model for (a)
Consider for the thermal noise of Rs only:
From (1) to (4), the output noise current can be derived as:
2 equation is able to be written down immediately from (5). It is given as
2 M2 contributes directly to the output:
2
when the parallel combination of Rs and Rs1 is approaching to 1/gm2. Take some values to give an approximate evaluation of each noise contribution. For Rs=50,
gm1=gm2=0.015, γ/α=1, and Rs1=200, (3-17) would be dB
F≈1+0.25+0.08+1.33=2.66=4.25 (3-18) The noises contribute by M2 is the main noise sources. The drain noise of M1
generates much less output noise as compared to M2 for its negative feedback function. However, if gm2 is increased to make the term be zero, the noise contributes by M2 is also increased. Moreover, the noise contributed by Rs1 is much large than that from M1.
3.3 LC-Folded Structure
The folded topology is a typical structure for low supply voltage consideration. The supply voltage of connected stages could be given respectively. An stacked structure
stage could be set differently. Though their biasing condition is independent, they are fully connected at high frequency for the frequency characteristic of LC tank. The LC tank is designed to resonate at the operation frequency. It is almost short at zero frequency so that DC supply voltage could be added through it. At the operating frequency, it provides very high impedance so that it will not degrade the differential current. Complete current could be transmitted to the switching stage for current commutation. At frequencies higher or lower to the center frequency, the impedance of LC tank is low. Therefore its resonate behavior forms a good filter to unwanted signals.
3.4 Mixing Stage
In this work, the proposed mixer utilizes current commutation for frequency mixing.
A mixing stage is constructed to transform the incoming RF signal to a lower frequency. The non-ideal switching character and noise contribution will alleviate the circuit performance. To make the switching behavior more ideal, MOSFET of larger size is chosen and biasing point is set near threshold voltage. As pointed out in the beginning of this paper, the effort to convert signal into differential form is to make mixer in double-balanced structure. The issues of even-order distortion and LO-IF feedthrough are diminished in the double-balanced mixer.
Moreover, PMOSFET is chosen for its lower flicker noise. The flicker noise of MOSFET is appeared in low frequency range around DC, much lower than LO frequency, it can be effectively modeled as interference at the gate terminal of switching component. This slowly varying offset voltage disturbs the switching time, advancing or retarding the time of zero crossing. Mixed with the LO signal, the low frequency noise is up-converted to frequency around the LO frequency which degrades the function of mixing [11]. Therefore, the mixer topology is chosen as PMOS pairs. The complete circuit schematic is shown in Fig. 3.4.
Fig. 3.4 Complete circuit schematic of the mixer.
3.5 Chip Implementation and Measured Result
The die micrograph of the mixer fabricated in 0.18-um RF CMOS technology is shown in Fig. 3.5. The size of the chip is 1.04 x 0.67 mm2 including bonding pads.
Measurements were conducted by chip-on-board setup as shown in Fig. 3.6. RF input and LO signals are applied through on-wafer probing with a GSG probe and GSGSG probes, respectively. A hybrid coupler is utilized to generate the LO differential signal from a single-ended signal. DC pads are wire-bonded on a PCB board, so as the differential IF signal. The output IF signal is buffered by an on-board unit gain operational amplifier circuit to convert to a single-ended form. Not to affect the IF loading condition, the differential input impedance of the OP amplifier is chosen as 16
LO+
LO-RFin
Fig. 3.5 Micrograph of the mixer.
Kohm. A 50-ohm resistor is connected in series at the OP amplifier output for impedance matching to measurement system. Therefore, 6dB voltage gain shall be compensated in all the gain measurement.
The supply voltage Vdd is set as 1V in the measurements. The total DC power consumption is only 2 mW. The measured and the simulated input return loss centered at 5.5 GHz are shown in Fig. 3.7(a). The measured S11 is better than -10 dB within the wanted frequency band but for frequency higher than 4GHz, the measured S11 is worse than the simulated data. If is found on the Smith chart that the impedance is higher than 50Ohm. The input matching condition could be improved with higher bias voltage for larger gm. The RF signal is downconverted to 1 MHz. The measured conversion gain is 10.4 dB and the P1dB point is -6.8 dBm as depicted in Fig. 3.7(b).
It is about 3.5 dB short as compared to the simulation. Two-tone test is done for measuring third-order intermodulation distortion. The maximum gain is corresponding to LO power equal to 2dBm as shown in Fig. 3.7(c). Fig. 3.7(d) shows that the measured IIP3 is about 3.8 dBm while the simulated IIP3 is about 0dBm. The noise figure is not tested for now and the simulated result is 9.9 dB.
RF port Probe
G G S
G
G G S S
LO port Probe
Bond wire
Vg1 Vg2 VDD Vgmixer DC Bias
IF Output Buffer
RF port Probe
G G S
G
G G S S
LO port Probe
Bond wire
Vg1 Vg2 VDD Vgmixer DC Bias
IF Output Buffer
Fig. 3.6 Setup for mixer measurement.
1 2 3 4 5 6 7 8 9 10 Fig. 3.7 Mixer measured result (a) Input return loss (b) Conversion Gain (c) Conversion gain versus Lo
3.6 Summary
A 5-GHz double-balanced mixer is designed and fabricated in 0.18 CMOS technology. The circuit architecture is chosen available for the application of low supply voltage and low power consumption. The circuit consists a transconductance stage and PMOS switching pairs in a folded topology. Phase splitting function is integrated in the transconductance stage, which is composed of a common gate and common source transistors to save power consumption and to benefit from the double–balanced topology. Output balanced condition and noise of the transconductance stage are analyzed.
The measured input return loss and voltage conversion gain are 11dB and 10.4dB, respectively. The input third-order intercept point (IIP3) is 3.8dBm while consuming only 2mW from a 1V supply. Table I summaries the measured results of this work and compares the performance with other two circuits. Among these, [12] is a differential input mixer, and the power consumption must be increased since a phase splitting stage has to be added for single-ended input. As compared to the two circuits, this work has comparable gain and linearity while consuming the lowest power and lower supply voltage.
TABLE 3.1
Summary of measured performance and comparison to other mixers.
Item This Work Ref[10] Ref[12]
Technology CMOS 0.18um CMOS 0.18um CMOS 0.18um
RF Frequency (GHz) 5.5 2.4 2.4
DC Supply Voltage (V) 1.0 1.8 1
LO power (dBm) 2 - 0.5 Vp
Conversion Gain (dB) 10.4 16.5 11.9
IIP3 (dBm) 3.8 9 -3
Noise Figure (dB) 9.9 (simulate) 14.2 (DSB) 13.9 (SSB)
Power Dissipation (mW) 2 5.4 3.2
Chapter 4
Low-Power Front-End Circuit
4.1 IntroductionTo meet the low supply voltage requirement, the conventional cascode topology is dismissed, a single transistor structure is adopted instead for the LNA. The issue of this structure is the stability problem, and it has been tackled in our design. A figure of merit is also presented to find an optimum biasing point for transistors under low supply voltage as low as 0.6V.
Transformer ac coupling is an effective way to realize a low power front-end circuit.
It can not only cut down the supply voltage [13], but also do the phase transformation
IF- IF+
LO- LO+
LO+
VDD
M1
Ld LS1
RFin Lg
Ls Cex
LS2
Fig. 4.1 Receiver front-end circuit schematic.
without extra power consumption [14]. The transformer design relates to many design variables, to analyze and design with a quick convergence to the optimum condition is realistic for fabrication. In this work, based on resonant operation idea [15], a transformer is designed to transform single-ended signal from the LNA into differential current with current conversion gain to realize a low power receiver front-end circuit.
Fig. 4.1 shows the circuit schematic of this receiver front-end. The design consideration of each stage is discussed in the following sections.
4.2 Low Noise Amplifier
4.2.1 MOSFET I-V Model
A semi-empirical, single-piece expression that provides good accuracy in moderate inversion and acceptable accuracy in weak and strong inversion is given by [16]
}
φ is the thermal voltage. The parameter n whose value depends on the
process describes the rate of exponential incrase of Ids with Vgs in the subthreshold region. Its value varies from 1.1 to 1.9 which is higher for short channel devices.
When MOSFET operates in weak inversion region, the exponential terms in (4-1) are small and with log(1+x)≈x for x<<1, (4-1) reduces to
t for linear region, and it is simplified to
n for strong inversion where MOSFET in the linear RF blocks are usually biased. In the
saturation region, the second exponential in (4-1) becomes negligible, and (4-1) reduces to
2
2 )]
1
{[ln( t
th gs
n V V
do
ds I e
I φ
−
+
= (4-5) From the semiconductor concept, the MOSFET’s operation region makes a transition from weak to moderate inversion region if both the minority and the majority carrier concentrations become equal. To determine the bias transition from the I-V relation of MOSFET, the exponential part of (4-5) is approximated as(Vgs −Vth)2 when Vgs −Vth >>2nφt. Thus, the upper limit of moderate inversion
region is roughly defined as the gate-source voltage at which 2 =10
−
t th gs
n V V
e φ or
Vgs-Vth=4.6nφt [17]. The boundary value for the transition for n as 1.1 to 1.9 ranges
from Vgs-Vth=0.131 to Vgs-Vth=0.226.
4.2.2 Optimum Design- New Figure of Merit
LNA typically consumes much more power than that of the other parts to provide enough gain to the receiver front-end circuit. In order to maintain low power consumption, the biasing current of the LNA is desired to be as low as possible.
Therefore, there exists a compromise between the current consumption, ID, and the transconductance, gm, of the MOSFET to keep the gain of the circuit. A conventional
the frequency response of a device into consideration. Another figure of merit, gmft/ID, [17] which adds unit gain frequency into it to evaluate the frequency response of the MOSFET is therefore defined and an optimum design point is found by using this parameter, which is moderate inversion region of a MOS transistor.
But this figure of merit is not effective as the supply voltage level goes down. As shown in fig. 4.2, where the x axis is the biasing current, ID, and the y axis is the production of gm and ft divided by ID, both of which are not normalize but it has no effect on the conclusion. Fig. 4.2(a) takes supply voltage, VDD, as 1 V and 0.8 V, respectively. Sweep the bias voltage, Vgs, from zero to VDD, a maximum value of the figure of merit is reached when Vgs is about 0.6V. But when the supply voltage is lowered further to 0.6V, as shown in fig. 4.2(b), no optimum point would exist. The value of the figure of merit keeps flat when Vgs approaches VDD, 0.6V.
To decide an optimum design point around 0.6V, linearity of the MOS transistor is
0 1 2 3 4 5
-0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
g mf t/I D
ID (mA)
VDD=0.8V VDD=1V Vgs=0.6V
0.0 0.1 0.2 0.3 0.4 0.5
-0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
gmft/ID
ID (mA)
VDD=0.6V
(a) (b)
added to define a figure of merit for MOSFET: which has been used as a figure of merit for LNA. As shown in fig. 4.3(a), IIP3 has an optimum value around that flat region. Fig. 4.3(b) shows the new figure of merit.
Therefore, the bias condition of LNA is chose as 0.58V.
However, the load impedance affects the position of the IIP3 peak and should be taken into consideration as discussed in section 4.4. Therefore, a modified version of this circuit was re-taped out. The second chip of the front-end trades little gain while has better linearity and lower power consumption.
-5
0.10 0.15 0.20 0.25 0.30 0.35 0.40 -0.2
Fig. 4.3 Character of a transistor (a) Parameters variation of a transistor (b) Several figure of merits for a transistor.
4.2.3 LNA Stabilization
Cascode configuration shown in Fig. 4.4(a) is conventionally adopted for LNA design. It has good isolation between the input and output port. However, as the supply voltage goes down, cascode configuration is not applicable. A single transistor configuration as shown in Fig. 4.4(b) is preferred. The Cgd feedback path causes the circuit isolation become poor. The load inductance connected to the drain of the transistor falls into the unstable region for a common source transistor. Therefore, an effort is needed to make sure the circuit is stable.
Fig. 4.5 is the source and load stability circle of a single transistor from 0.1GHz to 10GHz. As shown in this figure, the load stability circle of a common source transistor typically cuts the upper region of the smith chart. There is no stability issue for the cascode topology since the load of the common source transistor is usually
Vdd
Cgd
(a) (b)
Fig. 4.4 Topologies of LNA (a) Cascode configuration (b) Single transistor topology.
capacitive and locates at the stable region. However, the load in our design is potentially inductive. To improve the stability of the two port network, a small signal model shown in Fig. 4.6(b) is used to calculate the input resistance when an inductor being its load and two passive components added as in Fig. 4.6(a). The input impedance is derived as
)]
To make sure the real part of the input resistance is positive, ac+bd must be positive.
indep(L_StabCircle1) (0.000 to 51.000)
L_StabCircle1
indep(S_StabCircle1) (0.000 to 51.000)
S_StabCircle1
Fig. 4.5 Load and source stability circle of a single transistor
After some calculation, the equation is given as 0
) 1
)(
(CgsLs −CgdLd −CgdLdw2 > (4-9)
The input resistance might be negative due to the inductive load. The second term in (4-9) would not be negative up to several tens of gigahertz. Therefore, the
The input resistance might be negative due to the inductive load. The second term in (4-9) would not be negative up to several tens of gigahertz. Therefore, the