Chapter 1 Introduction
1.2 Organization
This dissertation includes six chapters.
In Chapter 1, the background and the motivation of this thesis are reviewed.
In Chapter 2, we conduct a systematic comparison of carrier transport between overlapped and non-overlapped multiple-gate SOI MOSFETs (MuGFETs). The classical current-voltage and mesophysical characteristics have been investigated for devices with effective channel length Leff = 50 to 60 nm and fin width Wfin = 5 to 25 nm at T = 300 to 56 K. Several mesophysical characteristics, including quantum-mechanical confinement effects [12][13], quantum-mechanical interference effects [33], single-electron effects [34], variable range hopping conductance [25] and universal conductance fluctuations [35], are systematically examined. In addition, a new approach of Leff extraction is developed based on the quantum-mechanical interference effects.
In Chapter 3, we further demonstrate controlled single-electron effects in the non-overlapped MuGFETs [34] through a comprehensive investigation for the observed single-electron effects. Then, we systematically present single-electron effects for devices with various gate length (Lg), fin width (Wfin), gate bias (VGS), body doping (NB) and temperature [36]. The impact of access resistances [23], the estimation of gate-dot coupling strength [37] and phenomena of split-peak separations [38] are discussed.
Besides, we demonstrate that the gate capacitance as well as source/drain capacitance can be extracted with an aF-scale resolution by single-electron effects.
In Chapter 4, we report a generalized temperature-dependent channel backscattering extraction method that can self-consistently determine the temperature sensitivity of low-field mobility (µ0)and the critical length (l) in nanoscale MOSFETs [39]-[40]. The validity of our method for the process monitoring purpose is assessed based on various types of devices: high vs. low body-doping, HfO vs. SiO dielectric,
and unstrained vs. uniaxially strained devices. Through the extracted channel backscattering coefficients, we investigate the impacts of the Coulomb scattering, the uniaxial strain, the self-heating effect and the floating-body effect on ballistic efficiency.
Finally, we propose that the drain current variation can be suppressed through enhanced ballistic efficiency.
In Chapter 5, we systematically examine the gate tunneling current induced C−V distortion from measurements to simulations. Through the BSIM4-based macro model, different mechanisms of C−V distortion can be characterized for short and long channel devices. Then, we investigate the validity of the concept of intrinsic input resistance [41] in the characterization of the distributed channel RC effects [42]. Finally, we assess the feasibility of using the intrinsic input resistance approach for the inversion C−V reconstruction [43].
Chapter 6 summarizes essential research results and contributions of this dissertation work.
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Chapter 2
Comparison of Carrier Transport for Overlapped and Non-overlapped Multiple-Gate SOI MOSFETs
2.1 Introduction
Multiple-gate silicon-on-insulator (SOI) MOSFET (MuGFET) structures provide superior electrostatic integrity needed for complementary metal-oxide-semiconductor (CMOS) scaling entering the deca-nanometer regime [1]. The benefits of MuGFET have been extensively investigated regarding issues of short-channel effects (SCE), leakage current, threshold voltage (VT) fluctuations, mobility, and so on [2].
For MuGFET design, source/drain engineering is crucial because of the parasitic drain/source resistance [3] and the parasitic fringing/overlap capacitance that may limit circuit performance [4]. Two options in the source/drain engineering are the overlapped structure with light-doping drain/source (LDD/LDS) and the non-overlapped structure.
The LDD/LDS implantation has been widely used in state-of-the-art CMOS devices for suppressing source and drain resistances. On the other hand, transistor optimization for peak circuit performance within leakage current constraints (i.e., minimum CV/I delay) may dictate the non-overlapped gate to source/drain structure to minimize the fringing/overlap capacitance. Whether the various source/drain engineering will impact the carrier transport in nanoscale MuGFETs merits examination. In this chapter, we conduct a systematic comparison of carrier transport between overlapped and non-overlapped MuGFETs. The classical current-voltage and mesophysical characteristics have been investigated for devices with effective channel length Leff = 50
2.2 Overlapped and non-overlapped device structures
The process flow for fabricating MuGFETs is similar to that reported in [32]. Fig.
2.1(a) shows a schematic view of the MuGFET investigated in this study [31]. Our devices were fabricated on SOI wafers using standard CMOS optical lithography [5].
The Si-body thickness, Hfin, was thinned down to about 40 nm by thermal oxidation.
The fin-width, Wfin, was defined by wet etching. After Wfin was developed, the Si-body fin was doped with BF2 implantation and annealed. Using optical lithography and anisotropic reactive ion etching, the gate length, Lg, was defined. Note that the LDD/LDS implantation was performed for the overlapped structure (Fig. 2.1(c)) and was skipped for the non-overlapped structure (Fig. 2.1(b)) before developing the composite spacer of silicon oxide and nitride. Finally, heavily-doped N+ source/drain was made. In this study, we compare these two types of devices based on the same effective source-drain length Leff.
2.3 Experimental comparison 2.3.1 Classical characteristics
Current-voltage measurements (IDS–VGS) at VDS = 50 mV under T = 300 to 56 K were performed with a 25-mV VGS step for the overlapped Device 1 with Wfin = 25 nm and Lg = 80 nm (Fig. 2.2), and for the non-overlapped Device 2 with Wfin = 25 nm and Lg = 30 nm (Fig. 2.3). Fig. 2.2 shows that the subthreshold swing S for the overlapped Device 1 decreases with temperature. We have confirmed that the S–T characteristic follows the Boltzmann law S = n(kBT/q)ln(10) with the body effect coefficient n ≈ 1.16.
The linear temperature dependence of S is a feature of fully depleted SOI [8], and has also been observed in tri-gate SOI MOSFETs [13].
For the non-overlapped Device 2, however, the linear temperature dependence of
below 223 K, S is a constant and does not follow the Boltzmann law. This suggests that for the non-overlapped Device 2, tunneling current dominates the fundamental limitation of leakage current instead of the thermal current [12]. We have noted that similar S behavior has been reported at T < 100 K for the planar non-overlapped NMOSFET in [12]. It implies that the leakage current associated with thermionic emission is suppressed in our MuGFET.
The insensitive temperature dependence of IDS can also be found in the strong inversion region for the non-overlapped Device 2 (Fig. 2.3). In contrast to that of the overlapped Device 1 (Fig. 2.2), the IDS for VGS > 0.6 V is nearly independent on temperature. These results indicate that carrier transport in the strong inversion region is determined by the phonon-limited mobility for the overlapped Device 1, but not for the non-overlapped Device 2.
2.3.2 Mesophysical characteristics
To further compare the carrier transport characteristics for overlapped and non-overlapped devices, we have investigated channel conductance (GDS = IDS/VDS) with low VDS. Fig. 2.4 shows the measured GDS versus VGS characteristics for the overlapped Device 3 with Wfin = 10 nm and Lg = 60 nm. Significant GDS fluctuations can be seen at T = 56 K (Fig. 2.4(a)). Similar GDS fluctuations have been reported in [6] and attributed to the intersubband scattering. While the number of populated subbands increases with increasing VGS, the intersubband scattering also increases with each new subband [7]. In other words, when VGS increases, the GDS increases due to new populated subbands and then decreases due to the mobility reduction (i.e., the increase of intersubband scattering). Thus, fluctuations can be seen in the GDS–VGS characteristics. We have noted that the GDS fluctuations almost occur at the same VGS, such as the spike at VGS-VT = 0.425 V (Fig. 2.4(a)). We have also noted that for the wider overlapped devices (i.e.,
Device 1) with negligible subband splitting, the GDS fluctuations can not be found.
One important criterion to observe the intersubband scattering effect is that the qVDS and kBT are not significantly larger than the subband energy split ∆E [7]. It is worth noting in Fig. 2.4(a) that the GDS fluctuations can be observed at VDS = 50 mV under T = 56 K. Considering the voltage drop across the access resistances (i.e., source/drain resistances, contact resistance and back-end metal resistance), the effective qVDS over the channel and therefore ∆E may be about 20 to 30 meV. This is also consistent that with the observed GDS fluctuations at VDS = 1 mV under T = 223 K shown in Fig. 2.4(b). Besides, we have noted in our process that the final minimum Wfin at the channel center is smaller than the mask-defined 10-nm Wfin (final minimum Wfin
~5 nm) due to over etching [31].
An important signature for intersubband scattering is that conductance reductions (i.e., mobility reduction) occur as VDS increases [6]. This is because the drain bias forces electrons to jump from higher to lower subbands, and thus enhances intersubband scattering and reduces the carrier mobility [7]. It is worth noting that the reductions in GDS due to mobility reduction can also be observed at VDS = 1 mV when temperature increases from 56 to 223 K. Similar VDS and temperature dependence in GDS has also been observed for trigate SOI MOSFETs in [6]-[7].
For the non-overlapped Device 2 in the high VGS regime, the GDS increases with VDS and temperature as can be observed in Fig. 2.5(a) and Fig. 2.5(b), respectively. Such VDS and temperature dependence of GDS is completely opposite to that of the overlapped Device 3 (Fig. 2.4) and can not be ascribed to the intersubband scattering effect. In addition, Fig. 2.5 also shows interesting fluctuations with negative differential resistance in the GDS. Although the GDS fluctuations in Fig. 2.5 were observed in the same measurement conditions as Fig. 2.4, one can safely state that it does not result
from the intersubband scattering. In the next section, we shall give more discussions for the anomalous GDS behavior of the non-overlapped Device 2.
2.4 Interpretation
2.4.1 Intersubband scattering effects
As described above, the VDS and temperature dependence of GDS in Fig. 2.5 for the non-overlapped Device 2 is completely opposite to characteristics of intersubband scattering effect. Therefore, the GDS fluctuations in Fig. 2.5 can not be ascribed to the intersubband scattering effect. Besides, we have also noted that for the overlapped Device 1 with the same Wfin (i.e., Wfin = 25 nm), the GDS fluctuations can not be found.
2.4.2 Single-electron effects
Coulomb blockade is expected to be important as the charging energy e2/Cg of the device becomes large [18][19]. With scaling of devices, it is expected that Coulomb blockade oscillation (CBO) occurs in ID–VGS characteristics [20]. Although the multiple-gate SOI structure with adequate source/drain engineering presents a very promising scheme to build room-temperature SETs [21], we have confirmed in Fig. 2.5 that the physical mechanism described for the non-overlapped device is not due to the CBO. Regarding single-electron effects in the non-overlapped multiple-gate device, we have presented our research results in Chapter 3.
If the GDS–VGS characteristics shown in Fig. 2.5(a) were due to CBO, the VGS period of CBO can be related to the gate capacitance by e/Cg as well as gate effective area (Aeff) by Cg = Aeff×εSiO2/EOT. Since the effective oxide thickness (EOT) is about 2.6 nm for our device, from e/Cg ≈ 75 mV (Fig. 2.5(a)), Aeff is estimated ~1.6×10-12 cm2 for our MuGFET. However, such Aeff is about 15 times smaller than 2HfinLg = 2.4×10-11 cm2. This indicates that the GDS oscillations in Fig. 2.5(a) can not be attributed to CBO.
which is not the signature of CBO.
2.4.3 Variable range hopping conductance
Charged centers in the oxide, interfaces or bulk Si can result in random potential fluctuation [22][23]. In the limit of zero temperature, electron transport is characterized by hopping certain charged centers. When the energy of carriers is increased with temperature or VDS, hopping processes determined by the activation energy may change.
In other words, conductance fluctuations may change with temperature or VDS. This phenomenon is an origin of the variable range hopping (VRH) itself. In our experimental results, however, the anomalous conductance fluctuations are present at the same (VGS-VT) values for the same device with various temperature and VDS (Fig.
2.9). Besides, if electron transport is limited by the VRH, the tunneling conductance must be less than e2/h [22][23]. That the GDS in Fig. 2.5 is several times e2/h may exclude the possibility of the VRH. Furthermore, if we assume the anomalous conductance fluctuations are caused by trapping and de-trapping mechanisms, a dependence of fluctuations on the measurement frequency is expected. This could not be observed in our AC Gm measurements in Fig. 2.16 to 2.18.
2.4.4 Universal conductance fluctuations
Due to the two voltage-controlled potential barriers, the universal conductance fluctuations (UCF) [24], as have been predicted by Lee and Stone [25] for disordered systems, are also not expected to be responsible for our observed conductance fluctuations. In addition, to the best our knowledge, the UCF are easily smeared by temperature and may not be easily observed for our devices at T > 4.2 K [26].
2.4.5 Quantum interference effects
Fig. 2.6 shows the electronic potential calculated using ISE device simulation
as the voltage-controlled potential barriers along the channel. Therefore, carrier transport from source to drain is significantly influenced by the barriers as illustrated in Fig. 2.6: directly tunneling (Ia), thermally-associated tunneling (Ib), and thermionic emission (Ic). The contribution of these three mechanisms to IDS depends on VGS and temperature. For high VGS, Ia is dominant. With decreasing VGS, increased electronic potential diminishes Ia, and thus Ib and Ic become important. In other words, IDS in the subthreshold region results mainly from Ib and Ic for the non-overlapped device. It is worth noting that carrier transport by Ic requires more thermal energy and may be suppressed under low temperature.
Figure 2.7 shows the temperature sensitivity of IDS (∂log(IDS)/∂T) vs. VGS
characteristics extracted from Fig. 2.2 and Fig. 2.3 under high and low temperatures.
For the non-overlapped device in the strong inversion region, the insensitive temperature dependence manifests the importance of Ia. On the other hand, the negative temperature dependence for the overlapped device in the strong inversion region indicates phonon scattering. In addition, it can be noted in Fig. 2.7(a) that ∂log(IDS)/∂T significantly increases with decreasing VGS for both overlapped and non-overlapped devices. This suggests that in the high temperature regime the subthreshold current of the non-overlapped device is dominated by Ic, similar to the overlapped device. When temperature decreases, however, the thermionic emission Ic is suppressed and the Ib
component with weak temperature dependence becomes dominant. In other words, the suppression of Ic under low temperature is the main reason of S saturation for the non-overlapped device. It should be noted that such mechanism of S saturation is different from lateral tunneling through the channel, as presented for ultra-short devices in [12] and [17].
Figure 2.6 also shows an equivalent quantum well under the gate in the
non-overlapped device [12]. It is worth noting that the height of the voltage-controlled
non-overlapped device [12]. It is worth noting that the height of the voltage-controlled