Conclusion - Comparison of Carrier Transport for Overlapped and

Chapter 2 Comparison of Carrier Transport for Overlapped and

2.6 Conclusion

We have conducted a comparative study of carrier transport characteristics for MuGFETs with and without the non-overlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the non-overlapped devices, however, we found insensitive temperature dependence of I_DS in both subthreshold and inversion regimes. Our low-temperature measurements indicate that the inter-subband scattering may be the dominant carrier transport mechanism for narrow overlapped MuGFETs. For the non-overlapped MuGFETs, the voltage-controlled potential barriers in the non-overlapped regions may give rise to the weak localization effect (conductance reduction) and the quantum interference fluctuations. In addition, we have developed a novel approach to obtain the V_GS-dependent L_eff for MuGFETs with non-overlapped gate to source/drain structure. The extracted Leff, based on the wave nature of channel electrons, agrees with the simulation result that is based on the inversion-layer sheet conductivity.

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Fig. 2.1. (a) Multiple-gate FinFET SOI structure investigated in this work and its cross-sectional AA’ view along the channel direction showing (b) the non-overlapped gate to source/drain structure and (c) the overlapped gate to source/drain structure.

(a)

(c) Overlapped FinFET Lg

D S

Wfin G (LDD/LDS)

Leff

(b) Non-overlapped FinFET L_g

D S

G (Non-LDD/LDS)

W_fin L_eff

S G

Wfin

Hfin

L_g SiO₂

A A’

Spacer

Fig. 2.2. Measured I_DS vs. V_GS characteristics at V_DS = 50 mV under T = 300 to 56 K

Fig. 2.3. Measured I_DS vs. V_GS characteristics at V_DS = 50 mV under T = 300 to 56 K

Fig. 2.4. Measured channel conductance (GDS) vs. (VGS-VT) characteristics for the

Fig. 2.5. Measured GDS vs. (VGS-VT) characteristics for the non-overlapped Device 2

Fig. 2.6. Calculated electronic potential for the non-overlapped gate to source/drain structure at VGS = 0 to 1 V. Vp: peak potential value in the non-overlapped region. Vc: potential value at the channel center. E: carrier energy. d: width of the effective quantum well. I_a: direct tunneling through the potential barrier of the non-overlapped region. I_b: thermally-associated tunneling. I_c: thermionic emission.

-0.59 -0.57 -0.55 -0.53 -0.51 -0.49 -0.47 -0.45

0 20 40 60 80

channel direction (nm)

Electronic Potential (eV) S D

V_GS=0~1V

eV_p

eVc

d E

Fig. 7. Measured temperature sensitivity of drain current (∆log(IDS)/∆T) vs. (VGS-VT) characteristics for overlapped and non-overlapped devices under (a) high temperature, T = 300 to 250 K and (b) low temperature, T = 223 to 56 K.

-0.002 0 0.002 0.004 0.006 0.008 0.01

-0.4 0 0.4 0.8

V

-V

(V)

(l o g (I

DS,T1

)- lo g (I

DS,T2

)) /( T 1 -T 2 )

T1 = 300K T2 = 250K

Non-overlapped Overlapped (a)

-0.4 0 0.4 0.8

V

-V

(V)

T1 = 223K T2 = 56K

Non-overlapped Overlapped (b)

Fig. 2.8. Calculated transmission probability Tr vs. VGS for d = 30 nm and E-eVp = 0~5, 5~10 and 10~15 meV.

Group 1 Group 2 Group 3

Fig. 2.9. Measured G_DS and G_m'/V_DS vs. (V_GS-V_T) characteristics for the non-overlapped Device 2 with Lg = 30 nm and Wfin = 25 nm at VDS = 1 and 50 mV under T = 56 and 300 K. (Gm' = ∂Gm/∂VGS and Gm = ∂IDS/∂VGS).

0 1 2 3 4

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

-V

(V)

G

( e

/h )

-1.0E-3 -5.0E-4 0.0E+0 5.0E-4 1.0E-3 1.5E-3

G

'/V

( S /V

)

Non-overlapped Device 2

G_DS G_m'

T=56K, VD S=1mV T=56K, V_{D S}=50mV T=300K, V_{D S}=2mV

Fig. 2.10. Calculated transmission probability Tr vs. VGS and E for d = 30 nm.

Fig. 2.11. Fermi wavelength as a function of (VGS-VT). The location at which the quantum interference occurs is indicated for d = 30 nm.

0 10 20 30 40 50 60 70 80 90

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

V

-V

(V)

λ

( n m )

Fermi wavelength (λ_F) calculation EOT ~ 2.6nm

Predicted interference occurrence for d = 30 nm n=1

n=2

n=3

n=4

Fig. 2.12. Fermi wavelength as a function of (V_GS-V_T). The location at which the quantum interference occurs is indicated for d = 40 nm.

0 10 20 30 40 50 60 70 80 90

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

V

-V

(V)

λ

( n m )

Fermi wavelength (λ_F) calculation EOT ~ 2.6nm n=1

n=2

n=3

Predicted interference occurrence for d = 40 nm

n=6

n=4 n=5

Fig. 2.13. Calculated transmission probability Tr vs. V_GS and E for d = 40 nm.

Fig. 2.14. Measured Gm'/VDS vs. (VGS-VT) characteristics for the Device 6 with Lg = 40 nm and W_fin = 25 nm.

-1.0E-3 -5.0E-4 0.0E+0 5.0E-4 1.0E-3 1.5E-3

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

-V

(V)

G

'/V

( S /V

)

Non-overlapped Device 6 L_g=40nm W_fin=25nm

VDS=2mV VDS=50mV

Fig. 2.15. Illustration of the quantum interference effect on ID–VGS, Gm–VGS, and

∂Gm/∂VGS vs. VGS characteristics.

Backgro und I_D Fluctua tio n due to

Qua ntum Interference I_D

V_GS

V_GS G_m

V_GS dG_m/dV_GS

4294 LCR meter

D S

G

Hi port (Force) Lo port

(Sense)

4156 IV meter

DC V_DS bias

4294 LCR meter

D S

G

Hi port (Force) Lo port

(Sense)

4156 IV meter

DC V_DS bias

Fig 2.16. AC Gm measurement used in this work (freq. = 2 MHz). Note that the trapping/de-trapping mechanisms can be suppressed by the AC method.

Fig. 2.17. DC and AC measurement results of ∂Gm/∂VGS vs. VGS-VT for the Device 4 with L_g = 30 nm and W_fin = 25 nm. We can determine the (V_GS-V_T) at which quantum interference occurs for each n (indicated by arrows).

-1.5E-3 -1.0E-3 -5.0E-4 0.0E+0 5.0E-4 1.0E-3 1.5E-3

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

-V

(V)

G

'/ V

( S /V

)

Non-overlapped Device 4 L_g=30nm W_fin=25nm DC meas. @ V_{D S}=2mV AC meas. @ V_{D S}=2mV DC meas. @ V_{D S}=50mV

n=1

n=2

n=3 n=4

Fig. 2.18. DC and AC measurement results of ∂G_m/∂V_GS vs. V_GS-V_T for the Device 5 with L_g = 30 nm and W_fin = 25 nm.

-1.0E-3 -5.0E-4 0.0E+0 5.0E-4 1.0E-3 1.5E-3

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

-V

(V)

G

'/ V

( S /V

)

DC AC

Non-overlapped Device 5 Lg=30nm W_fin=25nm V_{D S}=2mV

n=1

n=2

n=3 n=4

Fig. 2.19. Extracted VGS-dependent Leff for the non-overlapped multiple-gate FinFETs with Lg = 30 nm and Wfin = 25 nm.

10 15 20 25 30 35

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V

-V

(V)

L

eff

(n m )

meas. Lg=30nm

simu. Lg=30nm

average of 6 devices

1E+18 1E+20

0 20 40 60 80

channel direction (nm)

carrier density (cm-3 ) S D

V_GS=0~1V L_{e ff}

Fig. 2.20. A schematic carrier density plot along the channel between source and drain for the non-overlapped gate to source/drain structure at V_GS = 0 to 1 V. L_eff is determined based on the inversion-layer sheet conductivity.

Chapter 3 Single-Electron Effects of Non-overlapped Multiple-Gate SOI MOSFETs

3.1 Introduction

A single-electron transistor (SET) consists of a conducting island connected to two electron reservoirs through tunnel barriers [1]. When the size of the island as well as its capacitances is scaled sufficiently small, the conductivity is determined by single charge and shows periodicity. Many studies in the past [1]-[7] have pointed out that SET is a promising candidate for ultralow-power and ultrahigh-density circuit systems in the next generation [2]-[3]. Especially, the SET with standard silicon nano-electronics process and compatible with existing complementary metal-oxide-semiconductor (CMOS) device architectures is very attractive. Although various novel silicon-based SETs have been reported for superior room-temperature performance and functionality [4]-[6], it is difficult for these SETs to be compatible with state-of-the-art CMOS devices.

A direct way to realize CMOS-compatible SETs is raising Coulomb blockade effects [7] in real CMOS devices. Table 3.1 lists several studies of silicon-based SETs with MOS structures, and reveals that downsizing the SET is essential to achieving the Coulomb blockade oscillation (CBO). The key parameter is the constriction of carriers (i.e., the control of tunnel barriers and the suppression of short-channel effects). In [8], one approach of electronic confinement, using the non-overlapped-gate architecture as tunnel barriers, has been employed to produce controlled single-electron effects in real

(i.e., source/drain resistances) yields CBO in ultra-thin silicon-on-insulator (SOI) MOSFETs. In [20], using the multiple-gate structure to overcome the short-channel effect, significant CBO has been shown. Although these studies represent attractive schemes to build SETs on large-scale wafers, charging energy is small (less then about 6 mV) and is not suitable for room-temperature applications. To allow high-temperature operation, the size of dots needs to be reduced. Therefore, the purpose of this work is to explore further into combining more than one approach in ultra-scaled CMOS devices.

Since multiple-gate SOI MOSFETs are considered as a promising candidate for ultra-scaled CMOS [10], we have conducted an assessment of single-electron effects in these devices near room temperature [11][32]. The single-electron effects reported in [11] and [32] is associated with the presence of tunnel barriers in spacer-defined non-overlapped gate to source/drain regions. Besides, high source/drain resistances in narrow multiple-gate devices further facilitate the constriction of carriers. To the best of our knowledge, it is the first demonstration of single-electron effects in multiple-gate SOI MOSFETs with non-overlapped gate to source/drain structure at room temperature.

We have also noted that similar ideas have been reported in [23] and [24] after our study [11] [32].

We further demonstrate controlled single-electron effects in these devices through a comprehensive investigation on the observed single-electron effects, which can be modulated by geometry and applied bias. Moreover, the role of access resistances [9] and the gate-dot coupling strength [12] are assessed. The organization of this chapter is as follows. In Section 3.2, the theory of CBO is presented. In Section 3.3, we describe our device structure that features the non-overlapped architecture. Then, we systematically present single-electron effects for devices with various gate length (Lg), fin width (Wfin), gate bias (VGS), body doping (NB) and temperature. The impact of

access resistances [9], the estimation of gate-dot coupling strength [12] and phenomena of split-peak separations are discussed in Section 3.4. In Section 3.5, a new approach of capacitance extraction is presented. Finally, the conclusion will be drawn in Section 3.6.

3.2 Coulomb blockade oscillation

In this section we examine the circumstances under which Coulomb charging effects are important. Considering the electronic properties of the small island depicted in Fig. 3.1, charge exchange can occur only with source and drain terminals. The gate electrode provides an electrostatic or capacitive coupling through the gate capacitance C_g. The number of charges on this island is an integer with a quantized number N. When source-island (or drain-island) tunneling occurs, the charge on the island suddenly changes by the quantized amount e. The associated change in the Coulomb energy ∆E is expressed in terms of the capacitance C_g of the island as ∆E ~ e²/C_g. This charging energy becomes important when it exceeds the thermal energy kBT, i.e., e²/Cg > kBT [25]. A second requirement is that the barriers are sufficiently opaque such that the electrons are located either in the source, in the drain, or on the island. This means that over a time scale of ∆t, changing of the charge number on the island is much less than one. Typically, ∆t ≈ RbarrierCg, where Rbarrier represents the tunnel resistance of the barrier. From the Heisenberg uncertainty relation, ∆E∆t > h, we can obtain R_barrier > h/e² [25], which implies that for an ideal tunnel barrier, Rbarrier should be much larger than the resistance quantum h/e² = 25813 Ω.

Under these two criterions (i.e., e²/C_g > k_BT and R_barrier > h/e²), the conductance of the island is determined by serially discrete energy levels, which can be modulated by the gate voltage V_GS. Fig. 3.2 shows that while V_GS increases the island’s electrostatic energy through Cg, the tunneling of charges can compensate the increased energy state with a discrete integer. In other words, there is the energy competition between V and

the induced charge, which leads to so-called Coulomb blockade. Note that only when the increased energy state is charged, the island is conductive. With continually increasing VGS, discrete energy levels sequentially contribute discontinuous conductance at the corresponding V_GS and thus result in conductance oscillations, that is, Coulomb blockade oscillation.

3.3 Experimental measurement of single-electric effects

In this section we analyze the features of periodic oscillations in G_m (= ∂I_D/∂V_GS).

DC current-voltage measurements (ID–VGS) were carefully performed using the Agilent 4156C precision semiconductor parameter analyzer in low-noise probe stations. In Section 3.3.1, we present the multiple-gate MOSFET with the non-overlapped structure.

Experiments on the multiple-gate device with Lg = 30 nm and Wfin = 25 nm at different temperatures are described in Section 3.3.2. The geometry dependence, the V_GS dependence and the NB dependence are analyzed in Sections 3.3.3 to 3.3.5, respectively.

3.3.1 Devices

The process flow for fabricating MuGFETs is similar to that reported in [33]. Fig.

3.4(a) shows the schematic view of the multi-gate SOI MOSFETs investigated in this study. Our devices were fabricated on separation by implantation of oxygen (SIMOX) SOI wafers using standard CMOS optical lithography [13]. The Si-body thickness, H_fin, was thinned down to about 40 nm by thermal oxidation. The fin width, Wfin, was defined by wet-etching and is about 15 and 25 nm. After Wfin was developed, the Si-body fin was doped with B⁺ with doping concentration, N_B, about 6×10¹⁸ and 3×10¹⁸ cm^-3. Afterward the 1.6-nm gate oxide was thermally grown. The ultra-thin gate oxide contributes to not only the suppression of short-channel effects, but also the gate-dot coupling strength of the SET [12]. The in-situ heavily-doped N⁺ poly-silicon was

the gate length, L_g, was defined and ranges from 30 to 40 nm. Without the light-doping-drain/source (LDD/LDS) implantation, the composite spacer of silicon oxide and nitride was deposited and anisotropically etched. Finally, heavily-doped N⁺ source/drain was made. It is worth noting that all the processes are essentially the same as traditional CMOS technologies.

Table 3.2 lists the information of tested devices in this work. The main feature of our device structure is the non-overlapped gate to source and drain regions, which are defined by spacers, as depicted in Fig. 3.4(b). With increasing the gate voltage, there is larger carrier concentration under the gate electrode than in the non-overlapped regions (Fig. 3.4(c)). In other words, the non-overlapped regions separate inversed carriers from source/drain and act as the electrostatic tunnel barriers of the single-electron tunneling [8]. It is worth noting that the size of tunnel barriers depends on the non-overlapped regions as well as the spacers. Optimum tunnel barriers can be controlled through modulating the width of spacers. In addition, the high source/drain resistances that are intrinsic to the multiple-gate SOI structure are useful for the constriction of carriers [9].

3.3.2 Single-electric effects in multiple-gate devices

Figure 3.5(a) shows the Gm–VGS characteristics measured at room temperature (T

= 20 ^oC) for the Device 1 with L_g= 30 nm and W_fin = 25 nm. Periodic oscillations, an indication of the CBO [14], in the Gm–VGS characteristics can be seen. Such periodic oscillations in Gm can be reproduced for the Device 2 with the same size, as shown in Fig. 3.5(b). It is worth noting that the peaks of each period may be repeated at the same gate bias. For devices with large dimensions under the same measurement system, nevertheless, only the thermal noise can be seen. Therefore, the effect of equipments, such as the effect of source accuracy [15], is not responsible for the observed periodic oscillations. We have also noticed that the channel conductance (G = ∂I /∂V ) is on

the same order of magnitude as e²/h (~3.87×10^-5 S), which has been considered as one of the most important criteria for the CBO [1][9].

Figure 3.6(a) shows the oscillating components, Gm-<Gm>, for the data in Fig.

3.5(a). The period, ∆V_G, can be observed to be ~17 mV. When the temperature decreases from 293 to 233 K, as shown in Fig. 3.6(b), the oscillations are reproducible with the same period. To further analyze the periodic oscillations, both the discrete fast Fourier transform (FFT) [16] and the histogram of the directly counted peak-to-peak spacing (∆VG) [8,9] can be applied. It can be confirmed from Fig. 3.7 that the observed conductance oscillations in Fig. 3.5 follow Gaussian distribution [8,17-19] with a mean period (<∆VG>) ~17 mV and a standard deviation (sd) ~3.5 mV. The normalized width of the distribution [8], sd/<∆VG>, is about 0.2. Similar results have also been obtained in [8] for single-electron effects in planar bulk MOSFETs with the non-overlapped-gate architecture. The Gaussian shape of the ∆VG distribution has been explained in terms of the charging energy level dynamics due to shape deformation of the quantum dot [17,18]. In other words, the shape of the quantum dot in our device is not fixed and is deformed by VGS, which can be understood from the simulated VGS-controlled tunnel barriers shown in Fig. 3.4(c).

3.3.3 L

& W

_fin

dependence

The period of Gm oscillations, <∆VG>, represents the charging energy and is related to the gate capacitance by e/Cg [1]. For our multiple-gate devices, the gate capacitance C_g is associated with the effective gate area A_eff (i.e., 2H_finL_g). Therefore, we expect that the period <∆VG> decreases as Lg increases. Fig. 3.8 shows the Gm–VGS

characteristics for the Device 3 with L_g = 40 nm and W_fin = 25 nm at T = 20 ^oC. The phenomenon of Gm oscillation can still be observed with <∆VG> ~15 mV. Compared with the 17-mV period for the Device 1 and 2 with L = 30 nm, the decreased <∆V >

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