Chapter 5 Gate-Tunneling Current Induced Capacitance-Voltage
5.5 Experimental reconstruction
In this section, we demonstrate that the concept of Rii can be used to develop a simple method for the inversion C–V reconstruction for long-channel devices. As the conventional three-element model (Fig. 5.10(a)) is used to represent the small-signal equivalent model of a leaky MOS capacitor, the total series resistance, Rs, can be calculated by Rii + Rge + Rsd/2. The factor of 1/2 accounts for the Rsd induced de-biasing effect caused by one half of Ig. The inversion C–V may then be reconstructed by [20], [23]:
2 using the parallel circuit model of the LCR meter (Fig. 5.10(b)). The value of Rii can be extracted from the channel resistance (Fig. 5.9(a)). The values of Rge and Rsd can also be measured by standard procedures.
Fig. 5.11(a) and Fig. 5.11(b) show the measured inversion capacitance and our reconstructed C–V characteristics for NMOS and PMOS with Lg = 10 µm and W = 10 µm, respectively. The impact of Rii on the reconstructed results can be seen. Moreover, the correction for PMOS is larger because the lower PMOS channel mobility may result in a higher channel resistance and Rii. Besides, the reconstructed C–V characteristics show a slight decrease in the high gate bias regime. This can be attributed to poly-depletion effects. Also shown in Fig. 9 are the theoretical characteristics provided by the NCSU CVC (C–V analysis software developed by the North Carolina State University) [14]. Note that merely using the two-frequency three-element method [3]-[4], [22]-[23] has been known [7][14] to be unable to show the poly-depletion effect because of the limited number of elements. Using the Rii approach to fully account for the distributed effect together with the three-element model, however, our reconstructed C–V curves show poly-depletion effects and agree with the NCSU-CVC simulation
5.6 Conclusion
We have investigated the inversion C–V reconstruction and assessed the feasibility of the concept of intrinsic input resistance for long-channel MOSFETs. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Using the Rii approach in the inversion C–V reconstruction is more accurate and efficient than the segmented simulation approach. Our reconstructed C–V characteristics show poly-depletion effects and agree well with the NCSU-CVC simulation results. The intrinsic input resistance dominates the overall gate-current induced de-biasing effect (~95% for Lg = 20 µm) and can be extracted directly from the I–V characteristics. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.
References
[1] P.A. Kraus, K.Z. Ahmed, and J.S. Williamson Jr., “Elimination of Chuck-Related Parasitics in MOSFET Gate Capacitance Measurements,” IEEE Trans. Electron Devices, vol. 51(8), p. 1350, Aug. 2004.
[2] Z. Luo and T.P. Ma, “A New Method to Extract EOT of Ultrathin Gate Dielectric With High Leakage Current,” IEEE Electron Device Letters, vol. 25(9), p. 655, Sept. 2004.
[3] K.J. Yang and C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46(7), p. 1500, July 1999.
[4] A. Nara, N. Yasuda, H. Satake, and A. Toriumi, “Applicability Limits of the Two-Frequency Capacitance Measurement Technique for the Thickness Extraction of Ultrathin Gate Oxide,” IEEE Trans. Semiconductor Manufacturing,
[5] W. Lee, K.-W. Su, C.-S. Chiang, S. Liu, and P. Su, “Inversion MOS Capacitance Extraction for Ultra-Thin Gate Oxide using BSIM4,” Proc. IEEE 2005 VLSI-TSA Int. Symp. VLSI Technology, p. 62, April 2005.
[6] C.-H. Choi, Y. Wu, J.-S. Goo, Z. Yu, and R.W. Dutton, “Capacitance Reconstruction from Measured C-V in High Leakage, Nitride/Oxide MOS,” IEEE Trans. Electron Devices, vol. 47(10), p. 1843, Oct. 2000.
[7] D.W. Barlage, J.T. O’Keeffe, J.T. Kavalieros, M.M. Nguyen, and R.S. Chau,
“Inversion MOS Capacitance Extraction for High-Leakage Dielectrics Using a Transmission Line Equivalent Circuit,” IEEE Electron Device Letters, vol. 21(9), p. 454, Sep. 2000.
[8] D. Rideau, P. Scheer, D. Roy, G. Gouget, M. Minondo, and A. Juge, “Series Resistance Estimation and C(V) Measurements on Ultra Thin Oxide MOS Capacitors,” IEEE Int. Conf. Microelectronic Test Structures, p. 191, March 2003.
[9] K. Ahmed, E. Ibok, G. C.-F. Yeap, Q. Xiang, B. Ogle, J. J. Wortman, and J. R.
Hauser, “Impact of Tunnel Currents and Channel Resistance on the Characterization of Channel Inversion Layer Charge and Polysilicon-Gate Depletion of Sub-20-Å Gate Oxide MOSFETs,” IEEE Trans. Electron Devices, vol. 46(8), p. 1650, Aug. 1999.
[10] X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, “An Effective Gate Resistance Model for CMOS RF and Noise Modeling,” IEDM Tech. Dig., p. 961, 1998.
[11] W. Lee, P. Su, K.-W. Su, C.-S. Chiang, and S. Liu, “Investigation of Inversion C-V Reconstruction for Long-Channel MOSFETs with Leaky Dielectrics using Intrinsic Input Resistance Approach,” Int. Conf. Solid State Devices and Materials, p. 416, Sept. 2006.
[12] W. Liu, MOSFET Models for SPICE Simulation including BSIM3v3 and BSIM4, John Wiley & Sons, 2001.
[13] Evaluation of MOS Capacitor Gate Oxide C-V Characteristics Using the Agilent 4294A, Agilent Technologies Application Note PN4294-3.
[14] J.-S. Goo, T. Mantei, K. Wieczorek, W.G. En, and A.B. Icel, “Extending Two-Element Capacitance Extraction Method Toward Ultraleaky Gate Oxides Using a Short-Channel Length,” IEEE Electron Device Letters, vol. 25(12), p. 819, Dec. 2004.
[15] L. Pantisano, J. Ramos, E.S. A. Serrano, Ph. J. Roussel, W. Sansen, and G.
Groeseneken, “A comprehensive model to accurately calculate the gate capacitance and the leakage from DC to 100 MHz for ultra thin dielectrics,” IEEE Int. Conf. Microelectronic Test Structures, p. 222, March 2006.
[16] J. Schmitz, F.N. Cubaynes, R.J. Havens, R. de Kort, A.J. Scholten, and L.F.
Tiemeijer, “Test Structure Design Considerations for RF-CV Measurements on Leaky Dielectrics,” IEEE Trans. Semiconductor Manufacturing, vol. 17(2), p. 150, May 2004.
[17] J. Schmitz, F.N. Cubaynes, R.J. Havens, R. de Kort, A.J. Scholten, and L.F.
Tiemeijer, “RF Capacitance-Voltage Characterization of MOSFETs With High Leakage Dielectrics,” IEEE Electron Device Letters, vol. 24(1), p. 37, January 2003.
[18] C. Yu, J. Zhang, J.S. Yuan, F. Duan, S.K. Jayanarananan, A. Marathe, S. Cooper, V. Pham, and J.-S. Goo, “Evaluation of RF Capacitance Extraction for Ultrathin Ultraleaky SOI MOS Devices,” IEEE Electron Device Letters, vol. 28(1), p. 45, January 2007.
[19] W.K. Henson, K.Z. Ahmed, E.M. Vogel, J.R. Hauser, J.J. Wortman, R.D.
Venables, M. Xu, and D. Venables, “Estimating Oxide Thickness of Tunnel Oxides Down to 1.4nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors,” IEEE Electron Device Letters, vol. 20(4), p. 179, April 1999.
[20] E.M. Vogel, W.K. Henson, C.A. Richter, and J.S. Suehle, “Limitations of Conductance to the Measurement of the Interface State Density of MOS Capacitors with Tunneling Gate Dielectrics,” IEEE Trans. Electron Devices, vol.
47(3), p. 601, March 2000.
[21] G. Ghibaudo, S. Bruyère, T. Devoivre, B. DeSalvo, and E. Vincent, “Improved Method for the Oxide Thickness Extraction in MOS Structures with Ultrathin Gate Dielectrics,” IEEE Trans. Semiconductor Manufacturing, vol. 13(2), p. 152, May 2000.
[22] D.K. Schroder, Semiconductor Material and Device Characterization, 3rd Edition (John Wiley & Sons, Inc., New York).
[23] A.M. Goodman, “Metal-Semiconductor Barrier Height Measurement by the Differential Capacitance Method-One Carrier System,” J. Appl. Phys., 34(2), p.
329, Feb. 1963.
Fig. 5.1. (a) Inversion MOS capacitance (Cgc) for the short-channel (Lg = 0.24µm) device. C0: true capacitance for Lg = 10 µm. (b) The variation of Cm increases as Lg
decreases. Cm: measured capacitance. <Cm>: Cm mean.
(a)
(b)
95 100 105
0.1 1 10
Gate Length, L (µm)
Cm/<Cm> (%)
-0.1 0.0 0.1 0.2 0.3
-0.5 0 0.5 1 1.5
VGS (V)
Cgc/C0
: measurement w / calibrations : measurement w /o calibrations line : BSIM4 simu. w /o gate tunneling
15-array L=0.24µm
Fig. 5.2. (a) The impact of cable inductance, Ls, on Cgc. (b) Frequency dependence of the measured Cgc.
(a)
(b)
-1.0 -0.5 0.0 0.5 1.0
-0.5 0 0.5 1 1.5
VGS (V) Cgc/C0
w / SHORT calibration w /o SHORT calibration
Cable inductance effect
Ls
C
R
0.0 0.5 1.0 1.5 2.0
1E+4 1E+6 1E+8
frequency (Hz) Cgc/C0 VGS=0.3~1.5V
frequency indepedent
region
Fig. 5.3. (a) BSIM4-based macro model. Cf: fringing capacitance. R4 = 1x109 Ω, C4 = 1x10-9 F.
: VCCS
C4
Device part
D
B S
Ls+Li
R4 Ls+Li G
Rge
S/D extension
Rsd
Rsd
Cf
Cf
Ls+Li
Fig. 5.3. (b) Our BSIM4 extraction methodology of the inversion MOS capacitance.
SPICE DC curves fitting: VT(:
vth0), Igc, Igsd, Id,lin(:μ, Rsd, Rge) SPICE AC curves fitting:
dtox, Leff, Cf, Voff
Obtain the true Cgc by the gate-tunneling-free simulation Obtain the cable-inductance-free Cgc
by OPEN & SHORT calibrations DC meas.:
Id,lin-VG, Ig-VG
Extract Li
iteration
Fig. 5.4. (a) Merely considering Rge and Rsd without taking Li into account cannot model the Cgc characteristics in the high gate bias regime. (b) In the same MOS array of short-channel devices, the impact of on-chip inductance (Li) depends on the measurement configuration. (For the SD-G case, the Hi port is connected to source/drain, while the Lo port to the gate electrode.)
(a)
-1.1 0.0 1.1
-0.5 0 0.5 1 1.5
VGS (V)
Cgc/C0
single device Lg=10µm
: simu. Ig off
: simu. w /o Li, Rg e, Rsd : simu. w / Li, Rg e, Rsd : simu. w / Li, Rg e, Rsd, Ls : meas. w / calibrations : meas. w /o calibrations
Fig. 5.5. The segmented SPICE simulation reveals the importance of calibrations and the distributed effect for the long channel device.
measured cable inductance Ls
1 1.1 1.2 1.3 1.4 1.5
1000 100000 10000000
frequency (Hz)
Ls (µH)
Fig. 5.6. The cable inductance Ls vs. frequency characteristics. ~1µH Ls can be excluded after performing the SHORT calibration.
Fig. 5.7. (a) DC and (b) AC verification of the segmented SPICE simulation for the
Fig. 5.8. (a) The gate-tunneling induced C–V attenuation due to de-biasing effect can be simulated by BSIM4/SPICE simulation. (b) The gate currents simulated by the segmented simulation and the Rii lumped simulation are nearly identical.
0.1
Fig. 5.8. (c) Segmented SPICE simulation with each sub-transistor modeled by the BSIM4 MOSFET model. (d) Single-transistor SPICE simulation with Rii added to the gate terminal in addition to Rge.
Rge
Rsd Rsd
(c)
Rge+Rii
Rsd
Rsd
(d)
Fig. 5.9. (a) Rii for Lg = 10 µm device can be extracted from the DC output
Fig. 5.10. Small-signal equivalent models for MOS capacitor. (a) Three-element model. (b) Two-element parallel model.
(a) (b)
C ox R S
G ox
G m C m
Fig. 5.11. Reconstructed C–V characteristics for (a) NMOS and (b) PMOS with and reconstructed Cgc w /o Rii measured Cgc (Cm) reconstructed Cgc w /o Rii measured Cgc (Cm) NCSU CVC simu.
PMOSFET
L=10µm, W =10µm
(b)
Fig. 5.12. The contribution of intrinsic input resistance in the overall gate-current induced de-biasing effect. Rs = Rii+Rge+Rsd/2.
0 20 40 60 80 100
0.1 1 10 100
Gate Length, L (µm)
Rii/Rs (%)
W =10µm
VGS=1.5V (Rii)
Distributed effect : meas. data
line : BSIM4 simu.
Chapter 6 Conclusions
In this dissertation, we have systematically performed comparative investigation for various kinds of nanoscale MOSFETs including the overlapped vs. non-overlapped multiple-gate SOI MOSFETs, the strain vs. unstrained planar MOSFETs, the SiO2 vs.
HfO2 dielectrics, the high vs. low body doping, the SOI vs. bulk MOSFETs, and ultra-thin gate dielectrics. For multiple-gate SOI MOSFETs, quantum-mechanical confinement effects and quantum-mechanical interference effects may prevail in the narrow overlapped devices and the non-overlapped devices, respectively [1]-[2].
Besides, controlled single-electron effects have also been observed in the non-overlapped devices especially for smaller gate length and fin width [3]-[5]. In addition, channel backscattering characteristics have been successfully, physically and experimentally extracted through the newly developed self-consistence temperature- dependence extraction method [6]-[7]. We found that ballistic efficiency can be enhanced by compressive strain for PMOSFETs and is degraded by high body doping and high-k dielectric. Moreover, for the gate-tunneling current induced capacitance-voltage problem, we have proposed a simple reconstruction method [8].
Several important results were obtained and summarized as follows:
1. In Chapter 2, we have conducted a comparative study of carrier transport characteristics for multiple-gate SOI MOSFETs with and without the non-overlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the non-overlapped devices, however, we found insensitive temperature dependence of drain current in both subthreshold and inversion
regimes. Our low-temperature measurements indicate that the inter-subband scattering (i.e., quantum-mechanical confinement effects) may dominate carrier
transport mechanism for narrow overlapped multiple-gate devices. For the non-overlapped multiple-gate devices, the voltage-controlled potential barriers in the non-overlapped regions may give rise to the weak localization effect (conductance reduction) and the quantum interference fluctuations. Based on the wave nature of channel electrons, we have experimentally obtained the gate-voltage-dependent effective channel length for the non-overlapped multiple-gate SOI MOSFETs, which agrees with the simulation results.
2. In Chapter 3, we have systematically investigated controlled single-electron effects in multiple-gate SOI MOSFETs with various gate length, fin width, gate voltage, body doping and temperature. Our study indicates that using the non-overlapped
gate to source/drain structure as an approach of the single-electron transistor (SET) in MOSFETs is promising. Combining the advantage of gate control and the constriction of high source/drain resistances, single-electron effects are further enhanced using the multiple-gate architecture. From the presented results, downsizing multiple-gate SOI MOSFETs is needed for future room-temperature SET applications. Since single-electron effects can be achieved in state-of-the-art CMOS devices, it is beneficial to built SETs in low-power CMOS circuits for the ultrahigh-density purpose. In addition, we have analyzed gate capacitance as well as source/drain capacitance of multiple-gate SOI MOSFETs.
3. In Chapter 4, we have reported a generalized self-consistent temperature-dependent channel backscattering extraction method. We have also investigated the limitation of this self-consistent method and proposed guidelines for experimental extraction.
Using the generalized temperature-dependent method, we have shown that the
channel backscattering of nanoscale PMOSFETs can be reduced by the uniaxially compressive strain. Besides, channel backscattering is increased for NMOSFETs with higher body doping and HfO2 dielectric. In addition, our results indicate that on one hand the floating-body effect may decrease the channel backscattering in high drain bias regime, and on the other hand the self-heating effect may increase channel backscattering. We further demonstrate that the strain technology can improve the drain current variation through the enhanced ballistic efficiency. We believe that the generalized temperature-dependent extraction method is competent to be routinely used in technology development for the process monitoring purpose.
4. In Chapter 5, we have investigated the inversion C−V reconstruction and assessed the feasibility of the concept of intrinsic input resistance (Rii) for long-channel MOSFETs. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Using the Rii approach in the inversion C−V reconstruction is more accurate and efficient than the segmented simulation approach. Our reconstructed C−V characteristics show poly-depletion effects and agree well with the
NCSU-CVC simulation results. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.
Finally, it is worth noting that we have proposed an effective channel length extraction in Chapter 2 using the quantum interference effects. Similar ideas have been developed to determine the Si/SiO2 interface roughness for bulk MOSFETs [10] and the diameter of the nanowire devices [11]. In Chapter 3, we have demonstrated that the single-electron effect is competent to be used in the aF-scale capacitance extraction.
Recently, this concept has been employed in [12] for the nanoscale multi-channel devices. We believe that the feasibility of using mesophysics (buttom-up approaches) to determine important device parameters for nanoscale MOSFETs is promising.
References
[1] W. Lee and P. Su, “A Comparative Study of Carrier Transport for Overlapped and Non-overlapped Multiple-Gate SOI MOSFETs,” IEEE Trans. on Nanotechnology, 2009, to be published.
[2] W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “An Experimental Assessment of Quantum Interference in Multiple-Gate SOI nMOSFETs with Non-Overlapped Gate to Source/Drain Structure near Room Temperature,” Proc.
of the 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, p. 15, June 2007.
[3] W. Lee and P. Su, “Single-electron effects in non-overlapped multiple-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors,”
Nanotechnology, vol. 20, p. 065202, Feb. 2009.
[4] W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature,” IEEE Electron Device Letters, vol. 27(3), pp. 182−184, March 2006.
[5] W. Lee and P. Su, “A Comprehensive Study of Single-Electron Effects in Multiple-Gate MOSFETs,” Proc. of the 2008 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2008.
[6] W. Lee and P. Su, “Investigation of Channel Backscattering Characteristics in Nanoscale Uniaxial Strained PMOSFETs,” IEEE Trans. on Nanotechnology, 2009 (conditionally accepted)
[7] W. Lee and P. Su, “Investigation of Channel Backscattering Characteristics for Nanoscale SOI MOSFETs Using a New Temperature-Dependent Method,” Proc.
of the 2008 IEEE International SOI Conference, New York, USA, pp. 73−74, October 2008.
[9] W. Lee, P. Su, K. Su, C. Chiang, and S. Liu, “Investigation of Anomalous Inversion C-V Characteristics for Long-Channel MOSFETs with Leaky Dielectrics : Mechanisms and Reconstruction,” IEEE Trans. on Semiconductor Manufacturing, vol. 21(1), pp. 104−109, Feb. 2008.
[10] W. R. Anderson, D. R. Lombardi, R. G. Wheeler, and T.-P. Ma, “Determination of Si/SiO2 interface roughness using weak localization,” IEEE Electron Device Letters, vol. 14(7), pp. 351−353, July 1993.
[11] A.T. Tilke, F.C. Simmel, H. Lorenz, R.H. Blick, and J.P. Kotthaus, “Quantum interference in a one-dimensional silicon nanowire,” Phys. Rev. B, vol. 68, p.
075311, 2003.
[12] M. Hofheinz, X. Jehl, M. Sanquer, R. Cerutti, A. Cros, P. Coronel, H. Brut, and T.
Skotnicki, “Measurement of capacitances in multigate transistors by coulomb blockade spectroscopy,” IEEE Trans. on Nanotechnology, vol. 7(1), pp. 74−78, 2008.
簡簡 簡簡 歷歷歷歷 姓名: 李維
性別: 男
生日: 68 年 6 月 24 日 籍貫: 台北市
通訊地址: 112 台北市 北投區吉利街 257 巷 4 弄 10 號 5 樓 學歷:
博士論文題目:
矽奈米尺寸金氧半場效電晶體的載子傳輸與 重要元件參數之實驗性的研究
Experimental Study of Carrier Transport and
Important Device Parameters for Nanoscale Si MOSFETs Grade Name of School, Major Year
High School 師大附中 1994~1997
College 清華大學
工程與系統科學系 1997~2001
Master 交通大學
電子研究所 2001~2003
Ph.D. 交通大學
電子研究所 2003~2009
著著
著著 作作作作 目目目目 錄錄錄錄
A. International Journal
1. W. Lee and P. Su, “Single-electron effects in non-overlapped multiple-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors,”
Nanotechnology, vol. 20, p. 065202, Feb. 2009. (A 類期刊—SCI)
2. W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature,” IEEE Electron Device Letters, vol. 27(3), pp.
182−184, March 2006. (A 類期刊—SCI)
3. W. Lee and P. Su, “A Comparative Study of Carrier Transport for Overlapped and Non-overlapped Multiple-Gate SOI MOSFETs,” IEEE Trans. on Nanotechnology, 2009, to be published. (A 類期刊—SCI)
4. W. Lee and P. Su, “Investigation of Channel Backscattering Characteristics in Nanoscale Uniaxial Strained PMOSFETs,” IEEE Trans. on Nanotechnology, 2009. (A 類期刊—SCI) (conditionally accepted)
5. W. Lee, P. Su, K. Su, C. Chiang, and S. Liu, “Investigation of Anomalous Inversion C-V Characteristics for Long-Channel MOSFETs with Leaky Dielectrics : Mechanisms and Reconstruction,” IEEE Trans. on Semiconductor Manufacturing, vol. 21(1), pp. 104−109, Feb. 2008. (A 類期刊—SCI)
6. P. Su and W. Lee, “On the Prediction of Geometry-Dependent Floating-Body Effect in SOI MOSFETs,” IEEE Trans. on Electron Devices, vol. 52(7), pp.
1662−1664, July 2005. (A 類期刊—SCI)
7. P. Su and W. Lee, “Modeling Geometry-Dependent Floating-Body Effect Using Body-Source Built-In Potential Lowering for SOI Circuit Simulation,”
Jpn. J. Appl. Phys., vol. 44(4B), pp. 2366−2370, April 2005. (B 類期刊—SCI) 8. W. Lee, P. Su, K. Su, C. Chiang, and S. Liu, “Investigation of Inversion C-V
Reconstruction for MOSFETs with Leaky Dielectrics using BSIM4/SPICE and Intrinsic Input Resistance Model,” Jpn. J. Appl. Phys., vol. 46(4B), pp.
1870−1873, April 2007. (B 類期刊—SCI)
9. W. Lee and P. Su, “On the Experimental Determination of Channel Backscattering Characteristics – Limitation and Application for the Process Monitoring Purpose,” IEEE Trans. on Electron Device. (投稿中)
B. International Conference
10. P. Su and W. Lee, “Modeling Geometry-Dependent Floating-Body Effect using Body-Source Built-In Potential Lowering for Scaled SOI CMOS,” 2004 Int.
Conf. Solid State Devices and Materials (SSDM), Tokyo, Japan, pp. 510−511.
11. W. Lee, K. Su, C. Chiang, S. Liu, and P. Su, “Inversion MOS Capacitance Extraction for Ultra-Thin Gate Oxide using BSIM4,” Proc. of the IEEE 2005 VLSI-TSA Int. Symp. VLSI Technology, Hsinchu, Taiwan, pp. 62−63, April 2005.
(研討會論文—國際) (Oral presentation)
12. W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature,” Proc. of 2005 Int. Semiconductor Device Research Symposium (ISDRS), Washington D.C., USA, pp.175−176, Dec. 2005.
(研討會論文—國際) (Oral presentation)
13. W. Lee, P. Su, K. Su, C. Chiang, and S. Liu, “Investigation of Inversion C-V Reconstruction for Long-Channel MOSFETs with Leaky Dielectrics using Intrinsic Input Resistance Approach,” 2006 Int. Conf. Solid State Devices and Materials (SSDM), Yokohama, Japan, Sept. 2006. (研討會論文—國際)
14. W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “Controlled Single-Electron Effects in Multiple-Gate SOI MOSFETs near Room Temperature,” Proc. of the 2006 IEEE Int. SOI Conf., Niagara Falls, New York, USA, Oct. 2006. (研討會論文—國際)
15. W. Lee, P. Su, H. Chen, C. Chang, K. Su, S. Liu, and F. Yang, “An Experimental Assessment of Quantum Interference in Multiple-Gate SOI nMOSFETs with Non-Overlapped Gate to Source/Drain Structure near Room Temperature,” Proc. of the 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, p. 15, June 2007. (研討會論文—國際) (Oral presentation)
16. W. Lee and P. Su, “A Comprehensive Study of Single-Electron Effects in Multiple-Gate MOSFETs,” Proc. of the 2008 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2008. (研討會論文—國際) (Oral presentation)
17. W. Lee and P. Su, “Investigation of Channel Backscattering Characteristics for Nanoscale SOI MOSFETs Using a New Temperature-Dependent Method,”
Proc. of the 2008 IEEE Int. SOI Conf., New York, USA, pp. 73−74, October
Proc. of the 2008 IEEE Int. SOI Conf., New York, USA, pp. 73−74, October