Application of ballistic efficiency to suppression of drain current

A simple expression relating Id of nanoscale MOSFETs to µ0 has been derived by Lundstrom [35] as

( )(

B

)

I

I_{d d} = δµ₀ µ₀ 1−

δ (16),

in which the sensitivity of Id to µ0 is determined by the ballistic efficiency B. Eq. (16) reveals that the impact of the µ₀ variation, σ(µ₀)/µ₀, on the I_d,sat variation, σ(I_d,sat)/I_d,sat, can be suppressed when the ballistic efficiency B is enhanced. To ensure that the VT

variation does not affect the following analysis, we have confirmed in Fig. 4.22 that the standard deviation of VT, σ(VT), as well as the VT variation, σ(VT)/VT, are similar between strained and unstrained devices. The linear dependence of σ(Id,sat)/Id,sat on σ(µ₀)/µ₀ presented in Fig. 4.23 follows the prediction of Eq. (16), in which the slope represents the degree of ballistic efficiency B. The reduced slope for strained PFETs (Fig. 4.23) can be explained by the Bsat enhancement (Bsat,strained-Bsat,unstrained) (Fig. 4.24).

It is worth noting that the suppression of σ(I_d,sat)/I_d,sat (Fig. 4.23), the B_sat enhancement (Fig. 4.24) and the µ enhancement (Fig. 4.24) are more significant with decreasing Lg. Besides, we found that the B enhancement decreases with decreasing Vds (Fig. 4.25), which may be referred to the relation of B ~ λ/(L+λ) for low V_ds, i.e., the λ enhancement is not important for λ/(L+λ) as L >> λ. Such Vds dependence of the B enhancement results in the weak suppression in the σ(I_d)/I_d vs. σ(µ₀)/ µ₀ characteristics measured at V_ds = 0.3 V as shown in Fig. 4.26.

4.8 Conclusion

We have reported a generalized temperature-dependent channel backscattering extraction method that can self-consistently determine β in nanoscale MOSFETs.

Through comparing the Vgs and temperature dependence, we have shown that assuming βµ and β_l constants will result in unphysical backscattering characteristics. We have also investigated the limitation in the self-consistent approach and proposed guidelines for experimental extraction. Using an generalized temperature-dependent method, we have shown that the r of nanoscale PMOSFETs can be reduced by the uniaxially

compressive strain. Besides, r_sat is increased for NMOSFETs with higher N_a and HfO₂ dielectric. In addition, our results indicate that both self-heating and floating-body effects are important in the determination of backscattering coefficients. On one hand the floating-body effect may decrease channel backscattering in high drain bias regime, and on the other hand the self-heating effect may increase channel backscattering. We further demonstrate that the strain technology can improve the drain current variation through the enhanced ballistic efficiency. Moreover, the improvement shows Lg and Vds

dependence.Since β and r_sat can be physically determined by our developed program, the generalized self-consistent temperature-dependent method is competent to be routinely used in technology development for the process monitoring purpose.

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Fig. 4.1. Schematic diagram illustrating the backscattering theory [1]. Carrier in the critical length l is with a backscattering ratio rsat. The average injection velocity υinj is determined the equilibrium thermal velocity υ_therm and r_sat as υ_inj = υ_therm(1-r_sat)/(1+r_sat).

l

Source

Drain (1-r

sat

)

r

sat

1

Q

inv

,υ

inj

0.2 0.3 0.4 0.5 0.6 0.7 0.8

0 20 40 60 80 100

L

g

(nm)

B a ll is ti c E ff ic ie n c y

MSMC in [20]

Eq. (2) using VT,lin & set A Eq. (2) using V_{T,s at} & set A Eq. (2) using V_{T,s at} & set B

β_µ β_l γ

set A -1.5 1 0.5 set B (β_µ-β_l)=-2.2~-2.7 0.2

Fig. 4.2. Calculated ballistic efficiency B vs. L_g based on the results of [20] showing the need of accurate V_T,sat and (βµ-β_l).

Fig. 4.3. Measured I_d,sat and V_T,sat vs. T characteristics for the NMOSFET with L_g = 120 nm. Linear dependence of Id,sat and VT,sat on T is shown for T = 233 ~ 373 K. VT,sat is determined by maximum transconductance method with DIBL considered, i.e., V_T,sat = VT,lin-DIBL.

7 8 9

200 250 300 350 400

T (K)

I

d,sat

( 1 0

-4

A )

30 34 38 42 46

V

T,sat

( m V )

NMOSFET L_g=120nm

V_gs= V_ds = 1.5V

T V

_{T sat}

∂

∂

_,

T I

_{d sat}

∂

∂

_,

Fig. 4.4. Different estimations of -(∂V_T/∂T)/(V_gs-V_T). V_T,lin is extrapolated from the maximum transconductance. DIBL is the gate-voltage difference between gate voltages at Id = 100 nA/µm for Vds = 0.05 and 1.5 V.

Fig. 4.5. λ/l vs. T characteristics shows the need of self-consistent β for the backscattering coefficient extraction. In [7]-[15], β = -1.5 from β = 1+(βµ-β_l), βµ = -1.5 and βl = 1. Note that different values of I_d,sat and V_T,sat are considered in (4) at the corresponding temperature.

Fig. 4.6. Extracted β and βµ vs. V_gs characteristics for the NMOSFET with L_g = 120 nm.

βµ (–□–) is observed based on the effective mobility µ, which is extracted at different temperature by the split C–V method with R_sd correction.

-1.5 -1 -0.5 0

0.5 1 1.5

V

gs

(V)

ββββ &

ββββ

µ

self-consistent β

βββ

NMOSFET L_g=120nm β

β β

βµ obtained from the split C-V extracted mobility µ

-1.7 -1.5 -1.3 -1.1 -0.9

0 50 100 150 200 250

L

g

(nm)

β

self-consistent β

calculated from β = 1+(β_µ-β_l), β_µ=-1.5, β_l=1

NFET VGS-VT,s at=0.9V

Fig. 4.7. Extracted β vs. Lg characteristics for NMOSFETs at VGS-VT,sat = 0.9 V. The self-consistently extracted β shows significant L_g dependence.

Fig. 4.8. Extracted r_sat and the effective mobility µ vs. V_gs characteristics for the NMOSFET with Lg = 120 nm.

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.5 1 1.5

V

gs

(V)

r

sat

& n o rm a liz e d µ

r_{s at} extracted by self-consistent ββββ NMOSFET L_g=120nm

r_{s at} extracted by ββββ =-1.5

µ extracted by the split C-V method

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.5 1 1.5

V

gs

(V)

r

sat

∆γ=0

∆γ=0.1

∆γ=0.2

∆γ=0.3

∆γ=0.4

∆γ=0.5

NMOSFET Lg=120nm

Fig. 4.9. Extracted r_sat vs. V_gs characteristics for the NMOSFET with L_g = 120 nm with different ∆γ corrections.

Fig. 4.10. (a) Extracted β and (b) r_sat vs. (V_gs-V_T,sat) characteristics for 100-nm-L_g NMOSFETs with high and low body-doping N_a.

-1.4 -1.2 -1 -0.8 -0.6

0.2 0.5 0.8

V

gs

-V

T,sat

(V)

ββββ

Low N_a doping

(a) ^NMOSFET

L_g=100nm V_ds=1.1V

High N_a doping

0.3 0.5 0.7 0.9

0.2 0.5 0.8

V

gs

-V

T,sat

(V)

r

sat

High Na doping Low Na doping

self-consistent ββββ (b)

ββ

ββ = -1.5

Fig. 4.11. (a) Extracted β and (b) rsat vs. (Vgs-VT,sat) characteristics for 100-nm-Lg

NMOSFETs with HfO2 and SiO2 gate dielectrics.

-1.4 -1.2 -1 -0.8 -0.6

0.2 0.5 0.8

V

gs

-V

T,sat

(V)

ββββ

SiO2 dielectric

(a) ^NMOSFET

L_g=100nm V_ds=1.1V

HfO₂ dielectric

0.3 0.5 0.7 0.9

0.2 0.5 0.8

V

gs

-V

T,sat

(V)

r

sat

HfO2 dielectric SiO2 dielectric

self-consistent ββββ (b)

ββ

ββ = -1.5

Fig. 4.12. Measured drain-current vs. gate voltage characteristics for 50-nm-L_g PMOSFETs with and without uniaxially compressive strain at T = 233, 298, 373 K for (a) |Vds| = 0.05 V and (b) |Vds| = 1.3 V.

Fig. 4.13. (a) Extracted β and (b) r_sat vs. |V_gs-V_T,sat| characteristics for 50-nm-L_g PMOSFETs with and without uniaxially compressive strain [23][24]. The Rsd effect has been corrected. (R_sd ~ 125 Ω/um for the strained device and 214 Ω/um for the unstrained device).

1

characteristics at Vds = -20 ~ 20 mV. Effective mobility is extracted from the split C–V method at V_ds = 50 mV with R_sd correction [2].

0 0.5 1 1.5

l

T

-l

233K

(nm)

0.4V 0.5V 0.6V 0.7V 0.8V

Strained PFET L_g=50nm

|V_gs-V_{T,s at}| (b)

-35 -30 -25 -20 -15

0 0.2 0.4 0.6

l

T

-l

233K

(nm)

p o te n ti a l -k

B

T /q ( m V )

Strained

unStrained

l @ |V_gs-V_T,sat|=0.8V

backscattering source to drain flux (a)

Fig. 4.15. Extracted potential -kBT/q vs. (lT-l233K) characteristics for (a) strained and unstrained PMOSFETs with L_g = 50 nm at |V_gs-V_T,sat| = 0.8 V and |V_ds| = 1.3 V, and (b) the strained PMOSFET with Lg = 50 nm at |Vgs-VT,sat| = 0.4 ~ 0.8V and |Vds| = 1.3 V.

Fig. 4.16. Our self-consistent method considering accurate temperature dependence of carrier mobility and self-heating effects.

T

Fig. 4.17. Self-heating induced ∆T vs. ambient temperature T₀ for the SOI MOSFET with L_g = 63 nm. R_th (= 67064 K/W) is extracted by the method presented in [34].

20 30 40 50 60 70

200 250 300 350 400

Ambient T emperature, T

0

(K)

∆ T = R

th

x P o w e r (K )

SOI NMOSFET Lg=63nm Vgs=1.2V R_th=67064K/AV Vds = 1.2 ~ 0.6 V

Fig. 4.18. λ/l vs. T characteristics for (a) the constant β = -1.5 (i.e., βµ = -1.5 and βl = 1) and the self-consistent β, and (b) the self-consistent β with and without the correction of self-heating.

Fig. 4.19. rsat vs. Vgs characteristics for SOI NMOSFETs with Lg = 216 nm and 63 nm using the conventional method (i.e., assuming β = -1.5 in (10)).

0.2 0.3 0.4 0.5 0.6 0.7

0.7 0.8 0.9 1 1.1 1.2

V

gs

(V)

r

sat

conventional method

V

ds

(V) = 0.6 ~ 1.2 V DIBL = 89 ~ 150 mV

V

ds

(V) = 0.6 ~ 1.2 V DIBL = 50 ~ 71 mV

Lg = 216 nm

L_g = 63 nm

Fig. 4.20. rsat vs. Vgs characteristics for SOI NMOSFETs with Lg = 216 nm and 63 nm using the self-consistent method with and without self-heating corrections.

0.35 0.65 0.95

0.7 0.8 0.9 1 1.1 1.2

V

gs

(V)

r

sat

V

ds

(V) = 0.6 ~ 1.2 V DIBL = 89 ~ 150 mV

line: w/o heating corr.

dot: w/i heating corr.

L_g = 63 nm

0.35

0.65

V

ds

(V) = 0.6 ~ 1.2 V DIBL = 50 ~ 71 mV NEW self-consistent β method

L_g = 216 nm

Fig. 4.21. G_ds and the extracted β vs. V_ds characteristics for SOI NMOSFET with L_g =

Fig. 4.22. Comparison of σ(VT) and σ(VT)/VT for strained and unstrained PFETs.

Fig. 4.23. σ(I_d,sat)/I_d,sat vs. σ(µ₀)/µ₀ characteristics for strained and unstrained PFETs with Lg = 50 ~ 500 nm at Vds = 1.3 V.

0 1 2 3 4

0 1 2 3 4

σ(µ₀

)/µ

₀

(%)

σ (I

d,sat

)/ I

d,sat

( % )

unStrained Strained

PM OSFET s

|V

_gs

-V

_T

| = 0.8V

|V

_ds

| = 1.3V

L_g = 75~50nm

Suppression

Long channel

Short channel

Fig. 4.24. B_sat enhancement and µ enhancement vs. L_g characteristics for strained and unstrained PFETs. B_sat: ballistic efficiency B in saturation region.

|V_gs-V_T|=0.8V

|V_ds|=0.05V

B

sat,strained

-B

sat,unstrained

µ

0,strained

-µ

0,unstrained (a.u.)

|V_gs-V_T|=0.8V

|V_ds|=1.3V

0.07 0.08 0.09 0.1 0.11

0.2 0.5 0.8 1.1 1.4

|V

ds

| (V)

B

strained

-B

unstrained

PMOSFETs L_g=60nm

|V_gs-V_T|=0.8V

λ λ λ

λ

→ + + ←

B l

L

_g 2

Fig. 4.25. Vds dependence of the ballistic-efficiency enhancement. B is near λ/(2l+λ) for high Vds and λ/(Lg+λ) for low Vds.

Fig. 4.26. σ(Id)/Id vs. σ(µ0)/µ0 characteristics for strained and unstrained PFETs with Lg

= 50 ~ 500 nm at Vds = 0.3 V.

0 1 2 3 4

0 1 2 3 4

σ(µ0

)/µ

0

(%) σ (I

d

)/ I

d

( % )

unStrained Strained

PM OSFET s

|V

gs

-V

T

| = 0.8V

|V

ds

| = 0.3V

Chapter 5

Gate-Tunneling Current Induced Capacitance-Voltage Problems

5.1 Introduction

The gate capacitance-voltage (C–V) characteristic is fundamental to CMOS technology development because it plays an important role in oxide thickness extraction [21], carrier mobility calculation, interface trap characterization, and so on. As the gate dielectric thickness is reduced (below 20 Å), the inversion C–V characteristic is distorted due to direct tunneling current [1]-[9], [14]-[19]. Since the gate-tunneling current in metal oxide semiconductor (MOS) test structures may result in significant distributed channel resistance effect [5]-[9], several studies proposed conducting C–V measurements using short-channel devices [14]-[18]. Fig. 5.1(a) shows the observed inversion C–V characteristic with adequate calibrations for short-channel devices.

Although the inversion C–V characteristic is acceptable for gate bias (V_GS) smaller than 1 V, there still is significant C–V distortion for VGS > 1 V. One general way to solve this problem is to increase the C–V measurement frequency [14]-[18]. Based on the frequency dependent characteristics, parasitic component effects can be excluded and true C–V characteristics can then be calculated by a certain model of choice. For example, Pantisano et al. [15]proposed a C–V measurement from 1 kHz to 100 MHz and an extraction methodology using the three-element model [3]-[4], [22-23]. However, C–V measurements in the high frequency range require high frequency probes (Ground Signal Ground - GSG) and RF (radio frequency) test structures. Moreover, the

C–V reconstruction rather time consuming for regular product monitoring. Besides,

using these short-channel devices in C–V measurements has several drawbacks such as small intrinsic capacitance, large parasitic components and uncertainty in the physical gate length. In other words, the variation of measured capacitance increases as channel length decreases (Fig. 5.1(b)). Therefore, the reconstruction of C–V characteristics from long-channel devices is still a crucial issue.

Several studies have constructed the C–V characteristics for long-channel devices using distributed circuit approaches [5]-[9]. For example, Barlage et al. [7]proposed using a transmission line concept to extract the inversion MOS capacitance. In [5], we employed segmented SPICE simulation with each sub-transistor modeled by the BSIM4 MOSFET model to simulate the anomalous C–V curves due to gate tunneling. Although these methods may provide well-restored characteristics, the implementation is too complicated to be routinely used in a technology development. To develop a simple method for the inversion C–V reconstruction, the challenge lies in capturing the distributed nature of the gate capacitance and the channel resistance in a compact way.

This is analogous to the gate input impedance modeling in the compact model development for RF CMOS, where an intrinsic input resistance has been introduced [10]

as a major part of the gate input resistance. In this chapter, we investigate the inversion C–V reconstruction and assess the feasibility of the concept of intrinsic input resistance

for long-channel MOSFETs.

This chapter is organized as follows. In Section 5.2, devices and measurements in this work are presented. In Section 5.3, we describe BSIM4-based macro model using in this study, and identify mechanisms responsible for the inversion C–V attenuation in short-channel as well as long-channel devices. In Section 5.4, we investigate the validity of the concept of intrinsic input resistance. In Section 5.5, we assess the feasibility of

the intrinsic input resistance approach for the inversion C–V reconstruction. The conclusion will be drawn in Section 5.6.

5.2 Devices and measurements

Standard MOSFETs with doped poly-Si gate electrode were fabricated and tested in this study. The equivalent oxide thickness (EOT) is about 11 Å. The transistor gate length (Lg) ranges from 0.24 to 10 µm with 10-µm width (W). For the short-channel device with L_g = 0.24 µm, we employed a test structure with 15-array devices in parallel.

Our C–V measurement was carried out using the impedance analyzer Agilent 4294A and the Cascade Microtech probe system (S300 series) with DCP 100 probes. Under the RC parallel mode, the Hi port of Agilent 4294A was connected to source/drain, while the Lo port was connected to the gate electrode (SD-G case). The measurement principle of Agilent 4294A is the Four-Terminal Pair (4TP) configuration with Auto-Balancing-Bridge (ABB) method [13]. In the 4TP configuration, the outer shield of leads of Agilent 4294A needs to be connected together to provide a current return path to cancel the magnetic field generated by the inner current loop [13]. Besides, the whole system of the C–V measurement needs to be isolated from actual ground to exclude complicated coupling effects from the ground path and maintain stability of the C–V measurement.

Although the cable inductance, Ls, can be removed to a certain extent in the 4TP configuration [13], residual inductance may result in negative capacitance. Fig. 5.2(a) shows the measured inversion MOS capacitance, C_gc, with and without an adequate SHORT calibration. Without performing the SHORT calibration, Cgc dramatically drops as V_GS increases. By an adequate SHORT calibration, the residual L_s (~1 µH in series, Fig. 5.2(a) inset) can be compensated. In addition, Ls and stray capacitances may induce a resonance when the measurement frequency increases [13]. As shown in the Fig.

5.2(b), a resonance at ~30 MHz can be seen. The resonance leads to not only accuracy degradation but also very unstable measurement. To avoid the impact of the resonance, we performed C–V measurements in the frequency independent region (Fig. 5.2(b)). It is worth noting that the instrumentation error [19] and the impact of extrinsic capacitances and resistances [1]-[3] are frequency dependent. Therefore, measuring Cgc

in the frequency independent region may avoid these two mechanisms. In other words, the attenuation in C_gc measured in the frequency independent region with adequate calibrations (∆ in Fig. 5.2(a)) can be attributed to mechanisms of the intrinsic device part. After excluding the influences from the extrinsic components in the measurement setup, the Cgc data was then used in the following BSIM4-based extraction methodology.

5.3 BSIM4-based macro model and SPICE simulation

Figure 5.3(a) shows the BSIM4-based macro model we used in the simulation of Cgc. Segmented SPICE simulation that divides the transistor along the length direction with 10 sub-transistors in series was utilized and the BSIM4 device model parameters were calibrated through our extraction methodology (Fig. 5.3(b)). Our Cgc extraction methodology considers both DC and AC characteristics of devices. Basic device DC parameters such as threshold voltage (V_T), gate tunneling current (I_g), mobility (µ) and source/drain resistance (Rsd) need to be first determined and used in the AC analysis of SPICE. The oxide thickness, effective channel length, gate electrode resistance (Rge) and the parasitic inductance within the test structure itself (L_i) can then be extracted based on a comparison between the Cgc data and the simulation results. The true inversion MOS capacitance can be obtained by the gate-tunneling-free simulation. In the following sections, we discuss various mechanisms associated with the intrinsic device responsible for the anomalous C–V characteristics.

5.3.1 Short-channel device

Fig. 5.4(a) shows significant capacitance attenuation in the Cgc measurement for the device with Lg = 0.24 µm. The parasitic effects caused by Rge, Rsd and Li are responsible for the attenuation. Note that the impact of source/drain resistance, R_sd, and gate electrode resistance, Rge, increases as Lg decreases. In addition, the short-channel test structure is usually designed as a multi-array type to increase the impedance of the capacitor. As a result, the residual on-chip inductance, L_i, may become significant in the multi-array test structure when large current exists. By comparing the Cgc measurement data with the L_i-free simulation (Fig. 5.4(a)), it can be seen that the L_i effect is significant in the high gate bias (i.e., high gate tunneling) regime. Moreover, the Li-induced Cgc attenuation depends on the measurement configuration. As shown in Fig.

5.4(b), various measurement configuration may result in various C_gc attenuation due to different current direction. In other words, different C–V characteristics may be

5.4(b), various measurement configuration may result in various C_gc attenuation due to different current direction. In other words, different C–V characteristics may be

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