1. Introduction
1.3 Organization
In the rest of this dissertation, we focus on the design and implementation of the SSCG based on PLL. Three proposed SSCG are discussed.
In chapter 2, an extended input range ΔΣ modulator is developed and a fractional-N based SSCG utilizing the new ΔΣ modulator is designed and analyzed. Theoretical analysis for the input range of the new ΔΣ modulator is derived. Few simulations are made to compare the proposed SSCG and the conventional SSCG. Experimental results are coincided with the simulation results.
Chapter 3 focuses on the improvement of the SSCG using direct VCO modulation. A compact SSCG using a dual-path loop-filter combined another charge-pump can make the SSCG fully integration. The non-ideality of the dual-path loop-filter is analyzed. The phase noise of the SSCG is intensively studied. The modulation limitation and spurious modulation is also analyzed. Measurements show good agreement with the simulation results.
Chapter 4 presents a proposed SSCG with a two-point modulation. By mixing the analog modulation (VCO modulation) and the digital modulation (ΔΣ modulation), the proposed SSCG features good EMI performance and jitter performance by optimizing the loop bandwidth and the order of the ΔΣ modulator. The jitter and EMI from the quantization noise of the ΔΣ modulator and the VCO phase noise are deeply diagnosed. The simulation time is dramatically reduced by a well-built Matlab model. This model can analyze and predict the EMI performance and the jitter performance. The proposed DAC and other circuits are described. Measurements show good correspondence with the simulation results.
Chapter 5 develops another two-point SSCG for the application of SATA. The proposed DAC and the adopted dual-path loop filter are discussed. The linear model of the system including phase noise and jitter are presented. The major circuits are also discussed.
Measurements can meet SATA specifications and agree with the simulation results.
Finally, the conclusion of this thesis is given in Chapter 6.
CHAPTER 2
A Wide Input-Range ΔΣ Modulator for Applications to Spread-Spectrum Clock
Generator
A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (ΔΣ) modulator is presented. The proposed ΔΣ modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. A flexible digital modulation controller can generate center and down spread-spectrum modulation and each has spread ratios of 0.4%, 0.8%, 1.6% and 3.2%. The proposed SSCG has been fabricated in TSMC 0.35-um double-poly quadruple-metal CMOS process with output frequency of 300 MHz. The active area is 0.63×0.62 mm2 and the power consumption is 17.5 mW.
2.1 Introduction
Spread-spectrum clock generators have been widely used in the PC-based equipments as an effective method to reduce the high frequency emissions. Through the frequency modulation, the energy in each clock harmonic is spread evenly over a dedicated bandwidth, and thus, the power level at each clock harmonic is reduced as much as 10-20 dB, depending on the modulation index and the speed. Several techniques for spectrum spreading have been developed [2]-[9]. The fractional-N PLL with a ΔΣ modulator [8]-[9] has recently received much attention due to its advantages of being fully digital controlled and of being indirect modulated the sensitive VCO. The wider input range of the ΔΣ modulator is requested under the spread spectrum mode because the divider ratio changes all the time. An overflow problem may be encountered as the divider is set near the input boundary. Especially, in PC applications, a wide variety of divider numbers are often applied for different CPU
frequencies. For an example with the reference frequency (Fref) at 14.318 MHz and the output frequency at 300 MHz, the average value of the divider is 20.9526. Under a 3.2% deviation in center spread-spectrum mode, the variation of the fractional part is from 0.6173 to 1.2878, which crosses the unity boundary. However, the input range of the conventional ΔΣ modulator is limited under unity as its architecture is defined. Exceeding the input range will cause the stability problem and frequency error. In this study, the input range is enhanced to accommodate a wide variety of divider ratio. In Ref. [9], a method with a level shifter is used to shift the modulation profile to keep within the input range of the ∆Σ modulator. Therefore, some extra circuits are needed and make the modulator more complicated. Here, a simpler method with an extra bit added to the output of the first stage modulator is presented to extend the input range of ∆Σ modulator, solve saturation problem and thus, reduce the jitter introduced by the non-correct modulation.
2.2 Proposed Spread-Spectrum Clock Generator
The block diagram of the proposed spread-spectrum clock generator is shown in Fig. 2.1.
It is composed of a phase frequency detector (PFD), a charge pump circuit (CP), an off-chip loop filter (LF), a VCO, an asynchronous programmable counter (ASPC) and a digital modulation controller (DMC). The ΔΣ modulator of MASH type is employed due to the advantages of unconditional stability and easy high-order implementation. [11], [12]
2.2.1 Digital Modulation Controller
DMC which consists of a spread-spectrum profile generator and a ΔΣ modulator is used to control the divider value of ASPC. The profile generator as shown in Fig. 2.2(a) consists of a triangle wave generator and a profile controller to control the frequency deviation and spreading direction. The output of the controller denoted as INSD[k], where k is an integer, is fed to the ΔΣ modulator. The waveform of INSD[k] is shown in Fig. 2.2(b). The amplitude of the triangle wave, Vamp, controlled by SSPER is used to decide the frequency deviation ratio.
The mean value of the triangle wave, FNmean, controlled by SSTYP, is used to decide the center frequency of the SSCG. The maximal number of INSD[k], INSD[k]max, is given as
[ ]max mean amp
INSD k = FN +V . (2.1)
PFD LF
Fig. 2.1. Block diagram of the spread-spectrum clock generator.
SSTYP
Fig. 2.2. (a) Proposed spread-spectrum profile generator, and (b) The output waveform at INSD.
Fig. 2.3. Convectional third-order MASH 1-1-1 modulator (a) architecture and (b) input and output range.
Fig. 2.4. Proposed extended range MASH-type modulator (a) architecture and (b) input and output range.
The peak-to-peak frequency deviation ratio, Fdev,pp, is given as
where INTN is the integer part of the divider and BT is bit width of the modulator. In this design, there are two kinds of spread direction, i.e. center spread and down spread, and four peak-to-peak frequency deviation indexes: 0.4%, 0.8%, 1.6% and 3.2%. The frequency of the triangle wave is set at 40 kHz.
2.2.2 Modified ΔΣ Modulator
For clarity, the disadvantage of the conventional modulator as shown in Fig. 2.3(a) is indicated. Three first-order modulators are cascaded to implement a third-order MASH 1-1-1 modulator. The block diagram of each stage is shown in the right of Fig. 2.3(a), which is simply an accumulator with one-bit carry output. Both the input and output ranges are illustrated in Fig. 2.3(b). The exact input range is from1/2BT to(2BT −1)/2BT. It implies INSD[k]max is (2BT-1). Here BT=10. Each of the outputs of the three stages is 0 and 1. The output of the second stage passes through a differentiator and then its possible values become -1, 0 and 1. The output of the third stage passes through two differentiators and then its possible values become -2, -1, 0, 1 and 2. Summing the three branches together yields 8 possible outputs, i.e., -3, -2, -1, 0, 1, 2, 3 and 4. Therefore, the output range of the modulator is from -3 to +4 to accommodate all the possible inputs. So that 3bits at output are built. If INSD[k] is modulated beyond (2BT-1), then the modulator is saturated and can not function well. Therefore, such an arrangement can’t meet our requirement.
The proposed one with extended input range is shown in Fig. 2.4(a). Two different kinds of first-order ΔΣ modulator are employed. The block diagrams are shown in the bottom of Fig.
2.4(a). In stage-1 modulator, a 2-bit carry output denoted as C0[k] is designed. Stage2 and stage3 are unchanged. The inputs to the stage-1, stage-2, and stage-3 are denoted as INSD[k], EN1[k], and EN2[k], respectively. With the 2-bit carry output in stage-1 modulator, the input value INSD[k] can be set equal to or larger than one without error occurrence. As the input value is bigger than one, the stage-1 modulator can response quickly the integer part of the input to the output and will not saturate the following stages. The difference equation for
stage-1 modulator is given as follows. Let (2.5), the maximal number of C0[k] is equal to 3 and, thus, a two-bit carry output is needed.
From (2.4) and (2.5), the maximal number of SUM[k], SUM[k]max can be found as 2(BT+2)-1.
Substitute EN1[k]max and SUM[k]max into (2.3), INSD[k]max can be obtained as 3×2BT −1. The maximal input number of the proposed modulator is about 3 times compared to conventional modulator and hence extra two input bits are added. The output range of the proposed modulator becomes from -3 to 6. One extra bit is added. The input range and output range of the proposed modulator are shown in Fig. 2.4(b). The minimal input number of the proposed modulator is 1, which is the same to the conventional one.
From (2.1), one can get the following equation.
[ ]max 3 2mean amp BT 1
INSD k = FN +V = × − (2.6)
From (2.6) the advantages of the proposed modulator can be seen. When FNmean is equal to (2BT-1), which is the largest input number for the conventional modulator, the maximal number of Vamp is 0. Here, the maximal number of Vamp for the proposed architecture can be found as (2BT-2) by (2.6). When FNmean is equal to 1, which is the smallest input number for the conventional modulator, the maximal number of Vamp is 0. However, in proposed architecture, we can reduce the integer part of the divider by 1, and change the FNmean to
Fig. 2.5. The 300MHz output frequency simulation results for conventional (solid line) and proposed (broken line) architectures at the 3.2% center-spread spectrum mode.
(a) (b)
Fig. 2.6. The 300MHz output FFT simulation results of (a) conventional architecture and (b) proposed architecture at the 3.2% center-spread spectrum mode.
Delay#2 Delay#3
Fig. 2.7. (a) VCO with three-stage delay cells and (b) Schematic of each delay cell.
R1
Fig. 2.8. Charge-pump and loop filter circuit.
(2BT+1). Then the maximal number of Vamp is 2BT. The maximal frequency deviation appears when FNmean=Vamp, which is almost half of the input range. Therefore, one can efficiently use the the proposed modulator by simply shifting FNmean to FNmean +2BT.
The numerical comparisons of the output frequency between two architectures are illustrated in Fig. 2.5 and Fig. 2.6. The results are obtained from time-domain model built by MATLAB. The simulation case is a 300 MHz output with a 3.2% center-spread spectrum with the input frequency of 14.318 MHz. The fractional part of the modulator is changed between 0.6173 and 1.2878 and the mean value is 0.9526 as we mentioned above. Given BT=10, FNmean = 2BT×0.9526 = 975, and Vamp =2BT×(1.2878-0.6173)/2 = 343.
Fig. 2.5 shows the output frequency swing with respect to time for two architectures. It is shown that the solid line from the conventional modulator is clamped near 301 MHz, On the contrary, the curve by broken line can response well. Fig. 2.6(a) and 2.6(b) show the corresponding FFT results. The output spectrum in Fig. 2.6(a) for conventional modulator appears a peak near center frequency and a narrow peak-to-peak spreading ratio. However, the proposed one can correctly response the spreading profile.
The maximal frequency deviation can also be predicted. In above case, the maximal number of Vamp can be found as 974, which is equal to (FNmean-1). The INTN in this case is 20. From (2.2), the maximal peak-to-peak frequency deviation ratio can be found as 9.07%.
On the contrary, the conventional one only achieves 0.23% maximal peak-to-peak frequency deviation ratio. In summary, using this simple two carry-bits technique, the modulator can avoid the saturation region and enlarge the frequency deviation. Usually the spread spectrum ratio is less than 5% because of the jitter consideration. Therefore, the proposed SSCG can fulfill the requirement.
2.3 Circuit Description
The circuits in building blocks of Fig. 2.1 are briefly described. The wide band VCO which consists of the three stages of differential delay cells is shown in Fig. 2.7(a). The schematic of the cell is shown in Fig. 2.7(b). [10] The cross-coupled transistors, Mn1 and Mn2, give the VCO full swing and sharpen the edge of the output signal to reduce the jitter.
The transistors, Mn3 and Mn4, control the frequency of VCO. The voltage to current converter that will cause extra jitter is not needed because it is a voltage-controlled oscillator.
The tail current source is also avoided for low voltage application and for lower flicker noise up-conversion. [10] A 6-bit ASPC is adopted here for low power consumption. The charge-pump circuit and loop filter circuit are shown in Fig. 2.8. The cascoded current source is employed for good immunity against the power supper noise. The wide-swing bias circuit, which is not shown in the Fig. 2.8, is designed for low voltage operation. The controlling signals for UP and DN switches are fed from the output of PFD. The current of the charge pump is 6 uA and an external 3rd-order low-pass filter is used in this work to filter out the quantization noise of the modulator. The loop bandwidth of the PLL is traded off between modulation speed and modulator quantization noise. Here, the loop bandwidth of 150 kHz is chosen. The values of the components are listed in Table 2.1.
2.4 Measurement Results
The proposed SSCG has been fabricated in TSMC 0.35-μm double-poly quadruple-metal CMOS process. Fig. 2.9 shows the microphotograph of the chip. The active area is 0.63×0.62 mm2 and the total area including pads is 1.36×1.35 mm2. The tuning sensitivity of VCO is shown in Fig. 2.10 with a gain of 270 MHz/V near 300 MHz output.
The VCO reveals a good linear voltage to frequency transfer curve and has a maximal frequency more than 600 MHz. Fig. 2.11 indicates that the proposed SSCG operating at nonspread-spectrum mode achieves -104.31 dBc/Hz at 1 MHz offset from the carrier. It also reveals the closed-loop bandwidth of about 150 kHz. Fig. 2.12(a) shows the measured output spectrum at nonspread-spectrum mode. The amplitude is about 5.74 dBm. Fig. 2.12(b) shows the measured output spectrum under the 0.8% option in center spread-spectrum mode. The peak reduction is about 15.82 dB as compared to Fig. 2.12(a), which is very close to predicted results of 15.68 dB shown in Fig. 13. Fig. 2.12(c) shows the measured output spectrum under the 3.2% option in center spread-spectrum mode. The peak reduction is about 20.54 dB as compared to Fig. 2.12(a) that is slightly smaller than the predicted 21.36 dB in Fig. 2.14. This is because there exists small peaks at two ends of the measured spectrum. The phenomenon is due to the insufficient loop bandwidth. When the loop bandwidth is not
Fig. 2.9. Microphotograph of the proposed SSCG.
Kvco=270MHz/V @ 300MHz
100 150 200 250 300 350 400 450 500 550 600 650
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 Vcntl(V)
Frequency(MHz)
Fig. 2.10. Measured VCO frequency tuning curve.
Fig. 2.11. Phase noise measurement at non-spread spectrum mode.
(a)
(b)
(c)
Fig. 2.12. Measured spectrum (a) at non-spread spectrum mode, (b) at spread-spectrum mode with 0.8% center spread ratio, and (c) with 3.2% center
spread ratio.
Fig. 2.13. Comparison for FFT simulation results for spread-spectrum mode on with 0.8% center spread (o) and off (black).
Fig. 2.14. FFT simulation results for spread-spectrum on with 3.2% center spread (o) and off (black).
(a)
(b)
Fig. 2.15. Measured period jitter (a) at non-spread spectrum mode, and (b) with the center spread ratio of 0.8%.
enough to pass through high frequency components of the triangle signal, the modulation profile will be destroyed especially at the two ends. It is also founded in our simulation result of Fig. 2.6(b). The jitter performances at non-spread spectrum mode and spread-spectrum mode are shown in Fig. 2.15(a) and 2.15(b), respectively. The peak-to-peak jitter is 110 ps in non-spread spectrum mode and 140 ps under the 0.8% option. Table 2.1 gives the performance summary of the SSCG. Table 2.2 gives the comparison of EMI reduction between simulation and measurement.
2.5 Summary
In this work, an extended range MASH-type ΔΣ modulator is presented to solve the input range problems when the fractional-N PLL is operated as the SSCG. At the expanse of two extra input bits and one extra carry bit the proposed modulator is proven to have about 3 times input range as compared to conventional modulator. In the meantime the modulator can handle up to 9% frequency deviation. The spreading ratio and direction can be easily obtained by adjusting the amplitude and DC value of the digital triangle wave. The SSCG is implemented in TSMC 0.35 μm double-poly quadruple- metal CMOS process. Measurement results at 300 MHz under 0.8% and 3.2% spread ratio are in good agreements with the predictions. These results can be further applied to a wide variety of clock sources with spreading spectrum.
Table 2.1 Performance Summary
Modulation Method Modulation on divider Modulation Type Center-spread/Down-spread
Modulation Frequency 40 kHz
Spread Ratios(pp) 0.4%,0.8%,1.6%,3.2%
Output Frequency 300 MHz
Input Frequency 14.31818 MHz
VCO Gain(Kvco) 270 MHz/V
Loop bandwidth ~150 kHz
Loop filter R1=12 kΩ C1=400 pF C2=40 pF R3=10 kΩ C3=10 pF EMI reduction 15.82 dB @ 0.8% center spread ratio
20.54 dB @ 3.2% center spread ratio Jitter(PP) 110 ps at non-spread spectrum mode Jitter(PP) 140 ps at spread spectrum mode (0.8%)
Chip Area (active) 0.63×0.62 mm2
Power Dissipation 17.5 mW including output buffer @ 2.5V
Table 2.2 EMI reduction Between Simulation and Measurement Condition Simulation results Measurement results Center-spread 0.8% 15.68 dB 15.82 dB Center-spread 3.2% 21.36 dB 20.54 dB
CHAPTER 3
A Fully Integrated Spread Spectrum Clock Generator by Using Direct VCO Modulation
A compact architecture for a fully-integrated spread spectrum clock generator (SSCG) using VCO direct modulation is presented in this thesis. A dual-path loop filter in the phase-locked loop (PLL) is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third -charge pump which generates triangular waves is used to perform the function of a spread-spectrum.
The proposed circuit has been fabricated using a 0.35 μm CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5% and 2% are verified and are close to the theoretical analyses. The size of the chip area is 0.82×0.8 mm2 (including the loop filter) and the power consumption was 27.5 mW at 400 MHz.
3.1 Introduction
The electromagnetic interference (EMI) in electronic devices such as a PC, printer, PCI Express and SATA increases rapidly as the clock speed is raised. In many applications, clock generators are one of the major contributors of EMI. Spread-spectrum clock generators (SSCG) are proven to be an efficient way to reduce EMI levels [2]-[4], [7]-[9], [13]-[15]. A SSCG is basically a PLL with an appropriate frequency-modulated output. The frequency modulation is used to spread the output spectrum. There are three kinds of modulation schemes employed in PLLs. The first type involves a change to the divider made by a sigma-delta modulator [8]-[9]. The second type includes either digital manipulation of the output of a multiphase PLL or the use of a DLL/phase interpolator combo on the output of a standard PLL [5]-[7]. The last type involves direct modulation of the VCO in PLL [3]-[4], [16]-[17]. The latter has the advantages of a simple circuit structure and the absence of sigma-delta modulator noise. But the loop bandwidth of a PLL has to be much less than the modulation frequency to allow the frequency variation of the VCO. In general, the required loop bandwidth is about one of ten times that in the modulation. The modulation frequency is
Fig. 3.1. Proposed SSCG.
Fig. 3.2. (a) Dual-path loop filter (b) Traditional loop filter.
typically around 30 kHz to 50 kHz so that the loop bandwidth is around 3 kHz to 5 kHz. This leads to a large capacitor of more than 10nF in the loop filter, which becomes too large to be integrated in the chip [3].
Recently, the technique of capacitance multiplication is proposed to eradiate this problem [16], [18]-[20]. However, in order to accommodate another charge pump to generate the triangular modulation, a floating capacitor is connected [16]. The floating capacitor in a standard CMOS process can be PIP (poly to poly) or MIM (metal to metal) and needs extra masks and process steps. It also has the area and cost penalties comparable to those of a MOS
Recently, the technique of capacitance multiplication is proposed to eradiate this problem [16], [18]-[20]. However, in order to accommodate another charge pump to generate the triangular modulation, a floating capacitor is connected [16]. The floating capacitor in a standard CMOS process can be PIP (poly to poly) or MIM (metal to metal) and needs extra masks and process steps. It also has the area and cost penalties comparable to those of a MOS