Analysis of Noise Power Spectral Density from the ΔΣ Modulator

max _err M^ramp ω K

Δ ∝ . (5.10)

Equation (5.9) and (5.10) indicate how the low pass behavior causes frequency errors and distorts the output. It is clear that Δωerr=0 only if K=∞, i.e., the loop bandwidth is infinitely large.

With two point modulation activated, by the superposition principle, the closed loop transfer function of Fig. 5.4 can be derived as:

( ) (

( ) )

The first term in the right hand side is the same as (5.4). The second term appears as a high pass and can be treated as a complementary part if Gm=1. Therefore, from (5.11), Δωout

is equal to Δωsig if Gm=1. This means that the output is all pass without distortion and bandwidth limitation. The frequency errors for both one-point modulation and the proposed scheme, with a frequency ramp input, are shown in Fig. 5.5. Here, Gm=1. The other parameters are listed in Table 5.1. The solid line is the ideal all pass, the dashed line is from (5.4), the dashed-doted line is from the second term in (5.11), and the line with a circle mark are the output from (5.11). The dashed line cannot track the input frequency change well due to insufficient loop bandwidth. On the contrary, the line with circle mark can always track the input so that the output error is eliminated. Thus, the proposed scheme can track the modulation waveform very well and is independent of the PLL loop bandwidth as long as the paths are matched.

5.2.4 Analysis of Noise Power Spectral Density from the ΔΣ Modulator The power spectral density is closely related to the order of the ΔΣ modulator and the loop bandwidth. It is already known that a high order ΔΣ modulator is used to reduce the fractional spur within the loop bandwidth. In this design, only a second order ΔΣ modulator is chosen to save area and power, while maintaining jitter and EMI performance. To see the

interrelation between the order of the ΔΣ modulator and the PLL loop bandwidth, the output phase noise originated from the ΔΣ modulator and the VCO are investigated. The noise power spectral densities (PSD) of the phase SΦ(f) can be expressed as

( ) ( )

( ) _VCO

S_Φ f =S_Φ f +S_ΦΔΣ f , (5.13)

where SΦvco(f) and SΦΔΣ(f) are the noise of the VCO and the ΔΣ modulator, respectively. SΦΔΣ(f)

[11] can be found as

where m is the order of the modulator, and fbk is the operational frequency of the modulator.

SΦvco(f) can be easily derived as

2

( ) 1 ( ) 2

VCO vn s j f

S_Φ f =S_Φ ⋅ −T s _{= π} , (5.15)\

where SΦvn is the stand alone VCO phase noise.

In general, the loop bandwidth is much less than the phase comparison frequency fbk at the phase detector to avoid the spur. From (5.14), it is realized that the shape of output PSD, caused by the ΔΣ modulator, is increasing inside of the PLL loop bandwidth with f^2(m−1) and decreasing outside of the PLL loop bandwidth. In other words, the smaller the PLL loop bandwidth, the lower the jitter caused by the ΔΣ modulator. However, a large PLL loop bandwidth is needed to pass faithfully the modulation profile. Otherwise, the spectrum appeared at the output of PLL will be distorted, the spread ratio will be incorrect and EMI performance will be degraded. Thus, the PLL loop bandwidth is a trade-off between the modulation profile and the jitter performance. In the conventional situation [36], the bandwidth is approximately ten times the modulation frequency to obtain modulation performance. The in-band fractional spur are suppressed by a third-order ΔΣ modulator to minimize the phase noise and jitter. In addition, a third-order loop filter is needed to reduce the out-of-band phase noise and jitter caused by the comparison clock. In other words, it requires higher power consumption and more area. However, thanks to the all pass nature in

profile distortion.

The PSDs for the conventional fractional-N SSCG (FN-SSCG) and the two-point SSCG (TPDL-SSCG) in non-spread spectrum mode are illustrated in Fig. 5.6. Only the VCO and the modulator quantization noise are taken into account. The VCO phase noise is assumed as -89 dBc/Hz at the offset frequency of 1 MHz with the shape of f^-2. Other simulation parameters are listed in Table 5.1. Two different cases with loop bandwidths of 100 kHz and 300 kHz are studied. A third pole of 4.5 MHz is needed for the FN-SSCG to further filter the quantization noise of the third-order modulator. The center frequency is set at 1500 MHz, the spread ratio is -0.5%, and the modulation frequency is set at 31.25 kHz. The solid and dashed lines represent the total phase noise for the FN-SSCG with a 300 kHz loop bandwidth and TPDL-SSCG with a 100 kHz loop bandwidth, respectively. The contributions from the VCO are denoted by circle and plus marks in different cases. The phase noise from the ΔΣ modulator is denoted by diamond and square marks. Although the in-band phase noise in the proposed TPDL-SSCG with a second order ΔΣ modulator is larger than the case in the FN-SSCG with a third order ΔΣ modulator, the TPDL-SSCG still has enough performance in terms of EMI suppression, modulation profile linearity, and jitter through the following analysis and measurements.

The chip areas for the second-order, and third-order, MASH ΔΣ modulator are evaluated as 3920 and 4887, in units of gate-counts, respectively. The power consumption using the TSMC 0.18 μm process is 1.40 mW and 2.00 mW, respectively. The area is approximately 20% off in digital area and approximately 5% off in whole area, and the power is approximately 4% off in whole power consumption when using the second-order ΔΣ modulator. The 4 to 5% difference is still important because the power and area of the proposed SSCG is only 15.3 mW and 0.21 mm², respectively. Hence, in this work, a second-order ΔΣ modulator and a 100 kHz loop bandwidth, with a second-order loop filter, are designed for saving power and area.

Table 5.1 SSCG Simulation Parameters

FN-SSCG TPDL-SSCG

Input Frequency 25 MHz 25 MHz Output Frequency 1500 MHz 1500 MHz

Spread Ratio -0.5%-0 -0.5%-0

VCO Gain 480 MHz/V 480 MHz/V

Loop Bandwidth 100/300 kHz 100/300 kHz

Modulator third-order MASH second-order MASH Loop filter third-order second-order

Third pole frequency 4MHz N/A

Fig. 5.7. Simulation results for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.

Fig. 5.8 .Spectrum simulation results with the ΔΣ modulator noise for the FN-SSCG and the PDL-SSCG under different loop bandwidths.

Fig. 5.9. Spectrum simulation results without the ΔΣ modulator noise for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.

5.2.5 Simulation Results

To compare the performance between the FN-SSCG and the TPDL-SSCG, the following simulations are made. The same parameters listed in Table 5.1 are used. The output frequency swings are shown in Fig. 5.7. Four different spread ratios of 0.543%, 0.523%, 0.506%, and 0.510% for the FN-SSCG with a 100 kHz BW denoted curve-a, the FN-SSCG with a 300 kHz denoted curve-b, the TPDL-SSCG with a 100 kHz BW denoted curve-c, and the TPDL-SSCG with a 300 kHz BW denoted curve-d are obtained, respectively. The corresponding spectra results with the ΔΣ modulator noise are shown in Fig. 5.8. The simulated spectra with ΔΣ modulator noise are 20.35 dB, 19.69 dB, 20.47 dB, and 19.21 dB for curve-a, curve-b, curve-c, and curve-d shown in Fig. 5.7, respectively. The simulation results are summarized in Table 5.2. It is known that the larger the spread ratio, the better the EMI performance. To see the efficiency of EMI performance, the EMI reduction and its spread ratio need to be considered simultaneously. Therefore, the ratio of EMI in dB to spread ratios in percentage denoted by EMInorm is also evaluated. The case of the FN-SSCG with a 100 kHz BW has the largest peak-to-peak spread ratio (0.545%) deviation from the ideal value 0.5%, and the smallest EMI efficiency with the value of 37.34 dB/% because the PLL loop bandwidth is not enough that the output could not track the modulation profile and is distorted. Small peaks existed at two ends of the spectrum for the case of the FN-SSCG with a 100 kHz BW, meaning that it is not a good triangular waveform. The case of the FN-SSCG with a 300 kHz BW has better performance in terms of the spread ratio (0.523%) and EMI efficiency (37.65 dB/%) compared to one with a 100 kHz BW. However, it is clearly indicated that the case of the TPDL-SSCG with a 100 kHz BW has not only a more accurate spread ratio (0.506%), but also better EMI efficiency (40.45 dB/%) with respect to the two cases of the FN-SSCG because the case of the TPDL-SSCG with a 100 kHz BW has smaller ΔΣ modulator noise than the case of the FN-SSCG with a 300 kHz BW and utilizes the technique of the two point modulation to faithfully pass the modulation profile. This is also indicated from the spectrum shape that no obvious peaks appeared at the two ends of the spectrum. In addition, there is a 0.023% difference in spread ratios for PLL loop bandwidths changed from 100 kHz to 300 kHz for the FN-SSCG, while there is only 0.003% difference in spread ratios for the TPDL-SSCG. The slight difference between curve (c) and (d) in Fig. 5.7

Table 5.2 SSCG Simulation Summary

With ΔΣ noise Without ΔΣ noise

Spread ratio EMI EMInorm EMI

FN-SSCG (100KHz) 0.545 20.35 37.34 20.32 FN-SSCG (300KHz) 0.523 19.69 37.65 20.95 TPDL-SSCG (100KHz) 0.506 20.47 40.45 20.76 TPDL-SSCG (300KHz) 0.510 19.21 37.67 20.70

UNIT %-pp dB dB/% dB

Fig. 5.10. Simulation results for gain mismatch impact on spread ratio for the TPDL-SSCG.

is due to the quantization noise influence. It implies that the effect of bandwidth is of little importance in the proposed modulation.

More effects are illustrated in Fig. 5.7 and 5.8, which show that the bigger loop bandwidth and worse jitter both appeared at the output. The cases with a 300 kHz BW show the bigger instantaneous frequency fluctuations from Fig. 5.7, and the higher noise level from Fig. 5.8, with respect to the cases with a 100 kHz BW in both architectures. This confirms the results in (5.14). The proposed TPDL-SSCG has the advantage of low distortion, so that the modulation profile is more like a triangular wave, and can improve the linearity of the modulation profile and the EMI performance at the same time.

In order to deeply investigate the jitter effect on the EMI suppression level, the spectra simulation without the ΔΣ modulator noise for FN-SSCG and TPDL-SSCG under the same case as in Fig. 5.7 and Fig. 5.8 are drawn in Fig. 5.9. The simulation results are also summarized in Table 5.2. The simulated spectra without the ΔΣ modulator noise are 20.32 dB, 20.95 dB, 20.76 dB, and 20.70 dB for the FN-SSCG with a 100 kHz BW, the FN-SSCG with a 300 kHz BW, the TPDL-SSCG with a 100 kHz BW, and the TPDL-SSCG with a 300 kHz BW, respectively. It shows a 1.26 dB (=20.95-19.69) EMI degradation for the case of FN-SSCG with a 300 kHz BW when the ΔΣ modulator noise is taken into consideration;

while it is 1.49 dB (=20.70-19.21) for the case of TPDL-SSCG with a 300 kHz BW. It is clearly to seen that there is only 0.29 dB (=20.76-20.47) impact on EMI performance for the case of TPDL-SSCG with a 100 kHz BW. Therefore, the random jitter introduced by the modulator has a deteriorating effect on EMI suppression levels.

The impacts of the gain mismatch on spread ratios and the EMI performance are verified.

The cases for Gm=0.6, Gm=1.0 and Gm=1.4 are simulated under different PLL loop bandwidths. The impacts on spread ratios are shown in Fig. 5.10(a). When the PLL loop bandwidth is smaller than 100 kHz, the spread ratio is very sensitive to the gain mismatch between the two points. When the PLL loop bandwidth is larger than 100 kHz, the spread ratio variation is small. The impacts on the EMI performance are shown in Fig. 5.10(b).

When Gm =1.0 or Gm=1.4, the higher the PLL loop bandwidth has, the worse the EMI performance is. When Gm=0.6, the EMI performance is less related to the PLL loop bandwidth. In addition, the EMI variation is sensitive to the gain mismatch when the PLL

proposed SSCG is described below. One can rewrite (5.11) as

The first term in (5.16) is contributed by the modulation of divider and the second term is contributed by the modulation of the VCO. When the loop bandwidth is quite low, the output is dominated by the second term in (5.16), meaning that the spread ratio is sensitive to gain mismatch. In other words, when the loop bandwidth is quite high, the output is dominated by the first term in (5.16), meaning that the spread ratio is less sensitive to gain mismatch. But, it is noted from the above analysis that the EMI performance will be degraded once the loop width is large due to the quantization noise of the modulator. Therefore, if the gain mismatch is small, one can lower the bandwidth to achieve the desired performance according to the above analysis. If the gain mismatch is high as, or more than 0.4, one needs to tradeoff the loop bandwidth with the performance. Thus, in order to reduce the effect of gain mismatch, one can choose an appropriate loop bandwidth to let the first and the third Fourier frequencies of the triangular waveform to be passed through the divider path and to let the fifth and higher Fourier frequencies to be passed through the VCO path. This approach makes the output waveform dominated by the divider modulation path and aided by the VCO modulation path. A rule of thumb of 3 times of the modulation frequency can be the target loop bandwidth. Thus, the 100 kHz loop bandwidth is adopted in this work.

From (5.2), since C1 is varied within 5% and Ip3 is varied within 15% in the typical CMOS process, the gain mismatch is mainly contributed by Kvco. Therefore, the VCO with low sensitivity to VCO gain is needed. In this work, Kvco is varied about +/-30% over process, voltage, and temperature variation. It means Gm is changed about from 0.7 to 1.3. From the above simulation results, the gain mismatch impact on spread ratio with will be varied about 0.008% and the gain mismatch impact on EMI performance is about 0.23 dB. Moreover, the VCO calibration technique in [24] can be used to further improve the performance.

In short, the advantages of the proposed TPDL-SSCG are remarkable. First, a lower order ΔΣ modulator can be used for lower power consumption. Second, the lower order loop filter can be used for a smaller chip area. Third, the linear modulation profile, and small ΔΣ modulator noise can be optimized simultaneously.

Fig. 5.11. Block diagram of the proposed profile generator and ΔΣ modulator.

5.3 Circuit Descriptions

The block diagram of the proposed profile generator and ΔΣ modulator is shown in Fig.

5.11. The input range of the ΔΣ modulator must fulfill the requirement of 0 to -5000 ppm spread ratio. Accordingly, the fractional number is varied between 0.925 and 1. A MASH type ΔΣ modulator has an input range of less than 1 and cannot be used in this application. To eradicate this issue, a new version of the MASH-1-1 ΔΣ modulator, with extended input range, is used to overcome the overflow problem in the modulator [23]. Stage 1 has two carry bits while stage 2 only has one carry bit. The two-bit carry outputs cause inputs larger than, or equal to, 1 to quickly pass the integer part of the input to the output, and will not saturate the following stages. The advantages of this design are unconditional stability, and small area similar to the conventional MASH-1-1 ΔΣ modulator. In addition, this circuit has approximately 3 times the input range of the conventional MASH-1-1 ΔΣ modulator.

The profile generator consists of an up/down counter and a first-order ΔΣ modulator [39].

Although the clock input shown is fbk, the actual operating frequency of the up/down counter is fcnt, which is determined from the spread ratio of δ, the modulation frequency of fsig, and the bit number of the MASH-1-1 ΔΣ modulator (B) as described by

2 2

Therefore, an extra first-order ΔΣ modulator is added to generate the additional enable signal, fen to lower the operation frequency of the up/down counter, as shown in Fig. 5.11.

The relationship between fcnt and fen is fcnt=fen AND fbk. In this study, fout is 1.5 GHz, fsig is 31.25 kHz, and δ is 0.5% to meet SATA specifications. In addition, B=12 and fbk=25 MHz.

One can calculate that fcnt=19.2 MHz.

Fig. 5.12 shows the schematic of VCO used in this work [41]-[42]. It is composed of four current starved inverters (denoted by X) as delay cells, two pairs of cross-coupled current starved inverters (denoted by Y), and a voltage to current converter (V2I). The detailed circuit of the V2I is shown in Fig. 5.12(b), and the inverters of X and Y are shown in Fig. 5.12(c). This simple architecture is selected for its large signal swing, which allows better phase noise performance and large tuning range. The cross-coupled inverters have two

Fig. 5.13. Die photograph of the proposed TPDL-SSCG.

(a)

(b)

(c)

Fig. 5.14. Measured spectra (a) at non-spread spectrum mode, (b) of the conventional FN-SSCG, and (c) of the proposed TPDL-SSCG.

Measurement condition: RBW= 100 kHz, VBW= 100 kHz and Peak-Hold mode.

(a)

(b)

Fig. 5.15. Measured spectra for the TPDL-SSCG (a) with SSC-off (b) with SSC-on Measurement condition: RBW=10 kHz, VBW= 10 kHz and Peak-Hold mode.

Fig. 5.16. Measured modulation profile in time domain.

(a)

(b)

Fig. 5.17. Measured jitter for the TPDL-SSCG (a) with SSC-off, (b) with SSC-on.

functions: One is to provide negative impedance to mandate the phase delay in each inverter at 90 degrees, and the other is to allow the VCO to operate pseudo-differentially to obtain better PSRR. In other words, the VCO is a two-stage differential type. The size of inverter Y is suggested to be more than 0.5 times of size of inverter X to maintain oscillation [41]. Here, the factor is 0.7 times to allow a higher oscillation frequency than that of the 3-stage single-ended ring oscillator [41] because it has an additional coupling path from the cross coupled inverters with reduced delay time. Therefore, the power consumption can be relaxed for a given frequency. Moreover, unlike a singled-ended ring oscillator, which produces a distorted triangular waveform output, this topology produces a sinusoidal output, and a more symmetrical waveform, to get better phase noise performance [43]. To further minimize the phase noise, a low VCO gain of 480 MHz/V is chosen to lower the phase noise due to the noise coupling to the VCO input node. The noise of the V2I is also a main contributor to the phase noise. Therefore, the size of the V2I is the same as that in inverter X to lower the up-conversion noise from the bias circuit. The measured phase noise at 1 MHz offset frequency is -89 dBc with a power consumption of 3 mA.

5.4 Measurement Results

The proposed SSCG is designed and fabricated by TSMC 0.18 μm CMOS process. The die photograph is shown in Fig. 5.13. The active area is 0.42×0.48 mm². The output spectra without spreading, with spreading, using the conventional FN-SSCG, and with spreading using the TPDL-SSCG are shown in Fig. 5.14(a), (b), and (c), respectively. The resolution bandwidth (RBW) is set to 100 kHz to meet SATA specifications [35]. A second-order loop filter and a PLL bandwidth close to 100 kHz are chosen for both Fig. 5.14(b) and (c). The second-order extended range MASH ΔΣ modulator is adopted for both Fig. 5.14(b) and (c).

In other words, the conventional FN-SSCG is obtained just by switching off the path of the VCO modulation. The EMI reduction is approximately 7.52 dB for the conventional FN-SSCG and is approximately 10.14 dB for the TPDL-SSCG. The proposed SSCG has 2.62

RBW needs to be smaller than the modulation frequency [40]. Therefore, the spectra for the TPDL-SSCG, with SSC off and on using 10 kHz RBW, are measured and shown in Fig.

RBW needs to be smaller than the modulation frequency [40]. Therefore, the spectra for the TPDL-SSCG, with SSC off and on using 10 kHz RBW, are measured and shown in Fig.