Measurement - A High Performance Spread Spectrum Clock Generator Using

4. A High Performance Spread Spectrum Clock Generator Using

4.4 Measurement

The chip is designed and fabricated using TSMC 0.35 μm single-poly quadruple-metal CMOS process. The die photograph is shown in Fig. 4.15 and has an area equal to 0.90×0.89 mm². The output spectrum at 400 MHz without spreading is shown in Fig. 4.16(a). The magnitude of the peak is 3.30 dBm. The spectra for one and two-point modulations under a

2.5% spread ratio are shown in Fig. 4.16(b) and (c) with magnitudes of -16.06 dBm and -16.61 dBm, respectively. The loop bandwidth is 120 kHz for both modulations. Fig. 4.16(b) is obtained by switching off the VCO modulation. The reductions in peaks are approximately 19.36 dB and 19.91 dB for Fig. 4.16(b) and (c), respectively. Two small peaks which are due to an insufficient loop bandwidth are still visible at the edges in Fig. 4.16(b).With reference to Fig. 4.16(c), the EMI improved to 0.55 dB under the same loop bandwidth. The measured rms jitter is 14.27 ps under the non-spread spectrum mode as in Fig. 4.17(a) and reaches 24.86 ps under the 2.5% spread ratio as in Fig. 4.17(b).The rms jitter is increased to 10.59 ps, which is very close to the theoretical estimation of 10.42 ps (=2.5%×2500 ps/6). It has also been assumed that the total jitter is six times that of the rms jitter. Table 4.3 provides a summary of performance. The total power consumption is 33 mW and includes an output buffer.

4.5 Summary

In this study, a low jitter SSCG with a two-point modulation scheme has been presented. This technique permits an all-pass feature, even when a finite loop bandwidth is involved. This technique offers two advantages; first, an almost distortion-free response involving triangular modulation, which provides a 0.55 dB improvement in EMI suppression when compared with a conventional scheme. Second, a small loop bandwidth also offers the possibility of choosing a second order sigma-delta modulator without the disadvantage of quantization noise. Furthermore, both chip area and power consumption have been reduced. An attractive DAC structure has been proposed to accommodate the two-path loop filter and sensitive VCO modulation. The proposed technique provides total integration and suppresses the digital spur associated with highly sensitive VCO input. The effects of the VCO phase noise and the

quantization noise of the modulator are clearly verified. The VCO phase noise shows minor impact on the EMI performance; while the quantization noise has big degradation on the EMI performance.

Table 4.3 Performance Summary Modulation Method Two point

Modulation Type Center-spread Modulation Frequency 40 kHz Spread Ratios(pp) 1.25%, 2.5%

Output Frequency 400 MHz

VCO Gain 200 MHz/V

Input Frequency 14.31818 MHz Loop bandwidth ~120 kHz

Loop filter R1=12 kΩ C1=400 pF C2=40 pF Charge Pump Current Ip1=9 uA

EMI reduction 19.91 dB @ 2.5% center spread ratio

Jitter 14.27 ps rms at SSC-off

24.86 ps rms at SSC-on Chip Area (active) 0.90×0.89 mm²

Power Dissipation 33 mW including output buffer @ 3.0V

CHAPTER 5 A Low Power and High Precision Spread Spectrum Clock Generator for SATA Applications Using Two Point Modulation

A new technique utilizing two-point modulation (TP) for a spread-spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a ΔΣ modulator, and the voltage-controlled oscillator is modulated.

With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the ΔΣ modulator can be improved at the same time. The order of the ΔΣ modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop-filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18 μm complementary metal oxide semiconductor process. The size of chip area is 0.44×0.48 mm². The circuit produces a clock of 1.5 GHz with a down spread ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.

5.1 Introduction

Serial interfaces are widely used for high data rate transmission. For example, serial advanced technology attachment (SATA), which is the standard for high-speed storage devices such as hard disc drives and compact disc (CD)/digital versatile disc (DVD), can transmit data at rates up to 1.5 Gbps or 3 Gbps for generation I and II, respectively [35].

High-speed clocks often cause electromagnetic interference (EMI). Therefore, the spread-spectrum clock generators (SSCG) are employed in SATA to reduce EMI levels.

Typical specifications in SATA are the 5000 ppm down-spread ratio, modulation frequency within 30-33 kHz, and EMI suppression of at least 7 dB. In order to realize such a fine spread ratio, fractional-N phase-locked loops (PLLs) with a ΔΣ modulator are usually used [9], [13], [22]-[24]. This technique has the advantages of fully digital control and fine resolution. The modulator is normally driven by a triangular waveform. A non-linear profile, known as the

‘Hershey-Kiss’ profile, has been suggested for better EMI performance [2]. The nonlinear function of the ‘Hershey-Kiss’ profile makes it more expensive due to large area and power consumption. Therefore, triangular waveforms are still used due to their simple implementation [9], [15], [36]. Another important issue is the choice of loop bandwidth of PLL. The loop bandwidth has trade-offs between the modulation profile and the jitter caused by ΔΣ modulator. The profile is distorted and the effect of EMI suppression is degraded if the loop bandwidth is not wide enough. Therefore, the wide bandwidth leads to a request for a third order ΔΣ modulator in order to suppress the in-band fractional spurious. A design of a third order ΔΣ modulator with a third order loop filter and a 300 kHz loop bandwidth to improve the jitter and the modulation profile was presented in [36]. However, the third order ΔΣ modulator has high power consumption and occupies a large area. Recently, the method of two-point (TP) modulation, which has the divider and the voltage-controlled oscillator (VCO) modulated at the same time, was presented to enhance the bandwidth and improve EMI performance [25]-[26]. Here, a new version of SSCG with two-point modulation is presented for the SATA application [38]. The jitter caused by the ΔΣ modulator can be reduced by a small loop bandwidth, while the modulation profile can still be maintained.

Only a second order ΔΣ modulator, as well as a second order loop filter, is adopted. The chip area and power consumption are improved. In addition, aided with a dual-path loop filter (DL), the proposed TPDL-SSCG can be fully integrated.

5.2 Proposed TPDL-SSCG

It is well known that the transfer function of the phase response from the feedback divider to VCO output is a low pass function. On the contrary, the function from VCO input

Fig. 5.1. The block diagram of the proposed TPDL-SSCG

CP3

Fbk Fsig

Digital slicer

Fsig1 C2

R1 Vc

(a)

(b)

Fig. 5.2. (a) Proposed DAC. (b)Timing diagram for the proposed DAC.

to VCO output is a high pass function. A wideband response can be achieved if the loop is excited through these two points. The block diagram of the proposed SSCG is shown in Fig.

5.1 with a phase frequency detector (PFD), a dual path loop filter containing CP1, CP2, R1, C1, and C2, a VCO, a prescaler, a 5-bit programmable counter (PGC), a digital ΔΣ modulator, a modulation profile generator, and a DAC. Compared to the conventional one, this circuit incorporates two extra circuits of charge pump CP2 and DAC. The staircase triangular waveform is digitally generated by the profile generator. The frequency modulation is obtained from two inputs Vx and Vy. Vx is the input of the multi-modulus divider and Vy is the input of the VCO. The all pass behavior is obtained as long as the modulation coefficients along the two paths are matched.

5.2.1 The Proposed DAC

The function of the DAC is redrawn in Fig. 5.2(a). It consists of a digital slicer, charge pump CP3, and capacitance C1. An analog triangular waveform across C1 is obtained from a digital triangular waveform, fsig. The digital triangular waveform is first sliced into a square waveform, fsig1, and then charges the capacitor C1 to achieve digital-to-analog conversion.

The digital transition is smoothed out to reduce VCO interference. As compared to a traditional one, no high resolution DAC or reconstruction filter is needed [29]. Therefore, the power consumption and the chip area can be reduced.

The delay mismatch is known to degrade the performance [29]. The following approach is utilized to eliminate this non-ideality. Referring to the timing diagram in Fig. 5.2(b), fsig1

and Vy are two clocks delayed with respect to fsig in order to synchronize the delay from fsig to the output of the ΔΣ modulator, Vx. Because the digital slicer, the profile generator, and the ΔΣ modulator use the same clock, fbk, which is the output frequency of the PGC, the delay mismatch can be avoided.

The relation between controlled voltage Vc and the current Ip3 of CP3 can be written as

( )

to high output impedances. Accordingly, the smooth triangular waveform is obtained, as Ip3 is a square waveform. Here, both C1 and C2 with one terminal grounded are implemented by

Fig. 5.3. Simplified block diagram of the dual path loop filter.

Fig. 5.4. Linear model of the proposed TPDL-SSCG.

the accumulation MOS capacitor to save area. Both have good distortion performance when

where fout is the nominal VCO output frequency, fsig is the modulation frequency of the triangle wave, and Kvco is the conversion gain of VCO.

5.2.2 Dual-Path Loop Filter

To save the capacitor area in the loop filter, a modified dual-path loop filter is utilized [37]. The paths of pumping currents are shown in Fig. 5.3, in which Ip1 is the current of CP1, and Ip2 is the current of CP2. Ip2=K1Ip1. The loading effect of CP3 is neglected. The loop filter transfer function can be derived as

( ) ( ( ) )

other. However, the mismatch between Ip1 and Ip2 depends on the area. Therefore, a trade-off should be made. Here K1=0.75 and K2=4 such that the size of capacitance C1 can be reduced by four times. Compared to the dual path filter in [18], the dual path filter adopted here doesn’t need a unity-gain amplifier; therefore the phase noise is smaller.

5.2.3 Linear Model Analysis

Rather than finding out the phase relationship, here the frequency relationship in s-domain is adopted to study the frequency modulation in SSCG. The linear model is shown in Fig. 5.4, where Δωout is the output frequency deviation, Δωsig is the input modulation frequency deviation, and Gm is the gain mismatch factor stand for compensation between two paths. Two noise sources are taken into consideration: modulator quantization noise ΦΔΣ and VCO phase noise Φvn. According to (5.2), the gain mismatch may come from the process

vco p3 1 2

to the proposed DAC.

To see the advantage of two-point modulation, we first examine the results with only one point modulation Vx. For simplicity, the noise sources are ignored. The transfer function from Δωsig to Δωout can be described as

( ) ( )

actually a low pass behavior when F(s) in (5.3) is taken into account. Δωout can be given as

( ) ( )

^ramp

with K=Kd×Kvco×R1/N. K is approximately equal to the loop bandwidth of PLL and ω2=1/R1C1K2 is the zero of the loop filter. Here, the C2 effect is neglected. The frequency

Usually ω2<<K, (5.7) can be approximated by

( )(

)

Using inverse Laplace transforms, the transient response is obtained

( ) ( )

Fig. 5.5 Simulation results of frequency error with a frequency sweep input

Fig. 5.6 Phase noise simulation for FN-SSCG and TPDL-SSCG

The maximum frequency error, Δωerr, can be found by (5.9)

( )

max _err M^ramp ω K

Δ ∝ . (5.10)

Equation (5.9) and (5.10) indicate how the low pass behavior causes frequency errors and distorts the output. It is clear that Δωerr=0 only if K=∞, i.e., the loop bandwidth is infinitely large.

With two point modulation activated, by the superposition principle, the closed loop transfer function of Fig. 5.4 can be derived as:

( ) (

( ) )

The first term in the right hand side is the same as (5.4). The second term appears as a high pass and can be treated as a complementary part if Gm=1. Therefore, from (5.11), Δωout

is equal to Δωsig if Gm=1. This means that the output is all pass without distortion and bandwidth limitation. The frequency errors for both one-point modulation and the proposed scheme, with a frequency ramp input, are shown in Fig. 5.5. Here, Gm=1. The other parameters are listed in Table 5.1. The solid line is the ideal all pass, the dashed line is from (5.4), the dashed-doted line is from the second term in (5.11), and the line with a circle mark are the output from (5.11). The dashed line cannot track the input frequency change well due to insufficient loop bandwidth. On the contrary, the line with circle mark can always track the input so that the output error is eliminated. Thus, the proposed scheme can track the modulation waveform very well and is independent of the PLL loop bandwidth as long as the paths are matched.

5.2.4 Analysis of Noise Power Spectral Density from the ΔΣ Modulator The power spectral density is closely related to the order of the ΔΣ modulator and the loop bandwidth. It is already known that a high order ΔΣ modulator is used to reduce the fractional spur within the loop bandwidth. In this design, only a second order ΔΣ modulator is chosen to save area and power, while maintaining jitter and EMI performance. To see the

interrelation between the order of the ΔΣ modulator and the PLL loop bandwidth, the output phase noise originated from the ΔΣ modulator and the VCO are investigated. The noise power spectral densities (PSD) of the phase SΦ(f) can be expressed as

( ) ( )

( ) _VCO

S_Φ f =S_Φ f +S_ΦΔΣ f , (5.13)

where SΦvco(f) and SΦΔΣ(f) are the noise of the VCO and the ΔΣ modulator, respectively. SΦΔΣ(f)

[11] can be found as

where m is the order of the modulator, and fbk is the operational frequency of the modulator.

SΦvco(f) can be easily derived as

( ) 1 ( ) 2

VCO vn s j f

S_Φ f =S_Φ ⋅ −T s ₌ _π , (5.15)\

where SΦvn is the stand alone VCO phase noise.

In general, the loop bandwidth is much less than the phase comparison frequency fbk at the phase detector to avoid the spur. From (5.14), it is realized that the shape of output PSD, caused by the ΔΣ modulator, is increasing inside of the PLL loop bandwidth with f²⁽^m⁻¹⁾ and decreasing outside of the PLL loop bandwidth. In other words, the smaller the PLL loop bandwidth, the lower the jitter caused by the ΔΣ modulator. However, a large PLL loop bandwidth is needed to pass faithfully the modulation profile. Otherwise, the spectrum appeared at the output of PLL will be distorted, the spread ratio will be incorrect and EMI performance will be degraded. Thus, the PLL loop bandwidth is a trade-off between the modulation profile and the jitter performance. In the conventional situation [36], the bandwidth is approximately ten times the modulation frequency to obtain modulation performance. The in-band fractional spur are suppressed by a third-order ΔΣ modulator to minimize the phase noise and jitter. In addition, a third-order loop filter is needed to reduce the out-of-band phase noise and jitter caused by the comparison clock. In other words, it requires higher power consumption and more area. However, thanks to the all pass nature in

profile distortion.

The PSDs for the conventional fractional-N SSCG (FN-SSCG) and the two-point SSCG (TPDL-SSCG) in non-spread spectrum mode are illustrated in Fig. 5.6. Only the VCO and the modulator quantization noise are taken into account. The VCO phase noise is assumed as -89 dBc/Hz at the offset frequency of 1 MHz with the shape of f^-2. Other simulation parameters are listed in Table 5.1. Two different cases with loop bandwidths of 100 kHz and 300 kHz are studied. A third pole of 4.5 MHz is needed for the FN-SSCG to further filter the quantization noise of the third-order modulator. The center frequency is set at 1500 MHz, the spread ratio is -0.5%, and the modulation frequency is set at 31.25 kHz. The solid and dashed lines represent the total phase noise for the FN-SSCG with a 300 kHz loop bandwidth and TPDL-SSCG with a 100 kHz loop bandwidth, respectively. The contributions from the VCO are denoted by circle and plus marks in different cases. The phase noise from the ΔΣ modulator is denoted by diamond and square marks. Although the in-band phase noise in the proposed TPDL-SSCG with a second order ΔΣ modulator is larger than the case in the FN-SSCG with a third order ΔΣ modulator, the TPDL-SSCG still has enough performance in terms of EMI suppression, modulation profile linearity, and jitter through the following analysis and measurements.

The chip areas for the second-order, and third-order, MASH ΔΣ modulator are evaluated as 3920 and 4887, in units of gate-counts, respectively. The power consumption using the TSMC 0.18 μm process is 1.40 mW and 2.00 mW, respectively. The area is approximately 20% off in digital area and approximately 5% off in whole area, and the power is approximately 4% off in whole power consumption when using the second-order ΔΣ modulator. The 4 to 5% difference is still important because the power and area of the proposed SSCG is only 15.3 mW and 0.21 mm², respectively. Hence, in this work, a second-order ΔΣ modulator and a 100 kHz loop bandwidth, with a second-order loop filter, are designed for saving power and area.

Table 5.1 SSCG Simulation Parameters

FN-SSCG TPDL-SSCG

Input Frequency 25 MHz 25 MHz Output Frequency 1500 MHz 1500 MHz

Spread Ratio -0.5%-0 -0.5%-0

VCO Gain 480 MHz/V 480 MHz/V

Loop Bandwidth 100/300 kHz 100/300 kHz

Modulator third-order MASH second-order MASH Loop filter third-order second-order

Third pole frequency 4MHz N/A

Fig. 5.7. Simulation results for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.

Fig. 5.8 .Spectrum simulation results with the ΔΣ modulator noise for the FN-SSCG and the PDL-SSCG under different loop bandwidths.

Fig. 5.9. Spectrum simulation results without the ΔΣ modulator noise for the FN-SSCG and the TPDL-SSCG under different loop bandwidths.

5.2.5 Simulation Results

To compare the performance between the FN-SSCG and the TPDL-SSCG, the following simulations are made. The same parameters listed in Table 5.1 are used. The output frequency swings are shown in Fig. 5.7. Four different spread ratios of 0.543%, 0.523%, 0.506%, and 0.510% for the FN-SSCG with a 100 kHz BW denoted curve-a, the FN-SSCG with a 300 kHz denoted curve-b, the TPDL-SSCG with a 100 kHz BW denoted curve-c, and the TPDL-SSCG with a 300 kHz BW denoted curve-d are obtained, respectively. The corresponding spectra results with the ΔΣ modulator noise are shown in Fig. 5.8. The simulated spectra with ΔΣ modulator noise are 20.35 dB, 19.69 dB, 20.47 dB, and 19.21 dB for curve-a, curve-b, curve-c, and curve-d shown in Fig. 5.7, respectively. The simulation results are summarized in Table 5.2. It is known that the larger the spread ratio, the better the EMI performance. To see the efficiency of EMI performance, the EMI reduction and its spread ratio need to be considered simultaneously. Therefore, the ratio of EMI in dB to spread ratios in percentage denoted by EMInorm is also evaluated. The case of the FN-SSCG with a 100 kHz BW has the largest peak-to-peak spread ratio (0.545%) deviation from the ideal value 0.5%, and the smallest EMI efficiency with the value of 37.34 dB/% because the PLL loop bandwidth is not enough that the output could not track the modulation profile and is distorted. Small peaks existed at two ends of the spectrum for the case of the FN-SSCG with a 100 kHz BW, meaning that it is not a good triangular waveform. The case of the FN-SSCG with a 300 kHz BW has better performance in terms of the spread ratio (0.523%) and EMI efficiency (37.65 dB/%) compared to one with a 100 kHz BW. However, it is clearly indicated that the case of the TPDL-SSCG with a 100 kHz BW has not only a more accurate

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