CHAPTER 1 INTRODUCTION
1.4 Organization of This Thesis
1.4 Organization of This Thesis
This thesis is divided into five chapters. In Chapter 1, the background and motivation of this research are presented. In Chapter 2, the circuit of the automatic gain control is proposed. Design consideration, and design concept of the automatic gain circuit are discussed in Section 2.1, and section 2.2 respectively. Then the AGC architecture is presented in Section 2.3. The principle of operation of all the circuits building the AGC block is presented in Section 2.4. Finally, the simulation results are shown in Section 2.5. In Chapter 3, the circuit of the receiver is proposed. Receiver fundamentals and design considerations about the receiver circuits are reported first in Section 3.1 and Section 3.2 respectively. Then the
operational principle and circuit diagram of low noise amplifier, voltage controlled oscillator (VCO), and quadrature mixer, are shown in Section 3.3, 3.4, and 3.5 respectively. Finally, the simulation results are presented in Section 3.6. In Chapter 4, the layout for the CMOS AGC circuits is described. In Chapter 5, the conclusion and the future works are given.
Chapter 2
THE DESIGN OF THE AUTOMATIC GAIN CONTROL CIRCUIT
2.1 Design Consideration
Direct-conversion receivers exhibit important advantages over superheterodyne receivers in some applications such as paging receivers [8], [9]. The most important feature of any direct-conversion receiver is its inherent simplicity. Such simplicity allows the designer to obtain small size and low power consumption in his design. The price paid for this simplicity is losing some important electrical features like dynamic range.
To increase the dynamic range of the receiver via overcoming the changes in the input signal strength by producing a known output voltage, AGC systems should be used. The role of the AGC circuit is to provide a relatively constant output amplitude so that circuits following the AGC circuit as shown in Fig. 2-1 require less dynamic range. Usually, error free recovery of data from the input signal cannot occur until the AGC circuit has adjusted the amplitude of the incoming signal.
As direct-conversion receivers posses many problems [10]-[13], like dc offsets and flicker noise, many constraints on the designed AGC should be taken into consideration. Such constraints include:
- The AGC must include dc offset cancellation circuitry, without which clipping of the subsequent stages will result if not properly rejected.
- Possessing wide tuning range, and high dynamic range.
- The increase of the noise figure of the system due to the utilization of the AGC should be low.
- Fast enough and low power consumption.
- It should offer continuous control of the received signal instead of discrete control.
- It should work with a low pass filter to reject any continuous wave or modulated interferers.
Received data pattern at analog input Fig. 2-1 Modern communication system
2.2 Design Concept
Usually, error free recovery of data from the input signal in digital communication systems cannot occur until the AGC circuit has adjusted the amplitude of the incoming signal. Such amplitude acquisition usually occurs during a preample where known data are transmitted, as shown in Fig. 2-1.
The preample duration must exceed the acquisition or settling time of the AGC loop, but its duration should be minimized for efficient use of the channel bandwidth. If the AGC circuit is designed such that the acquisition time is a function of the input amplitude, then the preample time is forced to be longer in duration than the slowest possible AGC circuit acquisition.
Consequently, to optimize system performance, the AGC loop settling time should be well defined and signal independent.
The AGC loop depicted in Fig. 2-2 consists of a variable gain amplifier (VGA), a peak detector, and a loop filter. The AGC loop is in general a nonlinear system having a gain acquisition settling time that is
input signal level dependant. With the addition of the logarithmic function block between the envelope detector and the loop filter, and appropriate design of the loop components, the AGC system can operate linearly in decibels [14]. This simply means that if the amplitude of the input and output signals of the AGC are expressed in decibels (dB), then the system
response can be made linear with respect to these quantities. Since this logarithmic function needs more circuits to be realized, this block will be omitted in this design. To see under what constraints this new architecture can work, some derivations without this block will be performed as shown below.
Without loss of generality all signals shown will be expressed as voltages. The gain of the VGA, G(Vctr.), is controlled with the voltage signal Vctr. The peak detector and loop filter form a feedback circuit that monitor the peak amplitude, Ao, of the output signal Vo and adjusts the VGA gain until the measured peak amplitude, Vp, is made equal to the DC reference voltage, Vref. The output of the AGC circuit is simply the gain times the input signal: Vout (t) = G(Vctr.) Vin(t).
Since the feedback loop only responds to the peak amplitude, the amplitude of Vout is
Ao = G(Vctr) Ai (2.1)
Where Ai is the peak amplitude of Vin.
The equivalent representation of an AGC circuit, shown in Fig. 2-3, is a mathematical tool that is derived from Fig. 2-2 as follows. First, the feedback loop of the AGC circuit operates only on signal amplitude; hence the AGC input and output signals are represented only in terms of their
amplitudes Ai, and Ao respectively. Second, since the VGA multiplies the input amplitude Ai, by G(Vctr) as shown in equation (2.1), an equivalent representation is
Ao = Kexp [ln [G(Vctr)] + ln [Ai/ K]] (2.2)
Where K is a constant with the same units as Ai and Ao. The AGC model in Fig. 2-3 uses equation (2.2), but duplicates the K exp( ) function inside and outside the outlined block so that x(t) and y(t) represent the input and output amplitudes of the AGC, expressed in decibels within a constant of proportionality. Similarly, the z input shown, is the value of Vref. expressed in decibels within a constant of proportionality. The peak detector in Fig. 2-2 will be assumed to extract the peak amplitude of Vo(t) linearly and much faster than the basic operation of the loop so that Vp = Ao. Hence, the peak detector is not explicitly shown in Fig. 2-3. Finally, the loop filter in Fig. 2-2 is shown as an integrator in Fig. 2-3, with H(s) = gm / sC.
-Fig. 2-2 Block diagram of the AGC.
Fig. 2-3 Equivalent model for the AGC circuit
To derive a formula for the settling time of the AGC, assuming that the AGC loop is operating near its fully converged state (i.e., Ao = Vref.), we
can proceed as the following:
The output y(t) in Fig. 2-3 is given by
y(t) = x(t) + ln (G(Vctr)) (2.3) The gain control voltage is derived as
C dVctr/dt = gm[K exp(z) – K exp(y)] (2.4)
Taking the derivative of (2.3) and substituting in the derivative of (2.4), the following expression is obtained:
dy/dt = dx/dt + 1/G(Vctr) dG/dVctr gm/C K[exp(z) – exp(y)] (2.5)
Let 1/G(Vctr) dG/dVctr gm/C = Kx
Using the Taylor series expansion, we get exp(y) = exp(z) [1+y(t) – z +…]
Equation (2.5) can be written as
dy/dt + Kx Vref y(t) = dx/dt + Kx Vref ln(Vref/K) (2.6)
The first order linear system described by (2.6) has a high pass response with a time constant of
τ = 1/(Kx Vref) = [1 / G(Vctr) dG/dVctr gm/C Vref.] -1 (2.7)
If the loop filter components gm and C are linear and time invariant, then the constraint on constant settling time for the AGC loop is that the VGA has an exponential gain control characteristics. Under these conditions, the AGC loop has a time constant given by
τ = C/ (gm Kx1 Vref) (2.8)
Where Kx1 is constant, and equals
Kx1 =1/ G(Vctr) dG/dVctr (2.9) Integrating both sides of the above equation, produces the exponential gain characteristics of the VGA
G(Vctr)= Kx2 exp(Kx1 Vctr) (2.10)
WhereKx2 is the constant of integration. Notice that the settling time is a function of the input variable Vref, indicating the system is fundamentally nonlinear. By changing Vref, the operating point where the small signal approximation was made changes, and hence the AGC loop parameters change.
In our AGC circuit design, we have the following relations and parameters:
G(Vctr) = 35.2 Vctr – 13.6 G(2V) = 56
Vref = 0.5V C = 2pF
To have a settling time less than 16µs according to 802.11a standard, then gm should be larger than 0.4µA/V according to equation (2.7).
2.3 AGC Architecture
Figure 2-4 shows the block diagram of the proposed AGC inside the target receiver. The AGC circuit is composed of four variable gain amplifiers, peak detector, loop filter, low pass filter, and dc offset cancellation circuits. The baseband I and Q signals at the mixers output are
amplified by high pass amplifiers. Four stages of VGAs are incorporated throughout the baseband signal path to provide both high gain and dc offset cancellation. The gain of the VGAs is controlled by a feedback gain control signal (Vctr.). The peak detector extracts the signal amplitude. This signal will pass to the loop filter to be compared with a reference voltage. The loop filter will then generate a dc-like VGA control signal, Vctr. A sixth order low pass filter is integrated between the first two and the last two VGAs for channel selection and to reject any continuous wave or modulated interferers. The fully differential circuit architecture is employed in the circuit to ensure that it has better common mode noise rejection.
2-4 Principles of Operation
In this section, the principle and circuit design of the main blocks of the AGC, namely VGA, peak detector, loop filter, and low pass filter will be presented.
H P F
Fig. 2-4 The AGC inside the receiver
2-4-1 Variable gain amplifier including dc offset cancellation circuits There are several ways to vary the gain of an amplifier. As shown in Fig. 2.5, the gain of a simple differential amplifier can be controlled by its bias or loading. By tuning the loading RL1 and RL2, the gain at low frequencies is varied, but its common mode output voltage is also changed and affects the bias for the next stage. Alternatively, the gain can be varied by tuning the bias Ib [15]. However, when the signal is large, the bias should be set to a smaller value to get a smaller gain, in this case, the dynamic range of the input devices is also reduced. This is opposite to the requirement of a
VGA [16]. In addition, the common-mode output also depends on the gain, and this technique also entails a lot of power dissipation to obtain gain variation [17].
Fig. 2.5 Existing gain varying techniques
High input-referred offset voltage is one of the most important drawbacks of MOS analog circuits when compared to their BJT and BiCMOS counterparts. Typically the offset voltage can be as high as 20 mV, which can easily saturate the amplifier output stage when the DC gain is high enough. This problem is even worse in low-supply applications.
Traditional offset cancellation techniques [18][19] usually utilize sampling circuit and memory components to sample, store and cancel the offset voltage. As shown in Fig. 2.6, the offset voltage is sensed and stored in a capacitor during the calibration period, and feeding it back to signal after the calibration. The main problem with these methods is that they require a
clock signal and a calibration period. A clock signal would cause problems with clock feedthrough and charge injection, which makes cancellation inaccurate. A calibration period would reduce the overall speed and prevent the amplifier to operate continuously.
Fig. 2.6 Existing offset cancellation [18]
To achieve automatic offset cancellation, some techniques [20][21]
also use some logic circuits to control the amplifier and the tuning circuitry.
However the controlling and tuning circuitry will introduce large noise, consume more power and occupy more chip area. They still have the problems of clock feedthrough and charge injection and cannot operate continuously.
In this design, and as shown in Fig. 2.4, the first baseband block, the VGA, allows adjusting receiver gain to limit the output signal level. In the baseband receive path of this design, there are four cascaded variable gain amplifiers, one high pass filter, and two autozeroing loops (op-based integrator). One high pass filter and two autozeroing loops are used to
eliminate the dc offset introduced by VGAs and the previous stages. Two autozeroing loops and one high pass filter are utilized instead of one autozeroing loop since the cutoff frequency of the autozeroing loop is proportional to the gain of the variable gain amplifier. The high pass filter is placed in the former stage since it has better noise performance than the autozeroing loop, while autozeroing loops are placed at the latter stages to reduce the phase introduced by the VGAs.
The proposed AGC is realized with 4 identical VGA cells, as shown in Fig. 2.4. The gain of each cell can be varied independently from 0 dB to 16 dB by adjusting its own control voltage Vctr.. To achieve a minimum NF, the gain of the first two stages should be as high as possible [22]. In other words, when the signal is large, the gain of the third and fourth stages should be reduced before the gain of first two stages is reduced. However, for large input signals, the noise requirement of the VGA is actually relaxed.
The schematic of the VGA is shown in Fig. 2-7. In this circuit the input stage is a degenerated differential pair realized by means of MOS devices [23], biased in the linear region, shunting fixed value resistors. The input stage transconductance and therefore the amplifier gain is varied by varying the MOS resistance via Vctr. To maximize the gain, the resistive load (R1, and R2) is differential while two PMOS devices (M1 and M2) provide
current to the input stage. This configuration requires common mode feedback (M7, M8, M9, and the current source), but has the advantage of lower dc voltage drop. The flicker noise of the PMOS current sources has a negligible impact on the noise figure. To lower out of band blockers, a differential resistive-capacitive load (C1, C2, R1, and R2) is used to realize 20MHz pole to lower out of band blockers. Moreover, the input devices (M3, M4) have larger area to reduce the flicker noise. So, this VGA circuit design meets best the receivers, which require low noise, large gain for a small input signal and large continuous gain turning range. By turning its control voltage (Vctr.), its transconductance can be varied and hence its gain.
By varying the Vctr from 0V to 2V, the gain of the VGA sweeps from minimum to maximum.
Fig. 2-7 The utilized v lifier
V D D
The variatio e is shown in Fig.2-8. It is clear that the relation is linear only for small portion of Vctr. Since
n of the VGA gain with the control voltag
the receive path contains four VGAs, they can be tailored to better approximate a linear-in-dB characteristic. It can be done using two control voltages. One (Vctr.) is connected to the first two VGAs and the other one (0.4Vctr.) to the rest two VGAs. This will make the control curve more linear and achieve a smaller gain turning sensitivity. In this design, the gain of the cascaded four VGAs will change from –10dB to 56dB when Vctr changes from 0V to 2V.
Fig. 2-8 Gain variation of the VGA versus frequency
Since s. Each two stages have an independent gain control. Different gain distributions give d
1/A2IP
et to maximum gain, the noise figure of the whol
well. F
. For the sensitivity of -82dBm, the dynamic range of the wanted signal is -10dBm - (-82dBm) = 72dB.
the AGC consists of a cascade of 4 identical VGA stage
ifferent NF and IIP3 of the whole AGC. Assume A1, A2, A3, A4 are gain of first, second, third, fourth stage. F1, F2, F3, F4 are noise factors.
AIP31, AIP32, AIP33, AIP34 are input referred interception points. The noise factor of the whole AGC, F, is then:
F= F1 + (F2-1)/(A21) + F3-1/(A21A22) + F4-1/ (A21A22A23) (2.11) And the IIP3 of the AGC is:
3 = 1/A2IP31 + A21/A2IP32 + A21A22/A2IP33 + A21A22A23/A2IP34 (2.12) When all stages are s
e AGC is minimized, however the IP3 is degraded to minimum value as or a large input signal, the total gain of the AGC will be decreased to a smaller value. Since the signal power is large, the noise contribution from the AGC is not important any more, the gain of all stages can decrease at the same time. The IIP3 of the whole amplifier can also be improved when the gain in the first and second stage decreases.
The variable gain amplifier (VGA) is used to amplify the signal further and reduce the signal dynamic range
Becau
e system (required by 802.11a standard) = 10dB
VGA is also more relaxed because the by the low pass filter. Because the gain P3 of the VGA is varying too. Therefore, the lineari
to monitor the trength of the signal. The structure of the differential peak detector is shown
l diode can be constructed using the unidirectional se of gain in previous stages, the NF requirement of the VGA is relaxed. Assume F>>1,
NFvga≈NFsys + Gainlna + Gainmix + Gainfilter - 3 In this proposed receiver, we have:
NFsys: noise figure of th
Gainlna: gain of the LNA = 19dB Gainmix: gain of the mixer = 0dB Gainfilter: gain of the filter = 7dB
= 10 + 19 + 0 + 7 -3 = 33 dB.
The IIP3 requirement of the interference signals are suppressed of the VGA is varying, the II
ty of the VGA is defined in output-referred IP3 (OIP3)
2.4-2 Peak detector
In the feedback loop, we should use a peak detector s
in Fig.2-9. The idea current mirror [24].
VDD
Fig. 2-9 Structure of the differential peak detector
Transistors, M1, M2, M9, M10 combined with the current mirror M3, and M4 can be represented by a transconductance amplifier, as shown in
Fig. 2-10. W , and M10
are n
hen Vi+ is smaller than Venv., drain currents of M9
u balanced, such that a current pulse is generated at drain of M3. This current pulse discharges node Venv. through current mirror M3, and M4, forcing Vi+ to track Venv. As Venv approaches Vi+, drain currents of M1, and M2 are almost equal, so drain current of M3 is approximately zero. As a result, tracking behavior of the peak detector can be increased by increasing gm/C.
VDD
Fig. 2-10 Equivalent circuit of the peak detector.
2.4.3 Loop f
The gain of the VGA block is c ctr,
by the loop filter. The loop filter is composed of a two ilter
ontrolled by the control voltage, V which is generated
inputs transconductance cell (gm-cell), and a loading capacitor, C as shown in Fig. 2-11. The output of the I and Q peak detectors are summed together and applied to the input of the loop filter. The sum of these two input signals will be compared with a reference voltage value, Vref, to generate Vctr.
Table I shows the component values and channel dimensions of the MOS devices of all the circuits building the AGC.
Fig. 2-11 Structure of the loop filter
Device Value
Table I Component values and channel dimensions of MOS devices of the AGC.
2.4.4 Low pass filter
The design of full CMOS continuous-time filters can be realized with MOSFET-C or OTA-C techniques. However to achieve low power supply voltage and to achieve at the same time low-distortion specifications, the OTA-C technique is preferred. Even preferred, such filters introduce two problems. First of all, the OTA is not very linear. Its third-order harmonic distortion is given by:
HD3= (Vp)2/(32(Vgs-Vt)2) (2.13)
Where Vp is the maximal input amplitude, peak. It follows that a Vgs–Vt of 0.5V gives an HD3 of 0.125% when Vp is 100 mVp.
Another source of nonlinearity in the filter is the presence of junction capacitors. Its effect depends on how much of the total capacitance is made out of junction capacitance. It is calculated in [25] that the HD3 is in the order of –60 dB or 0.1% when half the integrating capacitance consists of junction capacitance.
The required integrated low pass filter should satisfy the following technical specifications:
- Simulated LC ladder, resistive terminations - Passband frequency from zero to 10MHz.
- Passband ripple should be less than 0.5dB.