CHAPTER 3 THE DESIGN OF THE 5GHz CMOS
3.4 Quadrature Down Conversion Mixer
In the RF mixers, the important design parameters are noise figure (NF), conversion gain (CG), third-order input intercept point (IIP3), and port
-to-port isolation. These parameters should be designed to meet the requirements of various standards for different wireless communication systems.
In this design, the mixer is intended to be used as the RF downconversion block in the wireless receiver shown in Fig. 1-1. As seen from that Figure, the mixer is placed after the low noise amplifier (LNA).
The LNA provides sufficient power gain to mask the noise contribution of the subsequent stages. Thus the noise figure contributed by the mixer can be ignored if its value is lower than the total gain of the previous stages.
Since the LNA has provided sufficient gain, the conversion gain of the mixer should not be high to overdrive the subsequent stages. Higher gain also implies higher signal swing in the circuit, which could degrade the linearity and the dynamic range. Nevertheless, very low gain far below 0dB is also unacceptable because the noise contributed by the stages after the mixer becomes higher. Thus the value of conversion gain around 0dB is acceptable.
In the modern wireless systems, the receiver could subject to an environment with large adjacent channel interfering signals. Due to the nonlinearity of the receiver, those interfering signals produce co-channel interference, which degrades the signal-to-noise-ratio of the received signal.
Thus IIP3 of the receiver, which indicates the ability of the receiver to reject the interfering signals becomes a very important feature of the RF receiver.
In most cases, the signal power handled by the RF mixer is higher than those by the other stages in the receiver. Thus IIP3 of the mixer is a critical parameter in the receiver design. In order to sustain a high receiver linearity, IIP3 of the mixer should be as high as possible.
The port to port isolation and LO power are also important issues in the mixer design. The LO power in the order of a few dBm is often required by the mixer to obtain high linearity and high dynamic range. Such a high LO power causes the LO energy leaks through the RF port and radiates from the antenna if the port isolation of the mixer is not high enough. The design criteria of the mixer is to keep the LO power as low as possible and increases the port isolation.
LTI system cannot provide outputs with spectral components not present at input. So, mixer must be either nonlinear or time varying in order to provide frequency translation. Mixer performs frequency translation by multiplying two signals (with their harmonics) in time domain.
Since the MOS transistor is basically a square-law device, then it can be used to implement second-order transfer functions [34]. In this receiver, the utilized mixer is a quadrature one, and Fig. 3-7 shows the circuit diagram
of the in-phase output of the mixer. In this circuit, type-A combiner consists of eight transistors (M9~M16), while type-B combiner consists of four transistors (M17~M20]. The transfer function of the two combiners can be modeled by the drain current equation of the MOS transistors in the saturation region. Using the ideal square law current identity of MOS transistors, the drain current ID can be expressed as
ID = K (VGS – VT) 2 (3.14) Where K= µs (Cox/2)(W/L) is the transconductance parameter, µs is the effective surface carrier mobility, Cox is the gate oxide capacitance per unit area, W/L is the channel width (length) of the MOS device, VGS is the gate-source voltage, and VT is the threshold voltage.
If the transistors in the type-A combiner are operated in the saturation region, the output voltage at the their drains terminals can be written as functions of the input signals LOQ+, LOQ-, RF+, and RF- by using (3.14).
The same thing can be done for the B-type combiner.
The supply voltage of the mixers can be as low as 1.8V, since only two transistors are cascaded between power supply and ground. By the way, the down-conversion mixers and VCO share the same current and so the power consumption will be reduced obviously. In comparison with other architectures, the current- reused method, as shown in Fig. 3-8, particularly
highlights the advantages of the low-power consumption in direct
Fig. 3-7 In phase output of the down conversion mixer
Fig. 3-8 The concept of current reuse technique in the receiver
3.5 Merged Quadrature Voltage Controlled Oscillator
Fig. 3-9 The conceptual block diagram of the voltage controlled oscillator
To implement the integrated quadrature VCO, a circuit structure based on the two-stage ring oscillator with LC-tank loads is proposed [35]. As shown in Fig 3-9 two fully differential narrow-band LC-tuned inverters are connected to form a two-stage ring oscillator structure for signal oscillation.
The output waveforms at the differential output nodes of one inverter are 90° out of phase from those at the differential output nodes of the other one.
Thus, these two differential output waveforms are synchronized in
quadrature phases [35]-[37]. When the delay time of the two fully differential inverters are kept the same at oscillation, the outputs of these two fully differential inverters can provide highly accurate quadraturesignals. By incorporating the LC-tank loads into two-stage ring oscillator, the performance of proposed quadrature VCO is significantly improved with respect to the following specifications: phase noise, frequency stability, and supply voltage sensitivities.
In order to efficiently reduce chip area, power dissipation, and quadrature phase error, the quadrature VCO is cascoded with quadrature mixer as shown in the block diagram of Fig. 3-8. As may be seen from Fig.
3-8, the cascoded quadrature VCO and quadrature mixer use the same current I1 (3mA). In this way, the total power dissipation can be optimized.
Furthermore, the signal paths from quadrature VCO to quadrature mixer can be kept very short and symmetrical to alleviate the influence on the quadrature phases of VCO output signals by the parasitic components on the signal paths. Thus the phase error and amplitude mismatch can be minimized.
M6 M5
Fig. 3-10 is the circuit diagram to demonstrate the implementation of quadrature VCO using the two-stage ring oscillator with LC-tank loads. The MOS transistors M1, M2, M3, and M4 are connected to form a two-stage ring oscillator to be used as the phase controller. The negative resistor in Fig.
3-10 is realized by two cross-coupled MOS transistors M5 and M6 (M7 and M8) and connected in parallel with the LC-tank loads to cancel the parasitic series resistance of spiral inductors and guarantee oscillation.
As shown in Fig. 3-10, the LC-tank loads consists of a spiral inductor L1 and L2, P+/N-well varactor diodes MD1, MD2, MD3, and MD4, and the parasitic capacitances of M1, M2, M3, M4, M5, M6, M7 and M8. The two
P+/N-well varactor diodes can be tuned simultaneously by the control voltage VC1 to obtain the desired oscillation frequency expressed as
fosc. = 1/2π LCHz.
where L is the inductance of the spiral inductor, and C is the total parallel equivalent capacitance. The maximum impedance of the LC-tank loads occurs at the oscillation frequency. At this frequency, the fully differential inverter achieves the maximum gain and the ring oscillator can maintain the quadrature oscillation. At other frequencies, the gain of the fully differential inverters is decreased due to the decrement of the impedance of the LC-tank loads. Thus the ring oscillator cannot maintain the quadrature oscillation. So the oscillation frequency is only dependent on L and C of the LC-tank loads.
The component values and channel dimensions of the MOS devices for the mixer and the VCO are summarized in table V.
Device Value Table V Component values and MOS dimensions of the mixer and the
VCO.
3.6 Simulation Results
The receiver’s front-end blocks have been simulated using Hspice with 0.18µm CMOS technology.
The simulated results of the LNA voltage gain and noise performance with operating current under 50-Ω system impedance are shown in Fig. 3-11. The LNA achieves a NF of 2 dB at 5.15 GHz with 4mA current drain from a 2-V supply. This is the lowest NF reported to date or at least according to my knowledge for a CMOS LNA operating in the 5 GHz band.
The mixers were also individually characterized and simulated. When biased with 3mA current and driven by –4dBm LO signal, the mixer has a conversion gain of 0 dB, and a 7 dB SSB noise figure. Fig. 3-12 shows the output transient waveforms of the quadrature oscillator. The LO frequency is 5GHz, the phase error is 0.6° and the amplitude error is 2mV.
The quadrature VCO covers a wide operating frequency range, from 5 GHz to 5.5 GHz. The tuning characteristic of the VCO under different control voltages is shown in Fig. 3-13. The simulated phase noise of the quadrature VCO is –100dBc/Hz at 500 KHz away from 5.15 GHz center frequency. The output spectrum of the VCO and the mixer are shown in Fig.
3-14, and Fig. 3-15 respectively. The low power operation of this receiver is
enabled by the current reuse technique used among quadrature VCO and mixer.
Linearity of the front-end of the receiver is evaluated with a two-tone simulation as shown in Fig.3-16. The input-referred IP3 is –5dBm, with a 1-dB compression point of –151-dBm. This is due to the high linearity of the short channel MOS- transistors.
The variation of the S11 parameter with frequency for the receiver front-end is shown in Fig.3-17. It approaches –19 dB at 5.15 GHz
(a)
(b)
Fig. 3-11 (a) Simulated LNA voltage gain versus frequency (b) Simulated LNA NF versus frequency.
Fig. 3-12 The output waveform of the quadrature oscillator
Fig. 3-13 The tuning characteristics of the VCO.
Fig. 3-14 The VCO output spectrum
Fig. 3-15 The mixer output spectrum
Fig. 3-16 Two-tone intermodulation simulation results of the receiver’s front-end
Fig. 3-17 Receiver’s front-end S11 parameter versus frequency.
Table IV summarizes the receiver performance.
Performance
Table IV Simulated received performance compared to that required by IEEE 802.11a standard.
Chapter 4
POST SIMULATION RESULTS
4.1 Chip Layout Description
The layout for one VGA using the CMOS 0.18µm 1P6M technology is shown in Fig. 4.1.
Fig. 4.1 Layout of one VGA circuit
The overall AGC circuit is shown in Fig. 4.2. The total area is .08mm2
4.2 Simulation Results
The post simulation results of the AGC circuit compared to the pre simulation results are shown in table V. The results are quite close to each other.
Fig. 4.2 Layout of the AGC circuit
Parameter Pre simulation
results
Post simulation results
Pass band range 106KHz~20MHz 100KHz~20MHz
Voltage gain -10~56dB -10~55dB
Dynamic range 60dB 60dB
Power consumption 11mW 10mW
Area _ .08mm2
Table V Comparison between pre and post simulation results for the AGC circuit
Chapter 5
CONCLUSIONS AND FUTURE WORKS 5.1 Conclusions
In this thesis, a 2-V 5-GHz direct conversion receiver has been designed and simulated using 0.18µm CMOS technology. The receiver achieves 4dB double sideband noise figure (NF), 90dB voltage gain, -7dBm input IP3 and dissipating 45mW. The receiver gain is carefully distributed before and after the mixer to minimize the 1/f noise contribution to the overall system noise. This receiver achieves the lowest noise figure and power consumption reported to date for a 5GHz direct conversion receiver.
This receiver complies with the performance requirements of the IEEE 802.11a wireless communications standard for operation at 5GHz.
An automatic gain control (AGC) circuit with high dynamic range is incorporated inside this receiver. The AGC achieves 7dB noise figure, 66dB tuning range, and dissipating 11mW. The problem of dc offset appears in direct conversion receivers due to the imperfect isolation between LO port and the inputs of the mixer and the LNA is cancelled using ac-coupling technique including trade-off between degradation of signal-to-noise ratio due to high cutoff frequency and slower transient related to low cutoff
frequency. The large and the continuous gain turning range of the AGC increases the dynamic range of the receiver. Moreover, as the noise figure of the AGC circuit is low (7dB), then the increment of the receiver’s overall noise figure due to the utilization of the AGC is acceptable. Finally, the obtained results show clearly that CMOS could be used to implement a high-performance, low power RF circuits in the low-GHz frequency range.
5.2 Future works
In the receiver design, although many simulation results have been shown to verify the function of the receiver, the hardware implementation is still needed for further verification. Furthermore, CMOS receiver circuits operated at lower supply voltages below 2V can be developed to meet the requirement of the future portable equipment. Moreover, further reduction in the power consumption, and noise figure of the AGC circuit is still required. Moreover, a chip for the AGC circuit will be fabricated, and further measurements on the chip will be carried out.
REFERENCES
[1] A. Abidi,” Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec.1995.
[2] B. Razavi,” RF IC design challenges,” in proc. Design Automation Conf., San Francisco, CA, 1998, pp. 408-413.
[3] W.A. Serdijin”A Low voltage low power fully integratable automatic gain control for hearing instruments,” IEEE Journal of Solid-State Circuits, Vol. 29, No.8, August 1994.
[4] R. Harjani, “A low-power CMOS VGA for 50 Mb/s disk drive read channel’s,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 42, No.6, June 1995.
[5] G.S Sahota, “ High dynamic range variable gain amplifier for CDMA wireless applications,” ISSCC97, Session 22, February 1997.
[6] Francisco Javier,”a direct conversion receiver using a novel ultra low power AGC,” ISSCC97, 1997.
[7] IEEE Standard 802.11a-1999: Wireless LAN MAC and PHY Specification—High Speed Physical Layer in the 5 GHz Band, 2000.
[8] J.F.Wilson et al., “A single-chip VHF and UHF receiver for radio paging,” IEEE J. Solid-State Circuits, vol. 26, pp. 1944-1950, Dec. 1991.
[9] Philips Semiconductors, “Advanced pager receiver, UAA2080T,” in RF/Wireless Commun. Handbook, 1996.
[10] H.Tsurumi and T. Maeda, “Design study on a direct conversion receiver front-end for 280 MHz, 900 MHz, and 2.6 GHz band radio communication systems ,” presented at IEEE Veh.Technol. Conf., St. Louis, MO, 1991,pp.
457-462
[11] J. Wenin, “IC’s for digital cellular communication,” presented at European Solid-State Circuits Conf., UIM, Germany, 1994, pp. 1-10.
[12] G. Schultes, E. Bonek, A. L. Scholtz, and P. Kreuzgnuber,”Low cost direct conversion receiver structures for TDMA mobile communications,”
presented at sixth Int. Conf. Mobile Radio and Personal Commun., Conventry, UK, 1991, PP. 143-150
[13] A. Batemen and D. M. Haines,” Direct conversion transceiver design for compact low-cost portable mobile radio terminals,” presented at IEEE Veh. Technol. Conf., San Francisco, CA, 1989, PP. 57-62
[14] J. Smith, Modern Communication Circuits. New York: McGraw-Hill, 1986, chapter 5.
[15] R. Gomez and A. A. Abidi, “A 50 MHz Variable Gain Amplifier Cell in 2um CMOS”, Proc. IEEE 1991Custom Integrated Circuits Conf. pp 941-943, 1991
[16] Eric A. M. Klumperink, Carlo T. Klein, etc. “AM Suppression with Low AM-PM Conversion with the Aid of a Variable-Gain Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, May 1996.
[17] C. Srinivasan, K. Radhakrishna Rao, “A 20 MHz CMOS Variable Gain Amplifier”, Proceedings. Ninth International Conference on VLSI Design, pp.90-3, 1995.
[18] Ahmad Baghai Dowlatabadi and J.Alvin Connelly, “A New Offset Cancellation Technique for CMOS Differential Amplifiers”, IEEE Symposium on Circuits and Systems (Cat. No.95CH35771). IEEE. Part
vol.3, 1995, pp.2229-32 vol.3.
[19] Comino et al. “Offset Correction for a Homodyne Radio”, United States Patent, No. 5748681.
[20] Chong-Gun Yu, Randall L. Geiger, “An automatic offset Compensation Scheme with Ping-Pong Control for CMOS Operational Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 29, pp 601 - 610, May1994.
[21] James H. Atherton and H. Thomas Simmonds, “An Offset Reduction Technique for Use with CMOS Integrated Comparators and Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 27. No. 8, August 1992.
[22] Francesco Piazza, Paolo Orsatti, Qiuting Huang, Hiroyuki Miyakawa,
“A 2mA/3V 71 MHz IF Amplifier in 0.4um CMOS Programmable over 80dB Range”, ISSCC Digest of Technical Papers, pp78-79, Feb., 1997.
[23] Danilo Manstretta, Rinaldo Castello, Francesco Gatta “ A 0.18µm CMOS Direct-conversion Receiver Front-End for UMTS” IEEE ISSCC Visuals Supplement, 2002
[24] Sergio A. Sanielevici, Kenneth R.Cioffi “ A 900 MHz Transceiver Chipset for two way paging applications”, IEEE Journal of solid-state Circuits. Vol. 33, No. 12, pp. 2160-2168. December, 1998.
[25] J. Silva-Martinez, High performance CMOS continuous-time filters.
Boston, MA: Kluwer, 1992
[26] Rolf Schaumann, M.S. Ghausi “ Design of Analog Filters, Passive, Active RC, and switched Capacitor”.
[27] Krummenacher, F., and N. Joehl, “ A 4-MHZ CMOS Continuous-Time Filter with on Chip Automatic Tuning,” IEEE J. Solid-State Circuits, Vol.
SC-23 (June 1988), 750-758.
[28] Jan Crols and Michiel Steyaert, CMOS Wireless Transceiver Design, Boton: Kluwer Academic Pulishers, p. 109, 1997
[29] Won Namgoong, Tersa H.Meng,” Direct-conversion RF receiver design,” IEEE transactions on communications, vol. 49.no.3, March 2001.
[30] B.Razavi “ Design considerations for direct –conversion receivers”
IEEE transactions on circuits and systems, vol. 44,No. 6, June 1997
[31] Derek K. Shaeffer,”The Design and Implementation of Low Power CMOS Radio Receivers”, 1999.
[32] Ting-Ping Liu and Eric Westerwick, ‘ 5-GHz CMOS radio transceiver front-end chipset,”IEEE journal of solid-state circuits, vol. 35, No.12, December 2000.
[33] Lap Chi LEUNG, A 900-MHz CMOS Bandpass Amplifier for Wireless Receivers, master thesis, Hong Kong University of Science and Technology, 1999.
[34] S.-Y. Hsiao and C.-Y. Wu,”A parallel structure for CMOS four quadrant analog multipliers and its application to 2GHz RF downconversion mixer,” IEEE J. Solid-State Circuits,vol. 33 no. 6, pp. 859-869, June 1998.
[35] C-Y. Wu and H.-S. Kao, “A 1.8GHz CMOS Quadrature Voltage-Controlled Oscillator (VCO) Using the Constant-Current LC Ring Oscillator Structure,” in Proc. IEEE International Symp. On Circuits and Systems, Monterey, California, USA, May 1998, vol. 4, pp. 378-381.
[36] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “ A 900MHz CMOS LC-Oscillator with Quadrature Outputs, “in Proc. IEEE ISSCC, PP.
392-393, Feb., 1996.
[37] M. Tiebout, “Low-Power Low Phase Noises Differentially Tuned Quadrature VCO Design in Standard CMOS,”IEEE J. Solid-State Circuits, vol. 36, pp. 1018-1024, July 2001.
PUBLICATION LIST
- CONFERENCE PAPER
[1] Chung-Yu Wu, Ismail Abdel Hafez, “A low-power high dynamic range AGC for 5GHz direct conversion receivers,” in Proc. Workshop on Wireless Circuits and Systems (WoWCAS) Conference, Vancover, Canada, May 21-22, 2004.