CHAPTER 3 THE DESIGN OF THE 5GHz CMOS
3.1.3 Noise figure
RF circuits always suffer from a noise problem. Noise can be defined as random interference unrelated to the desired signal. It is a kind of unwanted signal. But unlike harmonics and intermodulation, it is not a deterministic signal. For RF circuits built on CMOS technology, there are a
few types of noise, e.g. thermal noise, shot noise, flicker noise need to be considered.
In analog circuit design, signal-to-noise ratio (SNR) and noise figure (NF) are commonly used to specify the noise performance of a system. SNR is defined as a ratio of signal power over noise power. NF is defined as a ratio of SNR at the input of a system over SNR at the output of the system, i.e. SNR=Psignal/Pnoise, NF=SNRin/SNRout
Assume a system, matched to 50-Ω impedance, has power gain of A2, and internal input referred noise of Po and it is connected to a source with source noise of Pn,s. Then the NF is:
NF=SNRin/SNRout
= (Ps,in/Pn,s) / (Ps,out/Pn,out)
=(Ps,in/Pn,s) / [Ps,in* A2/(Pn,s *A2 + Po *A2]
=1 + Po/Pn,s (3.3) The source noise, Pn,s, is referred to the thermal noise from a 50- Ω resistor, i.e. V2n,s=4kTRs∆f, where k is Boltzmann’s constant (1.38*10-23 JK-1), T is the temperature in Kelvins, and Rs is the source resistance (50 Ω), and ∆f is the bandwidth of interest. At room temperature, T=300oK, a 50 Ω resistor has a noise power of:
Pn,s/ ∆f = 10*log10(kT/1mW) = 10*log10(1.38*10-23*300/0.001) = -174dBm/ Hz.
Or in a bandwidth of 200kHz,
Pn,s= 10*log10(kT*∆f/1mW) = 10*log10(1.38*10-23*300*200*103/0.001) = -121dBm
In a system with a few stages in cascade, the overall noise figure equals to:
NF=NF1 + (NF2-1)/A2 1+(NF3-1)/(A2 1A2 2)+(NF4-1)/(A2 1A2 2A2 3) +... (3.4) Where NFi is the NF of ith stage and A2 i is the gain of ith stage. From Eq.
(3.4), an important observation can be made. NF of the first stage is directly added to the NF of the whole system. The NF of each of other stages is scaled down by the total gain of stages in front of it when referred to the overall NF. Therefore, to achieve a smaller NF of the whole system, NF1 should be as small as possible. At the same time, the gain of this stage, A21, should be as high as possible so that noise contribution from following stages can be reduced.
3.1.4 Phase noise of LO signal
In practice, the local oscillator (LO) signal is not a pure sinusoid signal. It consists of some noise at frequencies close to ωLO. This is called phase noise. The phase noise (PN) of the LO signal is defined as the ratio between the noise power in 1-Hz bandwidth at a certain offset, ∆f, and the carrier power, as shown in Fig. 3.2:
Fig. 3.2 Phase noise of LO signal
PN=10log10[(noise power in 1-Hz bandwidth)/(Carrier power)] (3.5) Because of the phase noise, the interference close to the RF frequency will generate some noise located in the signal frequency band, as shown in Fig. 3.3. Assume the signal has a bandwidth of BW and the power is Ps, and there is an interference at ∆f with a power of Pi. If the conversion gain is one, after downconversion, the interference has a similar spectrum as LO signal. The power of the noise that located within the signal bandwidth is:
Pn_dB=Pi_dB + PN + 10log10(BW) (3.6) And SUSR=Ps_dB - Pn_dB =Ps_dB - Pi_dB - PN - 10log10(BW).
To achieve enough SUSR, the PN of the LO signal should be as large as possible, and the minimum requirement is:
PN= Ps_dB - Pi_dB -10log10(BW) - SUSR. (3.7)
Fig. 3.3 SNR degradation due to phase noise of the LO signal
3.2 Design Consideration and Performance Requirements for a 5-GHz WLAN Receiver
There are presently three silicon IC technologies suitable for realizing circuits in the 5GHz frequency range. Silicon, and silicon-germanium (SiGe), bipolar devices currently provide the highest performance and enjoy the customary advantage of a high gm/I ratio, in addition to process refinements specifically intended to enhance analog and RF performance.
These latter improvements often include special resistor and capacitor operations that posses some combination of tighter tolerance, reduced parasitics, and higher Q.
A significant less expensive technology that is used here is the conventional digital CMOS. Although its inferior gm/I ratio makes CMOS circuit performance more sensitive to wiring parasitics at a given level of
power consumption than for bipolar technologies, the superior linearity of short channel MOS transistors typically confers a somewhat higher dynamic range per power than that of bipolars, and this quality is often extremely
important for wireless systems. Another noteworthy factor is the large number of interconnect layers now commonly available in CMOS logic processes. For RF applications, these additional layers are indispensable for fabrication inductors and linear capacitors of high quality.
Performance requirements for the RF signal processing blocks are quite similar for both the HiperLAN2 and 802.11a standards. This commonality should not be surprising in view of the similar frequency bands, data rates, and intended deployment scenarios. Consequently, it is possible for a single receiver design to comply with both sets of specifications.
To determine the precise target values, we first compute the specifications for both HiperLAN and 802.11a separately, and select the more stringent of the two in every case. Here we reduce the specification set to frequency range, noise figure, maximum input signal level (or input-referred 1-dB compression point), and limits on spurious emissions.
For the frequency range, it is often acceptable to cover only the lower 200MHz band. The upper 100MHz domain is not contiguous with that allocation, so its coverage would complicate somewhat the design of the
voltage controlled oscillator. Furthermore, that upper 100MHz spectrum is not universally available. Hence the choice here is to span 5.15-5.35GHz.
The worst-case noise figure requirement for HiperLAN is not directly specified, but may be readily estimated from the fact that a class C receiver must exhibit a –70dBm sensitivity over a channel bandwidth of 24MHz.
Assuming conservatively that the predetection SNR must exceed 12dB, the overall receiver noise figure must be better than:
NF= -144 dBm/Hz-12dB- (-174dBm/Hz) = 18dB
Where –174dBm/Hz is the available noise power of the source.
Strictly speaking, the required noise figure for HiperLAN2 and 802.11a receivers is a function of data rate. Since it would be cumbersome to specify individual noise figures for each possible data rate, the specification for 802.11a instead simply recommends a noise figure of 10dB, with a 5dB implementation margin, to accommodate the worst-case situation. As this target is more demanding than that of the HiperLAN2, a 10dB maximum noise figure is the design goal for the present work.
As stated previously, HiperLAN specifies –25dBm as the maximum input signal that a receiver must accommodate, whereas 802.11a specifies a value of –30dBm. Consequently, -25dBm is the target maximum input level.
Converting these specifications into a precise IIP3 target or 1-dB
compression requirement is nontrivial. However, as a conservative rule of thumb, the 1-dB compression point of the receiver should be about 4dBm above the maximum input signal power level that must be tolerated successfully. Based on this approximation, we target a worst-case input-referred 1-dB compression point of –21dBm.
Finally, the spurious emissions generated by the receiver must not exceed –57dBm for frequencies below 1GHz, and –47dBm for higher frequencies, in order to comply with FCC regulations.
The choice of the direct conversion architecture results in a host of challenges that need to be dealt with in the architectural implementation and/or in the circuit design of the blocks. Such issues include:
• DC offsets which result from self-mixing of the receive mixer as well as dc offsets which result from baseband block mismatches and the high gain of the baseband stages will result in clipping of the subsequent stages if not properly rejected [29].
• Flicker noise on the receive path can impair the SNR of the lowest index OFDM subcarriers [30]. The effect of flicker noise can be reduced by a combination of techniques. As the stages following the mixer operate at relatively low frequencies, they can incorporate very large devices to minimize the magnitude of the flicker noise. Moreover, periodic offset
cancellation also suppresses low-frequency noise components through correlated sampling.
• The receive baseband path can have potential oscillation problems due to the fact that most of the receive path gain is implemented at a single frequency (baseband).
The CMOS RF receiver circuits include low noise amplifier, down conversion mixers, voltage controlled oscillator, low pass filter, and automatic gain control circuit. Such circuits will be described in the following sections.
3.3 Low Noise Amplifier
The first block in most wireless receivers is the low-noise amplifier (LNA). Since it is the first block, the weak signal from the antenna is applied to the LNA directly. Therefore, the LNA is required to provide a high gain, otherwise the noise of subsequent stages, such as the mixer and the low pass filter, will decrease the SNR at the receiver output. However, if the gain of the LNA is too high, the linearity requirement of the following stages will be too high. Because the noise from LNA is added to the weak signal directly without any reduction of previous gain stage, the noise figure of the LNA itself must be minimized.
So the LNA is responsible for providing signal amplification while not degrading signal-to-noise ratio, and its figure sets a lower bound on the noise figure of the whole system. Of primary interest is insight into designing LNA with low noise figure, good amplification level to the input signal, and low power dissipation [31].
The schematic of the LNA is shown in Fig. 3-4. It is a differential common-source amplifier. The gate and source spiral inductors L (9nH) and Ls (2.3nH) are used with the 2pf capacitor C2 to achieve 50-Ω input impedance matching. The input transistor M1 is biased at 4 mA to attain an acceptable level of noise and gain performances. Lower power consumption could be attained at the expense of higher noise. Cascode transistor M2 enhances the amplifier reverse isolation parameter (S12), and reduces the LO leakage from the mixer back to the LNA input. The capacitor C at the output blocks the second-order intermodulation products generated in the LNA [32]. This capacitor forms with inductor L1 a network that is necessary for optimal power transfer to the next stages. The common mode rejection ratio of the LNA is 40 dB.
The input impedance of the LNA must be matched to 50 Ω, so that the signal from the antenna won’t be reflected and a maximum power transfer from antenna to LNA can be obtained. There are several topologies, which
could be used in the input matching of a LNA [33], 50-Ω resistor matching, 1/gm matching, and inductive degeneration matching. Inductive source degeneration, as shown in Fig. 3.5, can achieve a better noise figure.
V D D
M 1 M 3
M 2 M 4
L 1 L 1
V I + V I
-L L
C
C
L s L s
LB = 2 n H
V O
LB = 2 n H
C 2 C 2
Fig. 3-4 LNA schematic
Fig. 3.5 Inductive degeneration used as input matching
The input impedance looking into the matching network, Zin is:
Where Rg and Rl represent the series resistance of the on-chip inductor L and Ls, C1 is the parallel combination of C2 and Cgs. The resonant frequency is
At resonant frequency, the impedance becomes a pure resistor,
Zin(ωo) = ωT Ls + Rg +R l (3.10) The input-matching network works like a gain stage with the gain depending on the value of the capacitor C1. The smaller the capacitor gets, the larger the voltage Vgs is, and therefore, the larger the gain becomes. To reduce the noise contribution from the following stages including the input devices of the LNA, C1 is to be minimized. However, to reduce the C1 (assuming C2 is constant) the input transistors have to be small in size which results in small gm and in turn degradation in the gain and noise performance of the whole LNA. In addition, to keep the same resonant frequency, larger inductors, (L + Ls), have to be used for the small C1, which have larger resistive loss, lower Q and larger noise contribution. Consequently, careful
tradeoffs have to be made between the transistor size and the inductors to optimize the overall noise performance. In this design, the gate inductor L is set to 9nH, and source inductor is set to 2.3nH, and the Q of inductors is around 7. The size of input devices are W/L=70µ/0.18µ .
For noise analysis, the noise equivalent circuit of the LNA is shown in Fig. 3.6. Rs and vs2 are the source resistance and thermal noise from source resistance. vg2 and vl2 are the thermal noise due to loss in the gate inductor and the source inductor in the matching network. iRp2 is the thermal noise due to the loss in the output inductor. i d12, i d22, i d32 and i d42 are the thermal noise from transistors M1, M2, M3 and M4.
Fig. 3. 6 Equivalent circuit of LNA with noise sources
The transconductance of the input stage of the LNA including the matching network is:
At the resonant frequency, the imaginary part vanishes and the real part equals 2Rs.Therefore Eq. (3.11) can be revised as:
The noise factor of the LNA [33] is:
From equation Eq. (3.12), the equivalent Gm of the LNA is independent from the gm of the input device, as long as the unit gain frequency, ωT, of the device is fixed. From equation Eq. (3.13), the output noise due the source noise is also independent from the gm of the input devices for a fixed unit-gain frequency, ωT. Therefore, the best method to improve the noise performance of the LNA is to increase the unit-gain frequency, ωT, of the input devices by increasing the bias current of the input
devices or reducing the Cgs of input devices. However, a smaller Cgs needs a larger L to maintain the same resonant frequency, and a larger L will have more loss and cause more noise. Therefore, a trade-off must be made between L and Cgs to optimize the NF of the LNA.
The component values and channel dimensions of the MOS devices of Fig. 3-4 are summarized in Table III.
Devices Value
M1, M3 70
µm/ 0.18
µmM2, M4 60/
µm/ 0.18
µmL, L
S, L1 9nH, 2.3nH, 2.3nH respectively
C2 2pF C 2pF
Table III Component values and dimensions of MOS devices of the LNA.
3.4 Quadrature Down Conversion Mixer
In the RF mixers, the important design parameters are noise figure (NF), conversion gain (CG), third-order input intercept point (IIP3), and port
-to-port isolation. These parameters should be designed to meet the requirements of various standards for different wireless communication systems.
In this design, the mixer is intended to be used as the RF downconversion block in the wireless receiver shown in Fig. 1-1. As seen from that Figure, the mixer is placed after the low noise amplifier (LNA).
The LNA provides sufficient power gain to mask the noise contribution of the subsequent stages. Thus the noise figure contributed by the mixer can be ignored if its value is lower than the total gain of the previous stages.
Since the LNA has provided sufficient gain, the conversion gain of the mixer should not be high to overdrive the subsequent stages. Higher gain also implies higher signal swing in the circuit, which could degrade the linearity and the dynamic range. Nevertheless, very low gain far below 0dB is also unacceptable because the noise contributed by the stages after the mixer becomes higher. Thus the value of conversion gain around 0dB is acceptable.
In the modern wireless systems, the receiver could subject to an environment with large adjacent channel interfering signals. Due to the nonlinearity of the receiver, those interfering signals produce co-channel interference, which degrades the signal-to-noise-ratio of the received signal.
Thus IIP3 of the receiver, which indicates the ability of the receiver to reject the interfering signals becomes a very important feature of the RF receiver.
In most cases, the signal power handled by the RF mixer is higher than those by the other stages in the receiver. Thus IIP3 of the mixer is a critical parameter in the receiver design. In order to sustain a high receiver linearity, IIP3 of the mixer should be as high as possible.
The port to port isolation and LO power are also important issues in the mixer design. The LO power in the order of a few dBm is often required by the mixer to obtain high linearity and high dynamic range. Such a high LO power causes the LO energy leaks through the RF port and radiates from the antenna if the port isolation of the mixer is not high enough. The design criteria of the mixer is to keep the LO power as low as possible and increases the port isolation.
LTI system cannot provide outputs with spectral components not present at input. So, mixer must be either nonlinear or time varying in order to provide frequency translation. Mixer performs frequency translation by multiplying two signals (with their harmonics) in time domain.
Since the MOS transistor is basically a square-law device, then it can be used to implement second-order transfer functions [34]. In this receiver, the utilized mixer is a quadrature one, and Fig. 3-7 shows the circuit diagram
of the in-phase output of the mixer. In this circuit, type-A combiner consists of eight transistors (M9~M16), while type-B combiner consists of four transistors (M17~M20]. The transfer function of the two combiners can be modeled by the drain current equation of the MOS transistors in the saturation region. Using the ideal square law current identity of MOS transistors, the drain current ID can be expressed as
ID = K (VGS – VT) 2 (3.14) Where K= µs (Cox/2)(W/L) is the transconductance parameter, µs is the effective surface carrier mobility, Cox is the gate oxide capacitance per unit area, W/L is the channel width (length) of the MOS device, VGS is the gate-source voltage, and VT is the threshold voltage.
If the transistors in the type-A combiner are operated in the saturation region, the output voltage at the their drains terminals can be written as functions of the input signals LOQ+, LOQ-, RF+, and RF- by using (3.14).
The same thing can be done for the B-type combiner.
The supply voltage of the mixers can be as low as 1.8V, since only two transistors are cascaded between power supply and ground. By the way, the down-conversion mixers and VCO share the same current and so the power consumption will be reduced obviously. In comparison with other architectures, the current- reused method, as shown in Fig. 3-8, particularly
highlights the advantages of the low-power consumption in direct
Fig. 3-7 In phase output of the down conversion mixer
Fig. 3-8 The concept of current reuse technique in the receiver
3.5 Merged Quadrature Voltage Controlled Oscillator
Fig. 3-9 The conceptual block diagram of the voltage controlled oscillator
To implement the integrated quadrature VCO, a circuit structure based on the two-stage ring oscillator with LC-tank loads is proposed [35]. As shown in Fig 3-9 two fully differential narrow-band LC-tuned inverters are connected to form a two-stage ring oscillator structure for signal oscillation.
The output waveforms at the differential output nodes of one inverter are 90° out of phase from those at the differential output nodes of the other one.
Thus, these two differential output waveforms are synchronized in
quadrature phases [35]-[37]. When the delay time of the two fully differential inverters are kept the same at oscillation, the outputs of these two fully differential inverters can provide highly accurate quadraturesignals. By incorporating the LC-tank loads into two-stage ring oscillator, the performance of proposed quadrature VCO is significantly improved with respect to the following specifications: phase noise, frequency stability, and supply voltage sensitivities.
In order to efficiently reduce chip area, power dissipation, and
In order to efficiently reduce chip area, power dissipation, and