CHAPTER 2 THE DESIGN OF THE AUTOMATIC
2.5 Simulation Results
The variation of the gain of the four-cascaded VGAs versus the control voltage is shown in Fig. 2-15. The relation is almost linear. The gain changes from –10dB to 56dB as the control voltage changes from 0V to 2V.
To reject dc offsets which would result from self-mixing of the mixers or receiver baseband mismatches, and result in clipping of the subsequent stages if not properly removed, some form of a high pass filter would have to be used. In this design, there are four variable gain amplifiers distributed in the receive path. The poles of these high pass amplifiers cannot be too low, as they would result in long transient settling during gain changes. On the other hand, poles cannot be placed too high since this will attenuate the lowest OFDM subcarriers (located at 312KHz) and thus system performance through degrading its signal-to-noise ratio. In this design, the poles are placed at 106KHz. For OFDM modulated signals; which has 52 subcarriers;
the lowest subcarriers are located at ±312KHz, and the highest subcarriers are at ±8.125MHz, so none of the subcarriers are attenuated by the filter in the receive chain. The frequency response of the four VGAs that comply with the above requirements is shown in Fig.2-16. The bandwidth of the VGA is slightly above 20MHz, to compensate for the parasitic capacitor of the high pass filter which will in turn decreases the bandwidth.
Fig. 2-15 The gain turning curve of the four-cascaded VGAs
Fig. 2-16 Frequency response of the four-cascaded VGAs.
Variation of the cascaded four VGAs gain and THD with input power is shown in Fig. 2-17. The gain reaches the maximum when the input signal is around –60dBm. If the required THD must be larger than 15dBc, then the dynamic range of the AGC is 43dB. The main advantage of the utilized AGC is that it offers continuous control of the received signal rather than discrete one. The noise figure of the AGC circuit was measured to be 7dB,which means that the increase of the receiver’s noise figure due to AGC will be acceptable.
Figure. 2-17 Variation of the cascaded VGAs gain and THD with input power.
The waveforms at the outputs of the I, and Q peak detectors are shown in Fig. 2-18. The Figure shows also the summation of these waveforms that will be applied to the input of the loop filter.
Figure. 2-18. I and Q peak detector outputs and their summation
To measure the stop band loss of the VGA and LPF, two tones were inserted at the VGA input; one with frequency of 5MHz, and the other with 25 MHz, as shown in Fig.2-19. The 5MHz tone was amplified by 37 dB, while the 25MHz one was attenuated by 17 dB. So the stop band loss is 54 dB. The frequency response of the elliptic sixth-order low pass filter is shown in Fig.2-20. Its cutoff frequency is 10MHz.
Table II summarizes the simulation results of the AGC and low pass filter.
(a)
(b)
Figure. 2-19 (a) Amplification of a 5MHz tone.
(b) Attenuation of a 25MHz tone.
Figure. 2-20 Frequency response of the LPF
Fig. 2.21 shows the gain of the VGA as a function of offset voltage. An input signal of -60dBm at 5 MHz is applied to the VGA input together with a DC offset voltage. As the offset voltage varies around the zero, the gain of the VGA also varies. Without offset cancellation, the gain is very sensitive to the input offset voltage. Even an offset voltage as small as 0.5 mV at the input will be amplified by the VGA to more than 0.5 V, and the operation point of the VGA will be shifted far away from the optimum value, which results in a significant drop of the gain. However, with offset cancellation, the offset voltage at input is not amplified and has little effect on the operation point, and as a result, the gain of the VGA is quite insensitive to the input offset voltage.
Fig. 2.21 VGA gain variation due to offset voltage (a) With offset cancellation
(b) Without offset cancellation
Performance Hspice simulation results
AGC passband range 106KHz~20MHz
AGC voltage gain -10~56dB
AGC noise figure 7dB
AGC dynamic range 60dB
LPF cutoff frequency 10MHz
LPF power consumption 14mW
LPF harmonic distortion 40dB
AGC Power consumption 11 m W
Table II Simulated AGC & LPF performance
Chapter 3
THE DESIGN OF THE 5GHz DIRECT CONVERSION RECEIVER
3.1 Receiver Fundamentals
In this section, some fundamental issues concerning direct conversion receivers front-ends are discussed, e.g. sensitivity, nonlinearity, noise figure, and phase noise.
Wireless products, e.g. mobile phones, pagers, wireless local-area-network (LAN) etc., usually consist of several basic blocks including transceiver front-ends and base-band back-ends. A transceiver front-end is a combination of a receiver front-end and a transmitter front-end. A receiver front-end converts a received radio frequency (RF) signal from an antenna into a baseband signal and a transmitter front-end converts a baseband signal into an RF signal and sends it to an antenna. In the receiver, the conversion is done by a few of frequency domain operations including downconversion, filtering and amplification. The frequency domain operation is realized in physical building blocks including LNA, mixers, and synthesizer. Those building blocks are not perfect. Besides the wanted frequency domain operation, unwanted operations are also performed. Those unwanted
operations include adding noise to the signal and distorting the signal.
Therefore the performance of a receiver is limited.
The performance of a receiver is defined as the output signal-to-unwanted-signal ratio (SUSR). This ratio is taken at its output, before demodulation and after analog-to-digital (A/D) conversion.
3.1.1 Sensitivity
The sensitivity is a measure of receiver performance. Although the performance of a wireless communication system is often specified in terms of the bit error rate (BER), the frame error rate (FER) and the residual bit error rate (RBER), those specifications are very impractical for the receiver front-end design. As a receiver front-end can only be evaluated by adding unwanted signals, such as noise, image signals and intermodulation signals, to the wanted signal, the performance can therefore be translated into the specification of signal-to-unwanted-signal ratio (SUSR), which can also be called as signal-to-noise ratio (SNR), if all unwanted signals are treated as kinds of noise. An approximate value for this SUSR can be found by means of BER simulations. For the 802.11a WLAN system, the required SUSR is 10dB. The sensitivity of a receiver is defined as the minimum signal power at the input of the receiver when a minimum SUSR of 10dB is achieved at
the output of the receiver. In the proposed application, a sensitivity of – 82dBm at a data rate of 6Mb/s, and a sensitivity of –65dBm at 54Mb/s is required.
3.1.2 Linearity
Many RF and analog circuits can be approximated with a linear model to obtain their response to small signals. Nonlinearity often leads to interesting and important phenomena. For simplicity, a nonlinear system can be modeled as follows:
y(t) ≈ α1 x(t) + α2 x2(t) + α3 x3(t) (3.1) Higher orders are assumed to have much smaller gain and are therefore ignored.
Nonlinearity of analog circuits will cause problems of harmonics, gain compression, desensitization, intermodulation, etc. [28]. Intermodulation is commonly used as a measure of linearity of a circuit. Two-tone test is usually used to measure the intermodulation of a circuit. As shown in Fig.
3.1, the amplitude of the input signal is swept from small power to large power. The output signals are measured at both the fundamental frequency, ω1 or ω2, and the IM3 frequency, 2ω1 - ω2 or 2ω2 - ω1. Two curves can be plotted in log-scale based on the measured amplitude of both fundamental
and IM3 components. There is an intersection point if the two lines are extrapolated. This point is called third interception point (IP3). Input referred IP3 (IIP3) is often used to specify the linearity of a system.
Fig. 3.1 Two-tone test of a nonlinear system
In a system with cascading of several stages, the IIP3 of the system, A2 IP3, can be expressed as:
Where A2 IP3,I is the IIP3 of ith stage and α21, β21,... are gain of each stage.
3.1.3 Noise figure
RF circuits always suffer from a noise problem. Noise can be defined as random interference unrelated to the desired signal. It is a kind of unwanted signal. But unlike harmonics and intermodulation, it is not a deterministic signal. For RF circuits built on CMOS technology, there are a
few types of noise, e.g. thermal noise, shot noise, flicker noise need to be considered.
In analog circuit design, signal-to-noise ratio (SNR) and noise figure (NF) are commonly used to specify the noise performance of a system. SNR is defined as a ratio of signal power over noise power. NF is defined as a ratio of SNR at the input of a system over SNR at the output of the system, i.e. SNR=Psignal/Pnoise, NF=SNRin/SNRout
Assume a system, matched to 50-Ω impedance, has power gain of A2, and internal input referred noise of Po and it is connected to a source with source noise of Pn,s. Then the NF is:
NF=SNRin/SNRout
= (Ps,in/Pn,s) / (Ps,out/Pn,out)
=(Ps,in/Pn,s) / [Ps,in* A2/(Pn,s *A2 + Po *A2]
=1 + Po/Pn,s (3.3) The source noise, Pn,s, is referred to the thermal noise from a 50- Ω resistor, i.e. V2n,s=4kTRs∆f, where k is Boltzmann’s constant (1.38*10-23 JK-1), T is the temperature in Kelvins, and Rs is the source resistance (50 Ω), and ∆f is the bandwidth of interest. At room temperature, T=300oK, a 50 Ω resistor has a noise power of:
Pn,s/ ∆f = 10*log10(kT/1mW) = 10*log10(1.38*10-23*300/0.001) = -174dBm/ Hz.
Or in a bandwidth of 200kHz,
Pn,s= 10*log10(kT*∆f/1mW) = 10*log10(1.38*10-23*300*200*103/0.001) = -121dBm
In a system with a few stages in cascade, the overall noise figure equals to:
NF=NF1 + (NF2-1)/A2 1+(NF3-1)/(A2 1A2 2)+(NF4-1)/(A2 1A2 2A2 3) +... (3.4) Where NFi is the NF of ith stage and A2 i is the gain of ith stage. From Eq.
(3.4), an important observation can be made. NF of the first stage is directly added to the NF of the whole system. The NF of each of other stages is scaled down by the total gain of stages in front of it when referred to the overall NF. Therefore, to achieve a smaller NF of the whole system, NF1 should be as small as possible. At the same time, the gain of this stage, A21, should be as high as possible so that noise contribution from following stages can be reduced.
3.1.4 Phase noise of LO signal
In practice, the local oscillator (LO) signal is not a pure sinusoid signal. It consists of some noise at frequencies close to ωLO. This is called phase noise. The phase noise (PN) of the LO signal is defined as the ratio between the noise power in 1-Hz bandwidth at a certain offset, ∆f, and the carrier power, as shown in Fig. 3.2:
Fig. 3.2 Phase noise of LO signal
PN=10log10[(noise power in 1-Hz bandwidth)/(Carrier power)] (3.5) Because of the phase noise, the interference close to the RF frequency will generate some noise located in the signal frequency band, as shown in Fig. 3.3. Assume the signal has a bandwidth of BW and the power is Ps, and there is an interference at ∆f with a power of Pi. If the conversion gain is one, after downconversion, the interference has a similar spectrum as LO signal. The power of the noise that located within the signal bandwidth is:
Pn_dB=Pi_dB + PN + 10log10(BW) (3.6) And SUSR=Ps_dB - Pn_dB =Ps_dB - Pi_dB - PN - 10log10(BW).
To achieve enough SUSR, the PN of the LO signal should be as large as possible, and the minimum requirement is:
PN= Ps_dB - Pi_dB -10log10(BW) - SUSR. (3.7)
Fig. 3.3 SNR degradation due to phase noise of the LO signal
3.2 Design Consideration and Performance Requirements for a 5-GHz WLAN Receiver
There are presently three silicon IC technologies suitable for realizing circuits in the 5GHz frequency range. Silicon, and silicon-germanium (SiGe), bipolar devices currently provide the highest performance and enjoy the customary advantage of a high gm/I ratio, in addition to process refinements specifically intended to enhance analog and RF performance.
These latter improvements often include special resistor and capacitor operations that posses some combination of tighter tolerance, reduced parasitics, and higher Q.
A significant less expensive technology that is used here is the conventional digital CMOS. Although its inferior gm/I ratio makes CMOS circuit performance more sensitive to wiring parasitics at a given level of
power consumption than for bipolar technologies, the superior linearity of short channel MOS transistors typically confers a somewhat higher dynamic range per power than that of bipolars, and this quality is often extremely
important for wireless systems. Another noteworthy factor is the large number of interconnect layers now commonly available in CMOS logic processes. For RF applications, these additional layers are indispensable for fabrication inductors and linear capacitors of high quality.
Performance requirements for the RF signal processing blocks are quite similar for both the HiperLAN2 and 802.11a standards. This commonality should not be surprising in view of the similar frequency bands, data rates, and intended deployment scenarios. Consequently, it is possible for a single receiver design to comply with both sets of specifications.
To determine the precise target values, we first compute the specifications for both HiperLAN and 802.11a separately, and select the more stringent of the two in every case. Here we reduce the specification set to frequency range, noise figure, maximum input signal level (or input-referred 1-dB compression point), and limits on spurious emissions.
For the frequency range, it is often acceptable to cover only the lower 200MHz band. The upper 100MHz domain is not contiguous with that allocation, so its coverage would complicate somewhat the design of the
voltage controlled oscillator. Furthermore, that upper 100MHz spectrum is not universally available. Hence the choice here is to span 5.15-5.35GHz.
The worst-case noise figure requirement for HiperLAN is not directly specified, but may be readily estimated from the fact that a class C receiver must exhibit a –70dBm sensitivity over a channel bandwidth of 24MHz.
Assuming conservatively that the predetection SNR must exceed 12dB, the overall receiver noise figure must be better than:
NF= -144 dBm/Hz-12dB- (-174dBm/Hz) = 18dB
Where –174dBm/Hz is the available noise power of the source.
Strictly speaking, the required noise figure for HiperLAN2 and 802.11a receivers is a function of data rate. Since it would be cumbersome to specify individual noise figures for each possible data rate, the specification for 802.11a instead simply recommends a noise figure of 10dB, with a 5dB implementation margin, to accommodate the worst-case situation. As this target is more demanding than that of the HiperLAN2, a 10dB maximum noise figure is the design goal for the present work.
As stated previously, HiperLAN specifies –25dBm as the maximum input signal that a receiver must accommodate, whereas 802.11a specifies a value of –30dBm. Consequently, -25dBm is the target maximum input level.
Converting these specifications into a precise IIP3 target or 1-dB
compression requirement is nontrivial. However, as a conservative rule of thumb, the 1-dB compression point of the receiver should be about 4dBm above the maximum input signal power level that must be tolerated successfully. Based on this approximation, we target a worst-case input-referred 1-dB compression point of –21dBm.
Finally, the spurious emissions generated by the receiver must not exceed –57dBm for frequencies below 1GHz, and –47dBm for higher frequencies, in order to comply with FCC regulations.
The choice of the direct conversion architecture results in a host of challenges that need to be dealt with in the architectural implementation and/or in the circuit design of the blocks. Such issues include:
• DC offsets which result from self-mixing of the receive mixer as well as dc offsets which result from baseband block mismatches and the high gain of the baseband stages will result in clipping of the subsequent stages if not properly rejected [29].
• Flicker noise on the receive path can impair the SNR of the lowest index OFDM subcarriers [30]. The effect of flicker noise can be reduced by a combination of techniques. As the stages following the mixer operate at relatively low frequencies, they can incorporate very large devices to minimize the magnitude of the flicker noise. Moreover, periodic offset
cancellation also suppresses low-frequency noise components through correlated sampling.
• The receive baseband path can have potential oscillation problems due to the fact that most of the receive path gain is implemented at a single frequency (baseband).
The CMOS RF receiver circuits include low noise amplifier, down conversion mixers, voltage controlled oscillator, low pass filter, and automatic gain control circuit. Such circuits will be described in the following sections.
3.3 Low Noise Amplifier
The first block in most wireless receivers is the low-noise amplifier (LNA). Since it is the first block, the weak signal from the antenna is applied to the LNA directly. Therefore, the LNA is required to provide a high gain, otherwise the noise of subsequent stages, such as the mixer and the low pass filter, will decrease the SNR at the receiver output. However, if the gain of the LNA is too high, the linearity requirement of the following stages will be too high. Because the noise from LNA is added to the weak signal directly without any reduction of previous gain stage, the noise figure of the LNA itself must be minimized.
So the LNA is responsible for providing signal amplification while not degrading signal-to-noise ratio, and its figure sets a lower bound on the noise figure of the whole system. Of primary interest is insight into designing LNA with low noise figure, good amplification level to the input signal, and low power dissipation [31].
The schematic of the LNA is shown in Fig. 3-4. It is a differential common-source amplifier. The gate and source spiral inductors L (9nH) and Ls (2.3nH) are used with the 2pf capacitor C2 to achieve 50-Ω input impedance matching. The input transistor M1 is biased at 4 mA to attain an acceptable level of noise and gain performances. Lower power consumption could be attained at the expense of higher noise. Cascode transistor M2 enhances the amplifier reverse isolation parameter (S12), and reduces the LO leakage from the mixer back to the LNA input. The capacitor C at the output blocks the second-order intermodulation products generated in the LNA [32]. This capacitor forms with inductor L1 a network that is necessary for optimal power transfer to the next stages. The common mode rejection ratio of the LNA is 40 dB.
The input impedance of the LNA must be matched to 50 Ω, so that the signal from the antenna won’t be reflected and a maximum power transfer from antenna to LNA can be obtained. There are several topologies, which
could be used in the input matching of a LNA [33], 50-Ω resistor matching, 1/gm matching, and inductive degeneration matching. Inductive source degeneration, as shown in Fig. 3.5, can achieve a better noise figure.
V D D
M 1 M 3
M 2 M 4
L 1 L 1
V I + V I
-L L
C
C
L s L s
LB = 2 n H
V O
LB = 2 n H
C 2 C 2
Fig. 3-4 LNA schematic
Fig. 3.5 Inductive degeneration used as input matching
The input impedance looking into the matching network, Zin is:
Where Rg and Rl represent the series resistance of the on-chip inductor L and Ls, C1 is the parallel combination of C2 and Cgs. The resonant frequency is
At resonant frequency, the impedance becomes a pure resistor,
Zin(ωo) = ωT Ls + Rg +R l (3.10) The input-matching network works like a gain stage with the gain depending on the value of the capacitor C1. The smaller the capacitor gets, the larger the voltage Vgs is, and therefore, the larger the gain becomes. To
Zin(ωo) = ωT Ls + Rg +R l (3.10) The input-matching network works like a gain stage with the gain depending on the value of the capacitor C1. The smaller the capacitor gets, the larger the voltage Vgs is, and therefore, the larger the gain becomes. To