Chapter 1 Introduction
1.6 Organization of the Dissertation
Six chapters are contained in this dissertation. Background and motivation are described in Chapter 1. Chapter 2 discusses the device structure, fabrication process, and basic electrical characteristics of the main device architecture proposed in this study.
Source/drain engineering for performance enhancement is investigated and analyzed in Chapter 3. Study on the transport behavior at cryogenic ambient is conducted in Chapter 4. Chapter 5 details the merits offered by independent double-gated configuration in SONOS memory devices. In Chapter 6, major achievements and summary are stated, and suggested future works are listed. The following specifies the detailed content of each chapter.
In Chapter 1, overview of NW technology and multiple-gated devices are mentioned along with a brief description of NW transport properties and nonvolatile memory technology. As noted in the motivation, to deal with some dilemma of NW fabrication process and to optimize the structure of our previously reported device, a novel independent double-gated poly-Si NW transistor with rectangular channels is thus proposed.
Chapter 2 elucidates the structure and fabrication process of the proposed poly-Si NW devices. An isotropic and selective plasma etching technique is explored to form a
rectangular-shaped NW. Subsequently, impacts of different operation modes associated with the double-gated configuration on device performance are discussed followed by the examination of the root cause for the size dependency, which is found to be intimately linked to the capability of the gates in adjusting the magnitude of grain boundary barrier height.
In Chapter 3, source/drain engineering is investigated to enhance device performance. Replacing ion implantation with in-situ doping for the formation of source/drain regions, it is demonstrated that the overall electrical characteristics are clearly improved and a record-breaking 73 mV/dec subthreshold swing is achieved.
In Chapter 4, to probe the underlying transport properties, devices with channel lengths ranging from 39 nm to 5 μm are fabricated and characterized under cryogenic ambient. A very intriguing abrupt switching phenomenon is observed when the device is operated under one of the two single-gated modes. In addition, this behavior shows a strong dependency on the channel length that is in obvious conflict with the conventional theory concerning SCE as the subthreshold current is reduced with shorter channel length. A simple model based on the barrier formation near the source/drain due to non-uniform gate doping is proposed to explain this phenomenon.
In Chapter 5, the influence of independent double-gated configuration on SONOS type nonvolatile memory applications is discussed. In contrast to the convention where
the programming/erasing gate also acts as the read gate, a dedicated read gate with oxide-only dielectric is proposed in the new mode. Greatly improved programming speed is achieved while the erasing speed, albeit initially retarded, shows enhancement when the erasing time is larger than a certain value. Retention characterization indicates that this new read mode offers a larger memory window after 10-year extrapolation. In addition, a proper auxiliary gate bias applied during programming/erasing processes is found to improve the programming/erasing speed. Finally, by taking advantage of the separate-gated feature, 2-bit/cell functionality is realized as well.
Chapter 6 summarizes the results and contributions made in this dissertation and provides suggested items for future works.
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Table 1-I Comparison of selected NW transistors with sub-20 nm channel length.
Ref 1-16 1-27 1-28 1-29 1-15
NW diameter (nm) 10 8 10 16 W/H=14/12
Gate structure omega GAA GAA GAA Tri-gate
L (nm) 5 15 8 10 3.8
Normalization method diameter diameter diameter perimeter perimeter
ION (μA/μm) 115 1940 3740 1494 976
ION/IOFF >105 >105 >107 >105 >104
DIBL (mV/V) 14 43 22 88 148
SS (mV/dec) 63 71 75 89 92
VDD (V) -1 -1 1.2 1 1
Microscopic image
Chapter 2
Double-Gated Poly-Si Thin Film Transistor with Twin Nanowire Channels
2.1 Introduction
Acting as an important building block in drivers of liquid crystal display (LCD), polycrystalline-Si (poly-Si) thin-film transistors (TFTs) have become very attractive for future 3-D electronics integration [2-1]. Compared with single-crystalline Si-based microelectronics where expensive substrates are inevitable, high performance TFTs have emerged as a promising alternative for macroelectronics employing glass and plastic substrates where flexibility and light weight are primarily preferred [2-2]. It would be quite a breakthrough if poly-Si TFTs could display comparable performance to single-crystalline Si-based devices on account of its low fabrication cost. However, the granular structure inherent in poly-Si significantly degrades the carrier mobility [2-3]
and limits its adoption and proliferation in advanced very large scale integration (VLSI) technologies. To address this intrinsic material issue, a plethora of recrystallization methods for grain enlargement have been proposed, with solid-phase crystallization (SPC) [2-4], metal-induced lateral crystallization (MILC) [2-5], and excimer laser annealing (ELA) [2-6] being the most commonly used. To continue the scaling trend
while simultaneously improving poly-Si device characteristics, such extrinsic modification as ultra-thin body structures provides an effective solution for the aforementioned problem. From a microscopic perspective, one-dimensional nanowire (NW) structure also offers a unique platform for physical properties not easily observed in conventional devices. The unique characteristics of large surface-to-volume ratio and high sensitivity to surface conditions have rendered NW a functional device suitable for bio-sensing [2-7] and nonvolatile memory [2-8] applications.
Among the various methods for NW fabrication, top-down approaches avoid the misalignment and hard-to-manipulate issues frequently encountered in bottom-up processes, and meanwhile are more compatible with modern CMOS process flow.
Moreover, when combined with multiple-gated scheme, the fabricated device exhibits enhanced drive current and steeper subthreshold swing due to improved control of electrostatic potential in the channel, as demonstrated in various works, including FinFET [2-9], omega-gate [2-10], tri-gate [2-11], and gate-all-around [2-12], etc.
Meanwhile, CMOS-compatible performance has also been achieved using poly-Si NW devices [2-13][2-14]. To this end, we had presented several innovative top-down approaches for forming poly-Si NWs using conventional I-line based lithography [2-15]-[2-17]. The NW channels were formed by the sidewall spacer etching technique and for the independent double-gated structure in [2-17], the NW channels were
surrounded by an inverse-T-shaped gate and a top gate. This kind of scheme has been shown to dramatically enhance the device performance under double-gated operation and provides more flexibility in device operation [2-18]. However, the cross-sectional shape of NW channels was triangular, which is irregular, and may lead to non-uniform carrier distribution inside the nanowire, making accurate theoretical modeling extremely difficult to perform. In view of this, a device with more regularly shaped NWs is highly demanded and in this study we propose a novel technique of forming rectangular NWs by adopting selective plasma etching.
In this chapter, the condition for isotropic plasma etching of poly-Si with high selectivity and controllable etching rate is first discussed. Then, based on the optimized condition, independent double-gated poly-Si NW TFTs with various NW dimensions are fabricated and characterized.
2.2 Experimental
Since we aim to fabricate a poly-Si NW transistor by forming a cavity at two sides of a nitride/poly-Si/nitride stack through selective etching of the sandwiched poly-Si followed by refilling with the active layer, in this section we would like to discuss some of the critical parameters that should be carefully adjusted. Subsequently, device fabrication process and measurement setup will be briefly mentioned.
2.2.1 Investigation of Selective Plasma Etching Conditions
The main feature in this structure lies in the fact that a sub-100 nm cavity could be formed by isotropic plasma etching using a high density plasma (HDP) etching apparatus. In this dissertation a transformer coupled plasma (TCP) reactor with model number TCP 9400 manufactured by Lam Research was used, which operates by inductively coupling RF power to plasma. This tool is equipped with two RF power generators. The top source RF power generates plasma and determines ion density, while the bottom bias RF power is responsible for controlling the ion bombardment energy. In other words, ion density and energy are independently controlled in this reactor, thus solving the inflexibility and poor efficiency of conventional capacitively-coupled reactors. In contrast to the typical anisotropic reactive-ion-etching
The main feature in this structure lies in the fact that a sub-100 nm cavity could be formed by isotropic plasma etching using a high density plasma (HDP) etching apparatus. In this dissertation a transformer coupled plasma (TCP) reactor with model number TCP 9400 manufactured by Lam Research was used, which operates by inductively coupling RF power to plasma. This tool is equipped with two RF power generators. The top source RF power generates plasma and determines ion density, while the bottom bias RF power is responsible for controlling the ion bombardment energy. In other words, ion density and energy are independently controlled in this reactor, thus solving the inflexibility and poor efficiency of conventional capacitively-coupled reactors. In contrast to the typical anisotropic reactive-ion-etching