Dependency of Performance Enhancement in Double-Gated over

Double-Gated over Single-Gated Operation on Nanowire Channel Dimension

To probe the impact of NW dimension, Figs. 2-13 (a) and (b) illustrate transfer curves for devices with 43- and 52-nm-thick NW channels, respectively. Evidently, for the 43-nm case, the enhancement from DG mode is still visible but the extent is smaller than that of the previous 18-nm one. On the other hand, when NW is widened to 52-nm, it comes as a surprise because no observable merit is obtained under multiple-gated operation since ID-VG characteristics for DG and SG-2 mode are essentially identical.

Before further in-depth investigation of the root cause for this size-dependent effect, additional information can be gained from other aspects.

First, GM enhancement is examined. Similar to the drain current ratio, GM ratio can

be defined as the GM (with respect to gate overdrive) under DG mode divided by the sum of that under SG-1 and SG-2 modes. As shown in Fig. 2-14, the peak of GM ratio is observed to be larger when NW size is smaller. For the device with 52-nm NW, the maximum ratio is only slightly larger than unity, implying that even under DG operation, the 1^st and 2^nd gates still control the channel in a rather independent way and the NW channel is only partially depleted in this case. On the contrary, the maximum ratio for 18-nm NW is seen to reach 2.4. From another viewpoint in terms of parasitic resistance, the total resistance is extracted in Fig. 2-15. S/D series resistance can thereby be determined based on the method in [2-26], in which a first order exponential curve fitting was adopted. Actually, under DG mode, the two conduction paths governed by 1^st and 2^nd gates can be conceived as flowing in parallel. Thus, for the simplest condition when two gates work independently, the S/D series resistance of DG mode (RDG) should be approximately equal to the equivalent resistance (REQ) of two single-gated modes. To obtain REQ, the drain current as a function of the gate voltage under SG-1 and SG-2 modes is first summed up followed by employing the fitting method in [2-26] to determine REQ. The extraction procedures (only the 18-nm NW case) are shown in Fig.

2-15 and the results for devices with three different NW thicknesses displayed in Fig.

2-16 (a). The smaller S/D series resistance under DG mode as compared with SG modes can be partly ascribed to the larger conduction area between channels and S/D provided

by DG mode, which helps reduce the spreading resistance. The ratio of the difference between REQ and RDG to REQ is given in Fig. 2-16 (b). For DG mode of operation, it can be seen that the 18-nm, 43-nm, and 52-nm NW give 45 %, 35 %, and 17 % reduction in terms of S/D resistance improvement, respectively. It is noteworthy that the technique utilized here cannot provide very accurate determination of the S/D resistance under SG modes because the approach in [2-26] was based on a tie-gated device without the need to consider the body effect. This is apparently not the case in our device where the drain current under SG modes is intimately related to the applied bias of the auxiliary gate.

However, even when normalization of the VTH is undertaken as shown in the output curves in Fig. 2-12, DG mode is still able to offer larger output current than SG-1 and SG-2 modes combined, and therefore it justifies the methodology used in Fig. 2-15 though the data presented is only a rough estimate.

As another indicator of gate controllability, the extracted SS as a function of NW thickness is plotted in Fig. 2-17 where SS is observed to decrease with reduced NW thickness for all three modes. The above size dependency, in fact, has been treated in both fully-depleted double-gated SOI [2-27][2-28] and poly-Si devices [2-29]. For single-crystalline devices, more rapid variation of surface potential triggered by the larger vertical electric field induced in devices with smaller NW thickness leads to better short channel effects immunity as the NW dimension is reduced. However, in

poly-Si based devices, potential barriers present in the grain boundaries are another major factor that needs to be accounted for so as to correctly interpret our results. This subject was recently treated in [2-23] where the origin of performance enhancement of a double-gated poly-Si NW transistor was investigated. And it was found that the major reason for the performance improvement under DG mode over SG modes stemmed from the different modulation capability of grain boundary barrier heights. To this end, using the similar analysis technique, the barrier height of grain boundary as a function of the gate voltage for three operation modes is shown in Fig. 2-18. Based on [2-30], the barrier height is extracted by using transfer curves measured at two different temperatures. Thanks to the increase of inversion carriers, the barrier height is monotonically made smaller with increasing VG- VTH. At strong inversion, the barrier of DG mode is the lowest among the three modes, demonstrating the merit of multiple-gated configuration in providing improved mobility and ION over SG modes.

Another insight can be gained from the comparison of barrier height reduction capability under DG mode as a function of NW thickness, as shown in Fig. 2-19. The respective barrier height at VG- VTH of 3 V for 18-nm, 43-nm, and 52-nm NW is 12 mV, 30 mV, and 76 mV. It is obvious that there exists a very strong size dependency in terms of the barrier height reduction rate. The rate at which the barrier is lowered determines how fast the drain current is increased as the gate voltage is enlarged, which in turn

defines SS. For the thinnest device, the gate-to-gate coupling effect is the most intense so that under DG mode the barrier can be very effectively lowered by the gate voltage, as evidenced in Fig. 2-19. As for the thickest case, there is very weak gate coupling effect and Fig. 2-18 (c) exhibits that even under DG mode the barrier height is still reduced in a similar rate as that of SG-2 mode. Hence, it becomes reasonable that the SS is reduced with thinner NW under DG mode.

Now that the detailed origin for the performance enhancement is clarified, the trend in Fig. 2-12 that shows reduced peak ratio with increased gate overdrive can be easily understood. As explained in the previous sub-section, the larger-than-unity drain current ratio is associated with the early saturation effect that occurs exclusively in SG modes, which only suffices to explain the reason that the peak ratio saturates beyond the drain voltage equal to the corresponding gate overdrive. Another prominent factor leading to the difference in output current of DG and SG modes should be their respective mobility values, which are an exponential function of the barrier height [2-30]. It is obvious from Fig. 2-18 (a) that the discrepancy of the barrier height between DG and SG modes gets smaller as the gate overdrive is increased; in other words, for a given drain voltage, the drain current ratio is expected to behave as a monotonically decreasing function of the gate overdrive, in agreement with Fig. 2-12.

With regard to the constant peak current ratio irrespective of the gate overdrive

observed in [2-23], it may have to do with the different shape of the NW channel between this work and [2-23] resulting in distinct distribution profile of carriers and barrier lowering rates among DG and SG modes. Further investigation is required to validate this point.

The proposed configuration with two independent gate electrodes also increases the flexibility in device operation. Taking advantage of additional freedom from the auxiliary gate, VTH can be adjusted by tuning the applied bias of the auxiliary gate. This is illustrated in Figs. 2-20 (a) and (b) where the bias of the auxiliary gate varies from -3 V to 3 V in 0.5 V step for SG-1 and SG-2 modes, respectively. As can be seen, due to the tiny volume of NW, VTH is efficiently shifted along with different auxiliary gate bias whereas SS shows weak dependence. Similar behavior has been reported in double-gated SOI devices and was attributed to the channel potential modulation by the auxiliary gate [2-31]. Shown in Fig. 2-21 is the VTH as a function of the auxiliary gate voltage extracted from Fig. 2-20. Within the range of applied auxiliary bias from -3 V to 3 V, the VTH of the device can be shifted from 4.2 V to -0.52 V and 6.1 V to -2.2 V when the 1^st and 2^nd gates assume the auxiliary gate, respectively. This is a direct consequence of better channel controllability of the 2^nd gate than the 1^st gate. With tunable VTH, this kind of device has strong potential for low standby power circuits. For instance, in standby circuit operation, lower IOFF can be obtained by raising the VTH of the device.

And in active mode, the VTH can be adjusted into a moderate value for providing sufficient drive current.

It is worth noting that in Fig. 2-20 the characterized device is with 18-nm NW. For the other two thicker cases in Figs. 2-22 (a) and (b), when adopting the same scheme, the shift rate of VTH is much reduced and it is the IOFF that is mainly altered by the auxiliary gate, which in turn modulates VTH. This is so because when two gates are independent of each other, applying an auxiliary gate bias only determines the surface condition on its side; hence, as the bias of the auxiliary gate is increased, the surface also starts from being depleted to inversion and when to the point of strong inversion, which means that the surface on the auxiliary gate side is already conducting, the IOFF as seen by the driving gate rises dramatically. A more quantitative treatment of this subject can be found in [2-18].