Chapter 2 Double-Gated Poly-Si Thin Film Transistor with Twin
2.2 Experimental
2.2.1 Investigation of Selective Plasma Etching Conditions
The main feature in this structure lies in the fact that a sub-100 nm cavity could be formed by isotropic plasma etching using a high density plasma (HDP) etching apparatus. In this dissertation a transformer coupled plasma (TCP) reactor with model number TCP 9400 manufactured by Lam Research was used, which operates by inductively coupling RF power to plasma. This tool is equipped with two RF power generators. The top source RF power generates plasma and determines ion density, while the bottom bias RF power is responsible for controlling the ion bombardment energy. In other words, ion density and energy are independently controlled in this reactor, thus solving the inflexibility and poor efficiency of conventional capacitively-coupled reactors. In contrast to the typical anisotropic reactive-ion-etching (RIE) process in an HDP etching tool, the sub-100 nm cavity-forming technique is accomplished by turning off the bottom bias. In this way, the bombarding energy of ions would be reduced to achieve high etching selectivity between poly-Si and the other layers.
The process flow of the proposed two-step N+ poly-Si etching scheme is depicted in Fig. 2-1. A stack of layers comprising 100 nm-thermal oxide/50 nm-nitride/100 nm-N+ poly-Si/50 nm-nitride was deposited sequentially on a 6-inch Si wafer. Here the
N+ poly-Si layer is formed by in situ doping. Next, the top nitride and N+ poly-Si stack were patterned by anisotropic etching in a TCP reactor. Figure 2-2 (a) displays a scanning electron microscope (SEM) picture taken after this step. It is observed that the final etching profile is anisotropic. This is because chlorine etching mainly proceeds in an ion-induced manner and the applied bottom bias helps enhance the vertical ion bombardment; therefore the etched profile is essentially anisotropic.
Following the photoresist stripping, the wafer was loaded into the same reactor for performing the selective and isotropic N+ poly-Si plasma etching. In this step, the bottom bias is turned off and fluorine-containing gas SF6 is added along with chlorine for increasing the isotropic etching component, with the results shown in Figs. 2-2 (b)~(d) corresponding to different etching conditions. It has been well known that poly-Si can be etched by fluorine-based etchants because of high volatility of SiF4
[2-19]. Meanwhile, F radicals are usually produced in large quantities in plasma along with little polymer formation so the final profile will be relatively isotropic.
Representative images in Figs. 2-2 (b)~(d) indicate that fluorine addition indeed greatly enhances the isotropic profile and demonstrates high selectivity with respect to the nitride layers. This is quite reasonable because in addition to rendering the motion of bombarding ions a random manner, setting the bias power to zero also improves etching selectivity of poly-Si against other materials. It is noted that this isotropic etching is
performed in the same reactor as that of anisotropic etching, suggesting the compatibility and convenience of this novel procedure. Nonetheless, the profiles in Figs.
2-2 (b) and (c) reveal that the etching parameters still need to be optimized given that the lateral etching depths are still too deep for both cases, probably owing to either the top power and SF6 flow rate that are too large or the etching time that is too long. Even though reducing the etching duration can help decrease the etching depth down to sub-100 nm regime, as shown in Fig. 2-2 (d), the etching rate is still too fast to control if sub-50 nm dimension is demanded. In light of this, the etching recipe is adjusted to P = 5 mtorr, Cl2 = 50 sccm, SF6 = 10 sccm, and top power = 300 W. To demonstrate the merit of this approach in fabricating deca-nanometer NWs, Fig. 2-3 displays the lateral encroaching depth as a function of etching time as characterized by SEM, indicating that the NW dimension could be flexibly controlled. In fact, it is very hard to produce the same result each time for etching with duration less than 10 seconds since the condition of glow discharge is not yet stable in such a short period. However, it is believed that the proposed method will have more reproducible results provided that the etching condition is optimized. In other words, by carefully adjusting the flow rate of source gas, RF power, and etching time, the structural parameter can be easily and reliably shrunk into deca-nanometer regime.
The top view of the proposed device is shown in Fig. 2-4 along with the fabrication flow in Fig. 2-5 which is briefly described below. A 6-inch Si wafer capped with 100-nm-thick thermal oxide and 50-nm-thick SiN layer served as the substrate on top of which 100-nm in situ doped N+ poly-Si and 50-nm–thick SiN were next sequentially deposited. Subsequently, the topmost SiN hardmask and N+ poly-Si were patterned by lithography and dry etching (1st Gate in Fig. 2-4). Then, cavities underneath the nitride hardmask were formed by employing the selective plasma etching method discussed in the previous sub-section. With an eye to examining the impact of NW dimension on the device performance, through controlling the etching duration (8 sec, 10 sec, and 12 sec), devices with three different NW dimensions were fabricated. Afterwards, 20-nm TEOS (tetraethoxysilane) oxide and 100-nm amorphous-Si were deposited by low pressure chemical vapor deposition (LPCVD) to serve respectively as the 1st gate dielectric and active layer. Due to the excellent comformality offered by LPCVD, the cavities formed by selective plasma etching were completely filled with the deposited materials. The intention of inserting a SiN layer between the thermal oxide and N+ poly-Si becomes evident here in that it helps preserve the shape of the cavity during RCA clean process that involves HF dip prior to the deposition of the 1st gate dielectric. Solid phase crystallization (SPC) was then performed at 600 oC in N2 ambient for 24 hours to transform the amorphous-Si into poly-Si. The reason that recrystallized poly-Si is
adopted as the channel material instead of as-deposited poly-Si is that the poly-Si obtained through direct deposition exhibits smaller grain size and a larger number of defects [2-20]. Subsequently, source/drain (S/D) implantation was conducted by phosphorus with 15 keV energy at 5 × 1015 cm-2 dose. Here a low energy implantation was chosen in an attempt to avoid inadvertent channel doping which might cause degraded gate controllability and severe leakage current. Optimization for S/D doping will be discussed in more detail in Chapter 3.
After forming S/D photoresist patterns (S and D in Fig. 2-4), S/D regions and NW channels were simultaneously defined by a single anisotropic dry etching step. In this step, the portions of poly-Si residing in the cavities remained intact and would become the NW channels in the final structure. For multiple-gated operation, the 2nd gate stack consisting of 20-nm TEOS oxide and 100-nm in situ doped N+ poly-Si gate was next deposited and patterned (2nd Gate in Fig. 2-4). All devices were then covered with 300-nm-thick TEOS oxide passivation layer by LPCVD at 700 oC for 4 hours, which is sufficient for activating the dopants previously introduced into S/D regions. The device fabrication was completed after standard back-end processing, including contact hole opening and standard metallization steps. To further boost the device performance and reduce fluctuation, NH3 plasma treatment at 300 oC for 3 hours was performed on all devices before characterization [2-21].
2.2.3 Measurement Setup and Electrical Characterization Methods
Before further investigation of the electrical characteristics, several important electrical parameters and extraction methods used in this dissertation are clarified.
Electrical measurements were performed by HP 4156A semiconductor precision analyzer which was controlled by a personal computer through Interactive Characterization Software (ICS), and Agilent 5250A switch. During all measurements, the temperature was controlled and stabilized by a temperature-regulated chuck.
Based on the transfer curve measured, definitions for some of the important parameters are listed below.
1. Threshold voltage (VTH)
The threshold voltage (VTH) is defined by the constant current method and is equal to the gate voltage when the drain current reaches a particular value, which is expressed as
L 10nA I W
@ V
VTH = G D = ×
, (2-1) where W and L represent respectively the channel width and length.
2. Subthreshold swing (SS)
It is defined as the magnitude of gate voltage required to alter (either increase or
reduce) the drain current by an order of magnitude in the weak inversion region, which
As in the equation relating the drain current to the gate voltage, the field effect mobility (μFE) can be derived as follows,
D
where GM is the transconductance obtained by the derivative of the drain current with respect to the gate voltage and all the other symbols have their usual meanings.
4. Operation mode
Owing to the fact that the proposed device possesses two independent gates, during I-V measurement there are three feasible read modes as determined by the choice of the driving gate, which are termed SG-1, SG-2, and DG modes, as defined in Table 2-I. For SG-1 mode, the 1st gate acts as the driving gate while the 2nd gate is called the auxiliary gate (AG) with a fixed bias, and vice versa for SG-2 mode. For the following context, AG will be applied a bias equal to zero (grounded) unless otherwise specified.
DG mode, on the other hand, stands for the scheme when both gates are tied together to drive the device simultaneously.
2.3 Results and Discussion
2.3.1 Impacts of Double-Gated Configuration on Device Performance
Shown in Fig. 2-6 is a cross-sectional transmission electron microscopic (TEM) image (along line A-B in Fig. 2-4) for one of the fabricated devices in which the selective plasma etching is performed for 6 sec. One can see that the NW channel thickness (or the width of NW between the two gate dielectrics) is around 18 nm and is nearly rectangular in shape. Transfer curves for this device are given in Fig. 2-7 where it is obvious that the DG mode demonstrates much enhanced performance over the other two SG modes in terms of lower VTH, higher ON current (ION), and steeper SS owing to its stronger electrostatic gate controllability over channels. It is also worth noting that SG-1 mode exhibits much lower ION and degraded SS as compared with SG-2 mode, indicating that the proposed device is an asymmetric type double-gated field-effect transistor. This can be attributed to the larger S/D resistance under SG-1 mode as the conduction proceeds mainly at the inner channel interface of the NWs, which is consistent with the output characteristics in Fig. 2-8. To make it more clear, a cross-sectional view along the overlap region between the S/D and gates (line C-D in Fig. 2-4) is plotted in Fig. 2-9. During SG-1 mode of operation, the conduction
electrons must transport across the offset (i.e., ungated) regions between the S/D and the inner channel, resulting in larger S/D series resistance [2-22]. Meanwhile, these ungated regions also serve as additional barriers that carriers have to overcome before inversion can occur, which translates to degraded SS. It is thus expected that under DG mode of operation, the current conduction is predominantly governed by the outer channels controlled by the 2nd gate. This statement will be more vividly demonstrated in the following sub-section where size dependency is examined. And for the purpose of fluctuation inspection, devices with different number of NW channels fabricated using a multi-finger layout [2-16] are characterized as shown in Fig. 2-10, which suggests that our NW TFT indeed possesses excellent uniformity from the nearly identical SS and VTH for all the measured devices.
GM characteristics under various modes are shown in Fig. 2-11. On account of more rapid shift of channel potential under DG operation, higher GM is obtained as compared with two SG modes. Output curves in Fig. 2-8 reveal that DG mode provides the highest current drive among the three modes, which is reasonable considering that the conduction width is the largest in DG operation; thus, to have a more fair comparison, the drain current ratio defined as the drain current under DG mode divided by the sum of that under SG-1 and SG-2 modes is plotted against the drain voltage in Fig. 2-12. It can be observed that DG operation effectively offers additional current
improvement since the resultant DG current is larger than two SG modes combined. In addition, it is interesting to note that the maximum ratio increases with decreasing magnitude of the gate overdrive, whose root cause will be discussed in Chapter 2.3.2.
Thus, it can be inferred from the aforementioned information that for this double-gated NW device, there is a strong interaction between the two gates leading to much improved performance. As a matter of fact, recently our group has found that the origin of output current enhancement giving rise to the result in Fig. 2-12 can be analytically modeled by taking into account the body effect [2-23]. By inserting an additional term caused by the body effect into the formula of the drain current as a function of the gate/drain voltage under SG modes, the saturation voltage VDsat of two SG modes becomes smaller than that of DG mode for a given gate overdrive owing to the fact that there is no body effect under DG mode. Thus, the output current reaches saturation earlier under SG modes and the drain voltage at which the ratio saturates in Fig. 2-12 coincides with the VDsat under DG mode. Besides the early saturation phenomenon, it was shown that the larger-than-unity drain current ratio in the linear regime is also contributed by mobility enhancement under DG mode. One plausible mechanism leading to such mobility and GM improvement in DG mode is volume inversion [2-24].
As opposed to the surface inversion in SG modes where carriers tend to be concentrated near the oxide/Si interface, under volume inversion in DG mode the charge centroid for
a symmetric DG MOSFET would be located near the middle of the channel and the surface-scattering-limited mobility is increased as a result. The improved mobility then brings about the gain in current drive and GM. However, double-gated SOI devices with ultra-thin body (less than 10 nm) are usually mandatory for volume inversion to assume a significant role [2-25]. Considering that the thickness of the NW characterized is still well above this value, the possibility of volume inversion can be ruled out and a detailed investigation of its origin will be given in the next sub-section.
2.3.2 Dependency of Performance Enhancement in
Double-Gated over Single-Gated Operation on Nanowire Channel Dimension
To probe the impact of NW dimension, Figs. 2-13 (a) and (b) illustrate transfer curves for devices with 43- and 52-nm-thick NW channels, respectively. Evidently, for the 43-nm case, the enhancement from DG mode is still visible but the extent is smaller than that of the previous 18-nm one. On the other hand, when NW is widened to 52-nm, it comes as a surprise because no observable merit is obtained under multiple-gated operation since ID-VG characteristics for DG and SG-2 mode are essentially identical.
Before further in-depth investigation of the root cause for this size-dependent effect, additional information can be gained from other aspects.
First, GM enhancement is examined. Similar to the drain current ratio, GM ratio can
be defined as the GM (with respect to gate overdrive) under DG mode divided by the sum of that under SG-1 and SG-2 modes. As shown in Fig. 2-14, the peak of GM ratio is observed to be larger when NW size is smaller. For the device with 52-nm NW, the maximum ratio is only slightly larger than unity, implying that even under DG operation, the 1st and 2nd gates still control the channel in a rather independent way and the NW channel is only partially depleted in this case. On the contrary, the maximum ratio for 18-nm NW is seen to reach 2.4. From another viewpoint in terms of parasitic resistance, the total resistance is extracted in Fig. 2-15. S/D series resistance can thereby be determined based on the method in [2-26], in which a first order exponential curve fitting was adopted. Actually, under DG mode, the two conduction paths governed by 1st and 2nd gates can be conceived as flowing in parallel. Thus, for the simplest condition when two gates work independently, the S/D series resistance of DG mode (RDG) should be approximately equal to the equivalent resistance (REQ) of two single-gated modes. To obtain REQ, the drain current as a function of the gate voltage under SG-1 and SG-2 modes is first summed up followed by employing the fitting method in [2-26] to determine REQ. The extraction procedures (only the 18-nm NW case) are shown in Fig.
2-15 and the results for devices with three different NW thicknesses displayed in Fig.
2-16 (a). The smaller S/D series resistance under DG mode as compared with SG modes can be partly ascribed to the larger conduction area between channels and S/D provided
by DG mode, which helps reduce the spreading resistance. The ratio of the difference between REQ and RDG to REQ is given in Fig. 2-16 (b). For DG mode of operation, it can be seen that the 18-nm, 43-nm, and 52-nm NW give 45 %, 35 %, and 17 % reduction in terms of S/D resistance improvement, respectively. It is noteworthy that the technique utilized here cannot provide very accurate determination of the S/D resistance under SG modes because the approach in [2-26] was based on a tie-gated device without the need to consider the body effect. This is apparently not the case in our device where the drain current under SG modes is intimately related to the applied bias of the auxiliary gate.
However, even when normalization of the VTH is undertaken as shown in the output curves in Fig. 2-12, DG mode is still able to offer larger output current than SG-1 and SG-2 modes combined, and therefore it justifies the methodology used in Fig. 2-15 though the data presented is only a rough estimate.
As another indicator of gate controllability, the extracted SS as a function of NW thickness is plotted in Fig. 2-17 where SS is observed to decrease with reduced NW thickness for all three modes. The above size dependency, in fact, has been treated in both fully-depleted double-gated SOI [2-27][2-28] and poly-Si devices [2-29]. For single-crystalline devices, more rapid variation of surface potential triggered by the larger vertical electric field induced in devices with smaller NW thickness leads to better short channel effects immunity as the NW dimension is reduced. However, in
poly-Si based devices, potential barriers present in the grain boundaries are another major factor that needs to be accounted for so as to correctly interpret our results. This subject was recently treated in [2-23] where the origin of performance enhancement of a double-gated poly-Si NW transistor was investigated. And it was found that the major reason for the performance improvement under DG mode over SG modes stemmed from the different modulation capability of grain boundary barrier heights. To this end, using the similar analysis technique, the barrier height of grain boundary as a function of the gate voltage for three operation modes is shown in Fig. 2-18. Based on [2-30], the barrier height is extracted by using transfer curves measured at two different temperatures. Thanks to the increase of inversion carriers, the barrier height is monotonically made smaller with increasing VG- VTH. At strong inversion, the barrier of DG mode is the lowest among the three modes, demonstrating the merit of multiple-gated configuration in providing improved mobility and ION over SG modes.
poly-Si based devices, potential barriers present in the grain boundaries are another major factor that needs to be accounted for so as to correctly interpret our results. This subject was recently treated in [2-23] where the origin of performance enhancement of a double-gated poly-Si NW transistor was investigated. And it was found that the major reason for the performance improvement under DG mode over SG modes stemmed from the different modulation capability of grain boundary barrier heights. To this end, using the similar analysis technique, the barrier height of grain boundary as a function of the gate voltage for three operation modes is shown in Fig. 2-18. Based on [2-30], the barrier height is extracted by using transfer curves measured at two different temperatures. Thanks to the increase of inversion carriers, the barrier height is monotonically made smaller with increasing VG- VTH. At strong inversion, the barrier of DG mode is the lowest among the three modes, demonstrating the merit of multiple-gated configuration in providing improved mobility and ION over SG modes.