Chapter 4 Investigations on Transport Properties of Double-Gated
4.4 Electrical Characteristics at Cryogenic Ambient
4.4.3 Observation of Hysteresis and Single Electron Effects
Since the proposed model implies that the conduction mechanism is similar to a feedback process, which has been utilized in achieving steep SS devices [4-19], the forward and reverse sweeping of the gate voltage is expected to result in hysteresis of transfer characteristics, as evidenced in Fig. 4-16 and Fig. 4-17 for L = 5 μm and 63 nm at 78 K, respectively. Here the applied drain voltages are 10 mV and 0.1 V. Negligible hysteresis in SG-1 mode indicates that it still obeys the drift-diffusion principle so that the turn-on and turn-off processes are reversible, and the effect of trapping in grain boundaries of poly-Si can be ruled out since plasma treatment was performed on the devices prior to characterization [4-20]. In contrast, SG-2 mode exhibits apparent hysteresis, with VTH window at VD = 0.1 V being 0.7 V and 3 V for L = 5 μm and 63 nm, respectively. This is because of the voluminous mobile charges existing in the on-state,
so during the reverse sweeping, the device cannot be turned off at the same voltage as it is turned on. In Fig. 4-16 (b), reverse sweeping displays a steeper SS than the forward one probably due to the additional effect of interface charges. A more detailed interpretation will be given later. It is interesting to note that SS of the reverse sweeping is larger than that of the forward one in Fig. 4-17 (b), which is related to their dissimilar effective barrier profiles. At the outset of the reverse sweeping when the 2nd gate voltage is sufficiently large, the barrier heights present at both the middle and edges of the channel are small compared with the thermal energy. As the 2nd gate voltage is gradually decreased, the conduction band edge of the central channel is supposed to be raised at a more rapid rate over that of the portion that is adjacent to S/D. In this regard, the major conduction barrier profile as seen by carriers is similar to that of a conventional MOSFET and the depth of the potential well is reduced with decreasing gate voltage.
For the same reason, the trapping of carriers is less severe in the reverse sweeping process and a smaller VTH is obtained as a result. Even though the effect of trapping/detrapping is now dramatically diminished compared with the turn-on process, this mechanism still needs to be taken into account given that during the turn-off process, SS of a short channel device in Fig. 4-17 (b) is steeper than that of a longer one in Fig. 4-16 (b).
The above statement also provides another perspective on the characteristics in Fig.
4-16 (b). As noted in Section 4.4.2, the effect of trapping/detrapping is actually not negligible for a long L device; hence, in the forward sweeping curve from VG2 = 0.1 to 3 V, the subthreshold current suffers carrier trapping and beyond VG2 = 3 V, detrapping sets in along with a sudden jump of the drain current. Since electron trapping in this case does not completely suppress the drain current as in a short L device, SS of forward sweeping is reasonably larger than that of the reverse one.
VD-dependent ID-VG curves plotted in Fig. 4-18 (a) imply that at 78 K hysteresis is observable at least up to VD = 2 V and the hysteresis window is monotonically decreasing with T, as shown in Fig. 4-18 (b), which is consistent with the fact that the probability of trapping/detrapping process occurrence is reduced with higher T.
As a matter of fact, some of the measured devices exhibit drain current oscillation as the gate voltage is varied. Figure 4-19 (left vertical axis) depicts such a behavior by magnifying ID-VG curves in the strong inversion regime. The corresponding GM
characteristic is shown in Fig. 4-19 as well in the right vertical axis. Although our proposed device is not intended to operate as a single electron transistor (SET), the potential valley in Fig. 4-11 assumes the role of an island and the two humps to its side are essentially tunneling junctions. However, owing to the large gate voltage interval (25 mV), the directly-counted period of GM oscillation shows only three different values and thus it is difficult to accurately perform a Gaussian fit, which is required for
extracting the charging energy [4-18] [4-21]. Another factor that may contribute to the drain current oscillation is inter-sub-band scattering whose influence becomes greater as the carrier concentration is increased due to the larger number of occupied sub-bands [4-22]. Asymmetric kink points for a given gate voltage in Fig. 4-20 suggest that the magnitude of barrier height at S/D is not identical, which can also be verified by interchanging the applied biases of S/D for ID-VG characterization in Fig. 4-21.
4.5 Summary
Making use of the mix-and-match of I-line stepper and e-beam direct writing, independent double-gated poly-Si NW transistor with L ranging from 39 nm to 5 μm are successfully fabricated and demonstrate excellent SCE immunity in terms of insignificant SS roll-off. And the origin of abrupt turn-on characteristics observed in SG-2 mode at cryogenic ambient is comprehensively studied in this chapter. It is found that the occurrence of this behavior is greatly influenced by L, T, and drain bias. A model taking into account the dopant distribution of an implanted gate is proposed to interpret our findings. It suggests that the non-intentionally formed barriers at the channel edge give rise to carrier trapping effects until an adequately large gate voltage is applied to lower the magnitude of the barriers for the trapped electrons to flow to the drain. Furthermore, since the channel potential profile resembles that of an island
confined by two tunneling junctions, single-electron effects are also observed. This kind of process-induced barrier is an attractive scheme to build SETs with simple CMOS-compatible process flow and with the aid of further surface engineering should help realize steep SS transistors at room temperature.
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Fig. 4-1 Layout of the device fabricated using mix-and-match between e-beam and I-line. L defines the channel length, which is smaller than 100 nm in this case.
D S
1st Gate
L NW
2nd Gate
Fig. 4-2 (a) Plane- and (b) cross-sectional view images of a fabricated device showing a 23-nm-thick NW channel surrounded by the 1st and 2nd gates. The drastic grain size discrepancy between the 1st and 2nd gates is a consequence of the different doping method implemented: the 1st gate is by in situ doping while the 2nd gate by implantation.
100 nm
2nd Gate (implanted)
1st Gate (in-situ doped)
NW
(a)
20 nm 1st Gate
2nd Gate
23 nm NW (b)
Fig. 4-3 Length-dependent transfer curves at 25oC under (a) SG-1, (b) SG-2, and (c) DG
Fig. 4-4 SS as a function of L extracted from Fig. 4-3.
Channel Length (μm)
0.1 1 10
SS (mV/de c )
0 100 200 300 400 500
SG-1 mode SG-2 mode DG mode
V
D= 0.5 V
1st Gate Voltage (V)
Fig. 4-5 Transfer characteristics at various temperatures for a device with 70 nm channel length under (a) SG-1, (b) SG-2, and (c) DG modes. The behavior of SG-1 mode is in accordance with thermionic emission model while SG-2 mode starts to exhibit very steep SS when T is below150 K. Abrupt increase of ID for DG mode at 100 K and 78 K is caused by the channel controlled by the 2nd gate.
Fig. 4-6 (a) SS and (b) VTH as a function of temperature for three operation modes extracted from Fig. 4-5. Ideal value of SS equal to ln10 × kT/q is also included for comparison in (a).
Fig. 4-7 Transfer characteristics at 78 K showing impacts of L in determining the occurrence of steep SS. In conflict with the conventional SCE theory, the subthreshold current is reduced as L is shortened.
2nd Gate Voltage (V)
1.0 1.5 2.0 2.5 3.0 3.5 4.0
Drain Current (A )
10
-1310
-1210
-1110
-1010
-910
-810
-710
-6L = 5 μm L = 2 μm L = 0.7 μm L = 70 nm
V
D= 0.5 V
T = 78 K
SG-2 mode
Fig. 4-8 Schematic structures along the length direction showing the 2nd gate-controlled side of channel for a device whose L is (a) long (> 100 nm) and (b) short (<
100 nm). Points A and C correspond to regions of the channel adjacent to S/D controlled by the locally thickened gate and point B to the middle of the channel. Because the thickness of the 2nd gate is 100 nm, the part of the 2nd gate between S/D is thicker in (b) than in (a).
source drain
oxide
NW
heavily doped poly
lightly doped poly
L
source drain
heavily doped poly
A
NW
B C
A B C L
(a)
(b)
Fig. 4-9 Simulated dopant distribution in an implanted gate corresponding to a device with (a) L = 2 μm and (b) L = 70 nm. It is observed that the bottom portion of the 2nd gate has much lower concentration in (b) than in (a).
dra in
D
D
P concentration (cm‐3) 1E+20 1E+19 1E+18 1E+17 1E+16 1E+15
(a)
(b)
Fig. 4-10 (a) TEM image of a non-overlapped NMOSFET with 16 nm gate length. The notched gate is fabricated by selective etching of poly-SiGe. (b) Simulated electrostatic channel potential profile under two different gate voltages. As the gate voltage is increased, the potential valley drops to a larger extent than the humps in the non-overlapped regions, facilitating the formation of a quantum dot. Adapted from [4-18].
Fig. 4-11 Qualitative band diagrams for devices with long and short L. Points A, B, and C correspond to the regions labeled in Fig. 4-8. For a short channel device, thermionic emission is the dominant transport mechanism while both thermionic emission and tunneling should be considered for a long channel device.
A
B
C
source drain
A
B
C
e‐
e‐
long L
short L
TE
TE
Tun
TE: thermionic emission Tun: tunneling
Fig. 4-12 Proposed model for the origin of steep SS. (a) For a low 2nd gate voltage (VG2
= V1), after electron trapping in the channel (dashed line), the potential is raised from its original level (solid line), which deters further injection from the source. (b) For a larger 2nd gate voltage (VG2 = V2) that considerably reduces the barrier height at drain side, electrons are detrapped and flow to the drain, leading to channel potential drop (dotted line) and an abrupt increase of drain current.
e‐ e‐ e‐
source drain
e‐ e‐ e‐
source drain
before e‐ trapping after e‐ trapping
after e‐ detrapping
V
G2= V
1V
G2= V
2> V
1(a)
(b)
Fig. 4-13 Transfer characteristics as a function of temperature for a device whose 1st and 2nd gates are both in situ doped. Compared with Fig. 4-5 (b), steep SS completely vanishes owing to the removal of barriers when very uniform doping concentration throughout the whole 2nd gate electrode is achieved by in situ doping.
Fig. 4-14 Drain-voltage-dependent transfer characteristics suggest DIBL could eliminate the occurrence of steep SS, in agreement with the proposed model.
2nd Gate Voltage (V)
-1 0 1 2 3 4
Dra in Current (A )
10
-1310
-1210
-1110
-1010
-910
-810
-710
-610
-5V
D= 0.01 V V
D= 0.1 V V
D= 0.5 V V
D= 1 V V
D= 2 V
L = 70 nm
T = 150 K
SG-2 mode
Fig. 4-15 Transfer characteristics under SG-2 mode for various VG1 at (a) 150 K and (b)
Fig. 4-16 Transfer characteristics for a device with L = 5 μm under forward and reverse sweeping of the gate voltage for (a) SG-1, (b) SG-2, and (c) DG modes.
1st Gate Voltage (V)
Fig. 4-17 Transfer characteristics for a device with L = 63 nm under forward and reverse sweeping of the gate voltage for (a) SG-1, (b) SG-2, and (c) DG modes.
1st Gate Voltage (V)
Fig. 4-18 Forward and reverse sweeping of transfer characteristics with (a) the drain voltage and (b) temperature as a parameter.
2nd Gate Voltage (V)
Fig. 4-19 Oscillation of the drain current and resultant GM at 1 mV VD.
2nd Gate Voltage (V)
2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
D rain Current (nA)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
G
M(nS)
-2 -1 0 1 2 3 4
I
DG
MV
D= 1 mV
L = 67 nm
T = 78 K
SG-2 mode
Fig. 4-20 Output characteristics showing a wider current blockade region at a lower gate voltage. Different kink points in the positive and negative drain voltage regime indicate the presence of asymmetric barriers.
Drain Voltage (V)
-4 -2 0 2 4
Drai n Current ( μA)
-25 -20 -15 -10 -5 0 5 10 15
V
G2= 1V V
G2= 2V V
G2= 3V V
G2= 4V
SG-2 mode
T = 78 K
L = 60 nm
Fig. 4-21 Transfer characteristics measured by interchanging the applied biases to S/D showing two distinct curves, an indication of the asymmetry between source and drain barriers, in agreement with Fig. 4-20.
2nd Gate Voltage (V)
2.0 2.5 3.0 3.5 4.0
Drain Current (A)
10
-1310
-1210
-1110
-1010
-910
-810
-710
-610
-5V
D= 0.5 V, V
S= 0 V V
S= 0.5 V, V
D= 0 V L = 60 nm
SG-2 mode
T = 78 K
Chapter 5
Analysis on the Potential of Poly-Si Nanowire Thin Film Transistors Featuring Independent Double-Gated Configuration for Nonvolatile Memory Applications
5.1 Introduction
With ever increasing demand for flash memory products (e.g., cell phones, USB drives, memory cards, etc.), cost reduction-oriented memory industries have devoted to circumventing the scaling limit [5-1]. Among the various nonvolatile memory (NVM) architectures, charge-trapping (CT) type device has demonstrated its high performance and strong potential to succeed the conventional floating-gate (FG) type device.
Silicon-oxide-nitride-oxide-silicon (SONOS), in particular, has received renewed interests due to its less stringent limitation on the tunneling oxide thickness and stronger immunity against interference coupling [5-2]. Akin to nitride read-only memory (NROM) [5-3], SONOS relies on the nonconductive nitride to trap electrons coming from the channel. In contrast to conductive polycrystalline-Si (poly-Si) used in the FG device, this unique feature helps realize 2-bit/cell functionality by storing electrons at two different sites. In addition to trapping layer engineering, 3D technology is also
under the spotlight as it not only is compatible with conventional planar processes by simply adding more layers in the vertical direction, but also greatly improves interconnect density, reduces cost and provides a platform for heterogeneous integration [5-4]. Recent works have demonstrated the feasibility and strong potential of 3D technology in NVM applications [5-5]-[5-7]. It is worth noting that in those 3D stacked structures, poly-Si is adopted for the channel material to avoid the complexity and difficulty in high temperature deposition of single crystalline Si layers. Though grain boundary effects are a concern in poly-Si, poly-Si based thin film transistors (TFTs) with nanowire (NW) channel and multi-gated scheme have been shown to perform comparably to their bulk-Si counterparts [5-8][5-9]. In addition, poly-Si TFTs greatly facilitate the integration of a wide array of circuit components, making possible system-on-panel (SOP) applications [5-10].
Most of the previous works regarding NW SONOS devices put emphasis on tie-gated structures owing to their better gate controllability and simpler fabrication procedure than separate-gated counterparts [5-11]-[5-13]. However, independent double-gated (IDG) type device has started to demonstrate its merits for more flexible operations based on the opposite gate bias effects [5-14]-[5-16]. In light of this and employing a very simple and low cost procedure, we propose an IDG poly-Si NW TFT as SONOS-type memory device in this chapter. It was found that the VTH windows
under two feasible read modes (i.e., read by two different gates) show distinctly different dependency on the auxiliary gate (AG) bias. Here, AG refers to the gate with a fixed bias during I-V measurement in contrast to the driving gate. In the following context, we investigate the mechanism leading to different P/E efficiency of the two read modes in detail, discuss the merits of the unconventional read approach and its retention and endurance characteristics. Considering that the device studied in this work is programmed and erased by Fowler-Nordheim (F-N) tunneling, which is compatible with NAND type flash memory, for the purpose of realizing 2-bit/cell feature, ONO stack is used as the dielectrics of both gates.
The content of this chapter is arranged as follows. Section 5.2 gives a brief overview of the P/E operation principles in flash memory. Influence of AG bias on P/E speed is then investigated in Section 5.3. The underlying principle governing the different dependency of VTH window on AG bias under two read modes is discussed in Section 5.4 along with its implications for P/E speed, endurance, and retention characteristics when different read modes are adopted. Section 5.5 demonstrates the proof-of-concept feature of 2-bit/cell functionality for our IDG NW device. Finally, a brief conclusion is drawn in Section 5.6. Through the analysis performed in this chapter, it is believed that the proposed concept will be highly advantageous in facilitating the advancement of 3D high density memory technology.
5.2 Programming and Erasing Operation Principles
Owing to the circuit design and the device wiring structure, NOR type flash memory is programmed by channel hot electron injection (CHEI) and erased by F-N tunneling while NAND type is programmed and erased both by F-N tunneling, as illustrated in Fig. 5-1. Operation features of NAND and NOR flash memory [5-17] are tabulated in Fig. 5-1(c). CHEI, as its name suggests, relies on a large lateral electric field to accelerate electrons to a point that they possess sufficiently high kinetic energy or become hot, which if lucky would then surmount the energy barrier between the gate dielectric and channel and get injected into the floating gate, giving rise to a VTH shift [5-18]. A schematic diagram detailing CHEI is shown in Fig. 5-2. The merits of CHEI include faster P/E speed (as compared with F-N tunneling) and the possibility of realizing multi-bit per cell features for charge-trapping type memory. However, as CHEI is in progress, the oxide field may become repulsive and some or all of the electrons injected could be repelled back into the silicon, resulting in low injection efficiency [5-19]. Furthermore, the damage done to the dielectric is another factor causing concern for the characteristics of cycling endurance, including gate disturb, window opening, and eccentric erase, etc. [5-20][5-21]. Scalability is also something that acts as a showstopper for NOR flash. In 45-nm node, self-aligned contact technique has been
adopted, but the physical gate length is still 110 nm due to the requirement of the drain voltage being above a certain value for CHEI to occur without inducing significant SCEs [5-22]. Hence, more sophisticated junction engineering and programming scheme needs to be utilized to promote aggressive gate length scaling for NOR flash [5-23].
When F-N tunneling occurs, conducting electrons in the channel tunnel through a triangular potential barrier into the floating gate via quantum mechanical tunneling, as shown in Fig. 5-3. An analytical formula in a simplified form relating the current density to the tunneling width and electric field is given by [5-24]
J = α Eox2 exp(-β/Eox) (5-1)
J = α Eox2 exp(-β/Eox) (5-1)