Organization of the Thesis

There are five chapters in the thesis. Chapter 1 is the introduction to ADC talking about background and motivations of research in ADC. Chapter 2 is the design and simulation of precharged SHA. The results of each circuit block in SHA will be shown at the end of this chapter.

Chapter 3 is the design and simulation of Multiplying Digital-to-Analog Converter (MDAC). In this chapter the process variation in comparator will be simulated. After all the circuit blocks being done we move to Chapter 4, where we will talk about whole ADC architecture using circuit blocks designed before. The effective number of bits (ENOB), INL and DNL will be simulated.

Finally, Chapter 5 is the conclusion about this research.

Fig 1.1 Connection between analog world and digital world

Fig 1.2 Classification of ADC applications according to sampling rate and resolution

Fig 1.3 10-bit pipelined ADC structure

Fig 1.4 Simplified circuit for modeling a typical feedback amplifier

CHAPTER 2

Precharged Sample-and-Hold Amplifier

2.1 Switch Design 2.1.1 NMOS Switch

This section will introduce NMOS and CMOS switches which are used a lot in designing mixed-signal circuits. Shown in Fig 2.1 is a simple NMOS switch controlled by a clock signal.

When clock goes low, the charge in the channel will inject to both sides equally, which can be written as:

(

^{GS- T}

)

ch ox

Q =C WL V V (2.1)

, in which we assume that impedance on the both sides are equal. This charge injection will cause voltage stored on a capacitor change, therefore, destroy the information we want. Also, the channel resistance is written as:

, it is an important design consideration when speed becomes an issue. Shown in Fig 2.2 is channel resistance with different channel widths versus input signal level.

2.1.2 CMOS Switch

When large signal has to be process, we might consider using CMOS switch shown in Fig 2.3.

In the same design manner, charge injection and channel resistance are important parameter. The charge injection of CMOS switch is difficult to express, but it is often much smaller than that of NMOS switch. In circuit design, the charge injection problem will be conquered by some techniques. The channel resistance of CMOS switch is written as:

( ) ^{( )} ( ) ( )

independent of input signal level [8]. Fig 2.4 shows the channel resistance with different sizes of NMOS and PMOS versus input signal level. It is apparent to see that large transistor size can have small and constant resistance.

2.2 Introduction to Precharged SHA

Precharged SHA and also called double miller capacitors SHA is shown in Fig 2.5. It can be seen that in the sample mode signals are sampled on both Cs and CL, which is the loading of the next stage. Having this design manner the output is precharged to approximate desired voltage in sample mode. When in the hold mode, which forms the miller capacitor around the opamp, the output signal would not vary considerably, so the opamp’s output voltage could stay nearly at the common mode voltage, therefore, low power and small output swing could be achieved. Also, clock phases are shown in Fig 2.6. When ψ₁ is high, it is in the sample mode. ψ_1a is off before ψ₁ because it would disable the path to be injected charge. This clock phase arrangement is called bottom plate sampling [9]. When the instant of ψ_1a goes low, the outputs start to hold the voltages sampled before (the charge stored on C_s is unchanged). When at the end of ψ₂ the hold signal is stable and then the low of ψ₂ is the time when the next stage is processing this sampled signal. In fact, the exact voltage at the output is not the point, but the charge stored on capacitor is. Ideally the charge stored on C_s does not change either in the sample mode or the hold mode unless the charge injections are considerable. As we mentioned before the combination of Cs

and C_o in the hold mode forms a miller capacitor, reducing the charge injections dramatically from switches S1 to S4. Since we use differential structure and the information is stored as the type of charge, the input common mode voltage could be different from the output common mode voltage.

So the input common mode voltage of amplifier is defined at the middle of opamp’s input common mode range, while output common mode voltage is defined at the middle of supply voltage.

Now we discuss the noise issue in SHA. The noise in the integrated circuits is expressed as power. In Fig 2.5 both the sample mode and hold mode contribute the noise to the outputs. We first express the output noise power in the sample mode as:

. 2

S O L

n s KT

V =C C C

+ + (2.4) ,where K is Boltzmann’s constant and T is absolute temperature. Then in the hold mode the output

noise is described by:

, where C_pi is the input capacitor of the opamp and n_e is the noise contribution factor of the opamp due to the other noise source except the input transistors, and it depends on the architecture of the opamp [1]. These two noise power values should be added to obtain the total noise power.

2.3 Opamp Design

Fig 2.7 shows a telescopic opamp. Telescopic opamp has the advantages of low power, high gain, high speed and low noise, but it suffers from small output swing. Listed above are the properties of telescopic opamp, the real performance is determined by designers in terms of system requirements and the tradeoffs between each of them. Now we talk about some concerns for designing this opamp: (1) slew rate is not we concern since output voltage is much stable and the differential inputs will not drive it out of its linear range. (2) small output swing can be designed, therefore large overdrive of transistors and high speed are achieved. (3) input common mode range need not to be large unless switch charge injections are very large, which is controlled by designing switches to be small. (4) speed and phase margin are much complicated to describe and they depend on how much loading of the next stage is. (5) common mode feedback amplifier

(CMFB) could not tolerate large output swing, so the overdrive of differential pairs in CMFB (M_c1~M_c4) have to be chosen carefully [9]. Now we move to specify the specifications of the opamp used in precharged SHA mathematically.

2.3.1 DC Gain Requirement

In the feedback amplifier, feedback network is usually formed by passive component such as resistors and capacitors and its gain is determined by its ratio. In this feedback SHA system, the forward path, i.e. opamp, has high gain to perform virtual short at the input differential voltage. If gain is not large enough, the inputs would have a little differential voltage, therefore, causing the feedback amplifier’s gain deflect from its ideal value. Precharged SHA is supposed to have gain of one in the hold mode if opamp’s gain and bandwidth are infinite. First if we consider the DC gain only we could write the input/output transfer function in the hold mode as:

1 1 limited in 20MHz. To achieve 10-bit accuracy, the deviation of V_o from V_i should be less than 1/2^N+1 (0.00049) of Vi. With these assumption, substitute them into (2.6), then we obtain that A0

(DC gain of opamp) should be larger than 163.

2.3.2 Output Swing Estimation

Here output swing is defined as differential output swing. The output swing is caused by the input differential signals when charge injections of switches are not equal or opamp’s mismatch problem, but the most importantly this will happen is that voltages stored on Cs , Co and CL are not equal. An unequal voltages stored on these capacitors is obvious because the time difference betweenψ₁ and ψ_1a. The output swing can be expressed by:

With some rational assumptions of Co=CL and Vco=Vcl=0.96Vi , we obtain that Vo,op = 0.32Vp-p.

2.3.3 Unity-Gain Frequency Requirement

In precharged SHA the feedback factor is one in the hold mode, the unity gain frequency (f_t) of opamp would approximately be the bandwidth (f-3dB) of SHA. It is the frequency range that an opamp has gain ability to operate correctly. More importantly it affects the settling speed of small signal processed in the opamp. In small signal model, transfer function of the first-order system can be written as:

( ) ( )

[

( ) ( )⁰

]

^{. t}

o t o o o

V =V ∞ − V ∞ −V e^−τ (2.8)

according to Laplace transform of the system [11]. The extreme single-ended output swing is 1.66V (from 1.5+0.32/2) if common mode output voltage is 1.5V. If 10-bit accuracy is desired, then settling within 0.1% of sampled voltage must be achieved. If we assume that settling within 3ns is rational, then substitute these assumptions into (2.8), we have f_t >281MHz. Fig 2.8 shows the configuration in the hold mode for calculating the time constant of the system. Time constant of the system is given by:

, in which Gm is the transconductance of the opamp. In (2.9) we could see that the time constant is affected by many parameters and tradeoff is complicated among each of them.

2.4 Bootstrapped Switch Design

In Fig 2.5, switches design is critical when analog signals have to be processed. We see very clearly that S₁, S₂, S₁₁ and S₁₂ sample analog input signal, therefore, their linearity and accuracy are very critical than others. The designs of the other switches are simple because they just process a constant voltage. If voltage level is large CMOS switches are used, otherwise NMOS switches

are used. Now we consider a special switch called bootstrapped analog switch for sampling analog signal. Bootstrapped switch configuration is shown in Fig 2.9 [7][12]. The idea in this is that making the charge injection independent of input signal level leads to no distortion at the output.

What makes the charge injection a constant is that we let the gate-source voltage of M_c-vgs constant and which can be understood in (2.1). The circuit operation can be achieved by charging the capacitor (C_b) in advanced, then disconnect the path to avoid the charge lost and gate-source voltage will maintain the voltage charged before. We must note that there are some nodes of this circuit will exceed the supply voltage, so the substrates have to be connected to the highest voltage nodes [7]. There is also a very important design consideration here that it must be designed that the delay time of switch is constant at all input frequencies. This is because non-constant delay time would cause distortion at the output. Now we use a terminology called group delay to exhibit the delay time at each frequency. The group delay at each frequency equals the negative of the slope of the phase at that frequency, it can be defined as:

( )

_d^d

{

^{H j}

( ) }

τ ω ω

= − ω ∠ (2.10) , where ∠H(jw) is the phase response [13]. For no delay time we should have our input frequency be less than one-tenth of f-3dB. Fig 2.10 shows a RC phase response with zero phase shifts (zero time delay) below one-tenth of f_-3dB, so we can keep the resistance of switch small to reduce time delay. The resistance of bootstrapped switch (Mc-vgs) versus input signal level is shown in Fig 2.11.

2.5 Capacitor Size Selection

Capacitors are very important in switch-capacitor circuits. Although a capacitor doesn’t contribute noise, the combination of resistors and capacitors contribute noise. In simple RC circuit we have RMS noise voltage of:

rms KT

V = C (2.11)

across the capacitor. It should be note that this noise voltage is independent of the value of resistance. We can decrease the KT/C noise by only increasing the value of C. For example, in (2.4) we can increase the value of the parallel combination of capacitors in denominator to keep the sampled RMS noise voltage under 1 LSB of ADC. Tab 2.1 lists the RMS noise voltage on a capacitor of different size. Depending on Tab 2.1 we could select a reasonable size of capacitor to limit the noise voltage.

2.6 Simulated Results

2.6.1 Opamp Simulated Results

Tab 2.2 shows the sizes of all transistors in this opamp. Fig 2.12 shows the gain and phase response of relationship between input and output when driving 0.25p capacitor loading. We see that DC gain (A₀) is about 552, unity gain frequency (f_t) is about 590MHz and phase margin (PM) is about 67 degree. Fig 2.13 shows the transfer curve that gives the information of output voltage swing range. The slope is sharpest between output voltages at -0.3V and 0.3V and this is what we call the output swing range. Fig 2.14 shows the transconductance (gm) of input differential pairs with different input common mode voltage. It can be observed that within the common mode range the transconductance would remain in the highest value and be more constant. We see that the input common mode range is between 0.85V and 1.65V.

2.6.1.1 Input-Referred Offset Voltage Simulation

When designing an analog circuit it is important to consider the process variation. The issue now is how to model the device size variation to be more approaching to reality. The approximate way is to model the device variation with the Gaussian distribution. Now we can model the device using the form as:

(

^,

)

P Gauss mean sigma= (2.12)

in which p could represent parameters of the device such as width, length, threshold voltage [10].

If we specify the standard deviation of Gaussian distribution well the simulated process variation approaches to the fabricated process variation. The standard deviation is specified according to device parameters of TSMC 0.35um technology. We model only the width of each device as the form in (2.12) and perform 200 Monte Carlo indices. Fig 2.15 shows the offset distributions over 200 Monte Carlo indices. We redraw it as the histogram shown in Fig 2.16 and obtain that the standard deviation of input-referred offset voltage (σ(V_os) ) is 0.34mV and the mean is -0.024mV.

This means that we will have 99.7% of input-referred offset voltage within 3σ(V_os) in fabrication.

Since only the width variation has been modeled the offset is much smaller than what we expect.

In general the input-referred offset is dominated mostly by the threshold mismatch of the input differential pairs. Finally, we summarize the performance of telescopic opamp in Tab 2.3.

2.6.2 Bootstrapped Switch Simulated Results

Tab 2.4 shows the sizes of all transistors in bootstrapped analog switch. We see that in Fig 2.17 the gate-source voltage of Mc-vgs remains a constant value. In (2.1) we see clearly that this leads to constant charge injection if the body effect is ignored and could be seen in Fig 2.18. In Fig 2.18 charge injection makes the negative voltage change but it is almost independent of voltage level.

Fig 2.19 shows the phase relationship between input and output and reveals the almost zero-phase shift up to 20MHz (Nyquist-rate frequency).

Now we take a look at sampled signal spectral to find the SFDR (Spurious Free Dynamic Range), which is the peak signal in the output spectrum to the largest spike in the output spectrum up to the Nyquist frequency [8]. We will consider two situations: (1) with the highest signal level (2.5V for single-ended), we see output spectrum at different input frequencies. Fig 2.20 shows the output spectrum at input frequency of about 20MHz and we see that SFDR is about 68dB. In constant input signal level of 2.5V, Fig 2.21 illustrates the SFDR values versus input frequency. (2)

at about input frequency of 20MHz, we see output spectrum at different input signal level (single-ended). Fig 2.20 illustrates the SFDR values versus input signal level.

2.6.3 Precharged SHA Simulated Results

The final design of precharged SHA is shown in Fig 2.23 and the remaining NMOS switch sizes are listed in Tab 2.5. For seeing the transient signal curve we use bootstrapped analog switches including S1, S2, S11, S12 to simulate the overall circuit. The simulated input and output signals are shown in Fig 2.24. Now we consider two situations that S₁, S₂, S₁₁, S₁₂ are bootstrapped switches or ideal switches to understand the importance of this analog switch. In the next section the input signal must meet the requirement of:

in sin s

f M

f = M (2.13) , where fs is sampling frequency, Msin is prime integer number of sinewave cycles and M is the number of samples. We take M=1024 samples in the following simulations. For example, if we want to input a signal near 1MHz we can select Msin=23, running 23 cycles of sinewave, to have fin=0.8984375MHz

2.6.3.1 Ideal-Switch Precharged SHA Simulated Results

In this section, we will consider the effects of either input signal level or input frequency respectively: (1) with the signal level of 4Vp-p (differential), we see the output spectrum at different input frequencies. Fig 2.25 shows the output spectrum at input frequency of about 20MHz and SFDR is 79dB. Fig 2.26 shows the SFDR values with 4Vp-p input voltage versus input frequency. (2) Fig 2.27 shows the SFDR values at input frequency of 20MHz versus input signal level.

2.6.3.2 Bootstrapped-Switch Precharged SHA Simulated Results

First, we take a look at the output frequency spectrum of SHA with the implementation of real transistors. Fig 2.28 shows a frequency spectrum when 4V_p-p and 20MHz input signal is presented and SFDR is about 73dB. In the same procedure as the last section, we will find out how signal level and frequency affect the SFDR value. (1) shown in Fig 2.29 is the SFDR values with signal level of 4Vp-p versus input frequency. (2) shown in Fig 2.30 is the SFDR values at input frequency of 20MHz versus input signal level.

2.6.4 Final Results and Discussions

The transient simulation in HSPICE doesn’t include the electronic noise, i.e. thermal noise, flicker noise, etc. We must take another way to look at how much noise affects the circuit. By using AC simulation in HSPICE we could integrate the total noise power in the bandwidth we interest. When in the sample mode the simulated RMS input-referred noise voltage up to noise equivalent bandwidth (NEB) is 0.285mV and 0.252mV when in the hold mode. Fig 2.28 shows that electronic-free SFDR is 73.88dB in full-range signal and also means that RMS distortion noise voltage is 0.286mV by using the formula:

( ) ( ) (

^{2 2}

)

²

, Vd, Vn and Voff are RMS noise voltages of distortion, electronic noise and offset due to process variations respectively and V_p is an amplitude of a sinewave [9]. Now it is intuitive to add these three noise powers together to obtain that the final electronic-included SFDR of SHA is 69.45dB [14].

The circuit is affected by many noise sources. Like those we presented are nonlinearity of devices and electronic noise. We should notice that the signal level and its frequency will provide the noise of nonlinearity because the transistors in opamp may be pushed into the triode region.

The electronic noise is independent of signal level and should be concerned in another way to really characterize the circuit performance by simulation. Finally, we use Tab 2.6 to summarize the performance of precharged SHA.

Fig 2.1 NMOS switch configuration

Fig 2.3 CMOS switch configuration

Fig 2.4 CMOS channel resistance versus input signal level

Fig 2.5 Precharged SHA configuration

Fig 2.6 Clock phases used in Precharged SHA

Fig 2.7 Telescopic opamp with continuous-time common mode feedback (CMFB) circuit

Fig 2.8 Precharged SHA in the hold mode and take some parasitic capacitors into account

Fig 2.9 Bootstrapped analog switch configuration

Fig 2.10 Linear phase response of first-order low pass filter

Fig 2.11 Channel resistance of M_c-vgs in bootstrapped analog switch versus input signal level

Fig 2.12 Gain and phase response of telescopic opamp

Fig 2.13 Input/Output transfer curve of telescopic opamp

Fig 2.14 Input common mode range of telescopic opamp

Fig 2.15 Simulated input-referred offset voltage over 200 Monte Carlo indices

Fig 2.16 Distribution of input-referred offset voltage of opamp

Fig 2.17 Control and input signals of bootstrapped analog switch

Fig 2.18 Input and output signals of bootstrapped analog switch

Fig 2.19 Phase response of bootstrapped analog switch

Fig 2.20 Frequency spectrum of bootstrapped analog switch when 2.5V and 20MHz single-ended input signal is presented

Fig 2.21 Simulated SFDR of bootstrapped analog switch at 2.5V input voltage versus input signal frequency

Fig 2.22 Simulated SFDR of bootstrapped analog switch at 20MHz input frequency versus input

在文檔中 低功率管線式類比數位轉換器的設計與分析 (頁 17-0)