CHAPTER 4
Pipelined Analog-to-Digital Converter
4.1 Clock Generator
In this section we discuss the clock generator that is a little different from some typical topologies. The clock generator is designed in the style of synchronous sequential circuit [22].
This kind of digital circuit is controlled by an external clock and must have an input signal to generate a designed output signal. In order to produce the clock pattern of ψ1 used in ADC, we input a signal pattern like:
input: 0 1 0 1 0 1 0 1 0 1 0 1 0 1 …..
, and the output we want should be:
output: 0 1 1 0 0 0 0 0 0 1 1 0 0 0……
The input signal is a 50% duty cycle, period of 6ns, square wave signal. We see that the output is high for one period (6ns) of input signal after the input experiences four periods. Now we can use state diagram to design the synchronous sequential circuit described above, but we will skip explaining this procedure because it is tedious and can be easily designed by Verilog HDL. Fig 4.1 shows the state diagram of this synchronous sequential circuit, and Tab 4.1 is the state-assigned table for Fig 4.1 in which we can derive all next-state outputs in terms of present-state inputs by using Karnaugh maps [23]. The final design of clock generatoris shown in Fig 4.2. in which the inverters are used as buffers [24] and the positive-trigger D flip-flop circuit is shown in Fig 4.3 [9][25]. Notice that in Fig 4.2 the external clock frequency is running at 333MHz.
4.2 ADC Design
4.2.1 Analog Path of ADC
In this section we will talk about how to integral all circuit blocks designed before to become a
functioning ADC. We divide the pipelined ADC into two parts, analog and digital, and the analog path had been described in the previous chapter. Fig 4.4 shows how the two consecutive MDAC are connected [4][5]. We see in Fig 4.4 that the additional switches are those connected to the opamp’s input. Also we observe that a pair of nonoverlapping clocks, ψ1 and ψ3 , are used in every two consecutive stages. As a result, we have odd stages clocked in ψ1 and even stages clocked in ψ3. Because we use the technique called opamp sharing, it slightly makes switch controlling complex.
As every two consecutive stages using one opamp we finally have the analog path shown in Fig 4.5 and it shows that only five opamps are needed. The first to the ninth stages totally solve 9 bits and the tenth stage has only one comparator to solve the final one bit.
4.2.2 Digital Path of ADC
In the previous section we knew that each stage have two comparators except for the final stage, so there are two bits produced by comparator banks in every stages. Now the question is how to combine these digital codes into one 10-bit digital number. We now put these codes into D flip-flops shown in Fig 4.3 in order to synchronize the signal. The detail in placing these D flip-flops is shown in Fig 4.6. By using this placement of D flip-flops we have a synchronous 19-bit output ready to enter the digital error correction (DEC) circuit.
Recall that in Chapter 3 we had the general form of MDAC’s transfer function in (3.8). We now apply (3.8) recursively, then the input of the entire pipelined ADC can be expressed as:
2 3 that we shift the digital number N bits to the right. Now it is obvious that how these 19 bit outputs are combined into 10-bit output. Fig 4.7 shows the algorithm of digital error correction with final
outputs of D0 to D9. Each block means one bit and we use full-adder to sum an overlapped bits and generates a carry to the next stage. We should notice that in the analog path the outputs are generated from left to right but in DEC circuit the outputs are generated from right to left.
4.3 Simulated Results
4.3.1 Clock Generator Simulated Results
In Fig 4.2 we indicated five clock outputs used in ADC. Notice that all clock signals except for ψ2 will drive lots of switches (large capacitive loading). Fig 4.8 shows the simulated clock signals driving capacitors of 8pF each. In Fig 4.8 the rise and fall time of clocks are 0.5ns. In MDAC the rise and fall time of clock signals are not much a concern since they process the sampled (stable) signals. While in SHA the clocks used to control S1, S2, S11 and S12 should have small rise time and fall time to avoid sampling uncertainty [15]. It is wise to build another specific clock generator for these analog-sampled switches. Finally Tab 4.2 summaries the final performance of this clock generator.
4.3.2 ADC Simulated Results
In this section we will simulate the frequency spectrum of ideal DAC’s output and characterize the linearity issue such as INL and DNL. If we want to see the frequency spectrum we have to place an ideal DAC behind the ADC we had designed. The entire block diagram is shown in Fig 4.9, where the DAC is modeled by HSPICE [9]. The transient simulated DAC’s output is shown in Fig 4.10. Apparently we see that the output has some delay because the latency through pipeline stages.
Now we put a 4Vp-p sinewave of 11.7578125MHz, which is running 301 periods and meets the requirement of (2.13), at the ADC’s input. After performing the Fast Fourier Transform (FFT) at DAC’s output we obtain the spectrum shown in Fig 4.11, where we have signal-to-noise plus distortion ratio (SNDR, which including quantization noise and distortion of devices) about
58.4dB. Here we should notice that the quantization noise in Fig 4.11 is the sum of noise voltage at each frequency [9]. If we increase the sampling frequency we actually lower the quantization noise floor but the total sum of noise voltage is unchanged. Now having the simulated SNDR we can use the formula written as:
1.76 6.02 ENOB SNDR−
= (4.2)
to calculate the effective number of bits (ENOB) when full-scaled input is presented. By substituting simulated SNDR of 58.4dB into (4.2) we obtain that ENOB is 9.41 bits.
Now we continue to discuss the issue of linearity. We often characterize the performance of linearity by using differential non-linearity (DNL) and integral non-linearity (INL). There are several methods to characterize these performances, while we use the method called code density testing or histogram testing [26]. Now we input a full-scaled sinewave of 0.8984375MHz, which is running 23 periods, into the system shown in Fig 4.9. By collecting 32768(32×210) consecutive data at DAC’s output, we can plot the histogram recording number of hits at each code number statistically shown in Fig 4.12. In Fig 4.12 we have simulated number of hits (Hsim(j)) from code 0 to code 2N-1. Using sinusoidal histogram code test we should find the offset, Vos and amplitude, VA first. Vos and VA can be express as:
and Nt is the total number we have sampled. Once we obtain the values from (4.3) to (4.6), we
to calculate the ideal number of hits for code j. The code width of the j-th code in units of LSbs is:
( ) ( )
Now we use all the data calculated in previous few equations and Matlab together to generate the DNL and INL plots illustrated in Fig 4.13. This figure shows that DNL is ranging from -0.37 LSB to 0.44 LSB and INL is ranging from -0.58 LSB to 0.63 LSB. DNL and INL requirements are much essential when using averaging at the output of ADC in the digital domain to increase the resolution. The averaging method can be referenced in [8][24][25] and it has a strong tradeoff between sampling frequency and resolution. Finally we summarize the performance in Tab 4.3
Fig 4.1 State diagram of clock generator
Fig 4.3 Positive-trigger D flip-flop
Fig 4.4 Two consecutive stages of MDAC using opamp sharing (a) sample phase in the first stage (b) amplification phase in the first stage
Fig 4.5 Analog path of pipelined ADC
Fig 4.6 Entire ADC architecture
Fig 4.7 Digital error correction structure
Fig 4.8 Simulated clock phases of synchronous sequential clock generator
Fig 4.9 Circuit connection for simulating ADC performance
Fig 4.10 Simulated DAC’s output signal from Fig 4.9
Fig 4.11 Simulated DAC’s output spectrum
Fig 4.12 Histogram of number of hits at each code number
Fig 4.13 Simulated INL and DNL Tab 4.1 State-assigned table for state diagram in Fig 4.1
Specification Performance External Clock Frequency 333MHz (duty cycle of 50%)
Input Cock Frequency 166MHz (duty cycle of 50%)
Generated Clock Frequency 41.67MHz
Power Consumption 31.72mW/13.47mW (PAA/PDD)
CMOS Technology TSMC 2P4M 0.35um
Tab 4.3 ADC performance summary