Chapter 2 Precharged Sample-and-Hold Amplifier
2.5 Capacitor Size Selection
Capacitors are very important in switch-capacitor circuits. Although a capacitor doesn’t contribute noise, the combination of resistors and capacitors contribute noise. In simple RC circuit we have RMS noise voltage of:
rms KT
V = C (2.11)
across the capacitor. It should be note that this noise voltage is independent of the value of resistance. We can decrease the KT/C noise by only increasing the value of C. For example, in (2.4) we can increase the value of the parallel combination of capacitors in denominator to keep the sampled RMS noise voltage under 1 LSB of ADC. Tab 2.1 lists the RMS noise voltage on a capacitor of different size. Depending on Tab 2.1 we could select a reasonable size of capacitor to limit the noise voltage.
2.6 Simulated Results
2.6.1 Opamp Simulated Results
Tab 2.2 shows the sizes of all transistors in this opamp. Fig 2.12 shows the gain and phase response of relationship between input and output when driving 0.25p capacitor loading. We see that DC gain (A0) is about 552, unity gain frequency (ft) is about 590MHz and phase margin (PM) is about 67 degree. Fig 2.13 shows the transfer curve that gives the information of output voltage swing range. The slope is sharpest between output voltages at -0.3V and 0.3V and this is what we call the output swing range. Fig 2.14 shows the transconductance (gm) of input differential pairs with different input common mode voltage. It can be observed that within the common mode range the transconductance would remain in the highest value and be more constant. We see that the input common mode range is between 0.85V and 1.65V.
2.6.1.1 Input-Referred Offset Voltage Simulation
When designing an analog circuit it is important to consider the process variation. The issue now is how to model the device size variation to be more approaching to reality. The approximate way is to model the device variation with the Gaussian distribution. Now we can model the device using the form as:
(
,)
P Gauss mean sigma= (2.12)
in which p could represent parameters of the device such as width, length, threshold voltage [10].
If we specify the standard deviation of Gaussian distribution well the simulated process variation approaches to the fabricated process variation. The standard deviation is specified according to device parameters of TSMC 0.35um technology. We model only the width of each device as the form in (2.12) and perform 200 Monte Carlo indices. Fig 2.15 shows the offset distributions over 200 Monte Carlo indices. We redraw it as the histogram shown in Fig 2.16 and obtain that the standard deviation of input-referred offset voltage (σ(Vos) ) is 0.34mV and the mean is -0.024mV.
This means that we will have 99.7% of input-referred offset voltage within 3σ(Vos) in fabrication.
Since only the width variation has been modeled the offset is much smaller than what we expect.
In general the input-referred offset is dominated mostly by the threshold mismatch of the input differential pairs. Finally, we summarize the performance of telescopic opamp in Tab 2.3.
2.6.2 Bootstrapped Switch Simulated Results
Tab 2.4 shows the sizes of all transistors in bootstrapped analog switch. We see that in Fig 2.17 the gate-source voltage of Mc-vgs remains a constant value. In (2.1) we see clearly that this leads to constant charge injection if the body effect is ignored and could be seen in Fig 2.18. In Fig 2.18 charge injection makes the negative voltage change but it is almost independent of voltage level.
Fig 2.19 shows the phase relationship between input and output and reveals the almost zero-phase shift up to 20MHz (Nyquist-rate frequency).
Now we take a look at sampled signal spectral to find the SFDR (Spurious Free Dynamic Range), which is the peak signal in the output spectrum to the largest spike in the output spectrum up to the Nyquist frequency [8]. We will consider two situations: (1) with the highest signal level (2.5V for single-ended), we see output spectrum at different input frequencies. Fig 2.20 shows the output spectrum at input frequency of about 20MHz and we see that SFDR is about 68dB. In constant input signal level of 2.5V, Fig 2.21 illustrates the SFDR values versus input frequency. (2)
at about input frequency of 20MHz, we see output spectrum at different input signal level (single-ended). Fig 2.20 illustrates the SFDR values versus input signal level.
2.6.3 Precharged SHA Simulated Results
The final design of precharged SHA is shown in Fig 2.23 and the remaining NMOS switch sizes are listed in Tab 2.5. For seeing the transient signal curve we use bootstrapped analog switches including S1, S2, S11, S12 to simulate the overall circuit. The simulated input and output signals are shown in Fig 2.24. Now we consider two situations that S1, S2, S11, S12 are bootstrapped switches or ideal switches to understand the importance of this analog switch. In the next section the input signal must meet the requirement of:
in sin s
f M
f = M (2.13) , where fs is sampling frequency, Msin is prime integer number of sinewave cycles and M is the number of samples. We take M=1024 samples in the following simulations. For example, if we want to input a signal near 1MHz we can select Msin=23, running 23 cycles of sinewave, to have fin=0.8984375MHz
2.6.3.1 Ideal-Switch Precharged SHA Simulated Results
In this section, we will consider the effects of either input signal level or input frequency respectively: (1) with the signal level of 4Vp-p (differential), we see the output spectrum at different input frequencies. Fig 2.25 shows the output spectrum at input frequency of about 20MHz and SFDR is 79dB. Fig 2.26 shows the SFDR values with 4Vp-p input voltage versus input frequency. (2) Fig 2.27 shows the SFDR values at input frequency of 20MHz versus input signal level.
2.6.3.2 Bootstrapped-Switch Precharged SHA Simulated Results
First, we take a look at the output frequency spectrum of SHA with the implementation of real transistors. Fig 2.28 shows a frequency spectrum when 4Vp-p and 20MHz input signal is presented and SFDR is about 73dB. In the same procedure as the last section, we will find out how signal level and frequency affect the SFDR value. (1) shown in Fig 2.29 is the SFDR values with signal level of 4Vp-p versus input frequency. (2) shown in Fig 2.30 is the SFDR values at input frequency of 20MHz versus input signal level.
2.6.4 Final Results and Discussions
The transient simulation in HSPICE doesn’t include the electronic noise, i.e. thermal noise, flicker noise, etc. We must take another way to look at how much noise affects the circuit. By using AC simulation in HSPICE we could integrate the total noise power in the bandwidth we interest. When in the sample mode the simulated RMS input-referred noise voltage up to noise equivalent bandwidth (NEB) is 0.285mV and 0.252mV when in the hold mode. Fig 2.28 shows that electronic-free SFDR is 73.88dB in full-range signal and also means that RMS distortion noise voltage is 0.286mV by using the formula:
( ) ( ) (
2 2)
2, Vd, Vn and Voff are RMS noise voltages of distortion, electronic noise and offset due to process variations respectively and Vp is an amplitude of a sinewave [9]. Now it is intuitive to add these three noise powers together to obtain that the final electronic-included SFDR of SHA is 69.45dB [14].
The circuit is affected by many noise sources. Like those we presented are nonlinearity of devices and electronic noise. We should notice that the signal level and its frequency will provide the noise of nonlinearity because the transistors in opamp may be pushed into the triode region.
The electronic noise is independent of signal level and should be concerned in another way to really characterize the circuit performance by simulation. Finally, we use Tab 2.6 to summarize the performance of precharged SHA.
Fig 2.1 NMOS switch configuration
Fig 2.3 CMOS switch configuration
Fig 2.4 CMOS channel resistance versus input signal level
Fig 2.5 Precharged SHA configuration
Fig 2.6 Clock phases used in Precharged SHA
Fig 2.7 Telescopic opamp with continuous-time common mode feedback (CMFB) circuit
Fig 2.8 Precharged SHA in the hold mode and take some parasitic capacitors into account
Fig 2.9 Bootstrapped analog switch configuration
Fig 2.10 Linear phase response of first-order low pass filter
Fig 2.11 Channel resistance of Mc-vgs in bootstrapped analog switch versus input signal level
Fig 2.12 Gain and phase response of telescopic opamp
Fig 2.13 Input/Output transfer curve of telescopic opamp
Fig 2.14 Input common mode range of telescopic opamp
Fig 2.15 Simulated input-referred offset voltage over 200 Monte Carlo indices
Fig 2.16 Distribution of input-referred offset voltage of opamp
Fig 2.17 Control and input signals of bootstrapped analog switch
Fig 2.18 Input and output signals of bootstrapped analog switch
Fig 2.19 Phase response of bootstrapped analog switch
Fig 2.20 Frequency spectrum of bootstrapped analog switch when 2.5V and 20MHz single-ended input signal is presented
Fig 2.21 Simulated SFDR of bootstrapped analog switch at 2.5V input voltage versus input signal frequency
Fig 2.22 Simulated SFDR of bootstrapped analog switch at 20MHz input frequency versus input
Fig 2.23 Precharged SHA with real transistor implementation, where the bootstrapped analog switches are shown in Fig 2.9
Fig 2.24 Transient simulation of a precharhed SHA with implementation of real transistors
Fig 2.25 Frequency spectrum of ideal-switch SHA at frequency of 20MHz and differential input of 4Vp-p
Fig 2.26 Simulated SFDR of ideal-switch SHA versus input signal frequency
Fig 2.27 Simulated SFDR of ideal-switch SHA versus input signal level
Fig 2.28 Frequency spectrum of bootstrapped-switch SHA at input frequency of 20MHz and differential input of 4Vp-p
Fig 2.29 Simulated SFDR of bootstrapped-switch SHA versus input signal frequency
Fig 2.30 Simulated SFDR of bootstrapped-switch SHA versus input signal level
Capacitor Value (KT/C)1/2 (T=343k)
Transistors Size Multiple
SFDR @ fin=20MHz and Vin=4Vp-p 69.45dB (including electronic noise)
Differential Input 4Vp-p
Supply Voltage 3V
Power Consumption 3.02mW
CMOS Technology TSMC 2P4M 0.35um
Tab 2.6 Precharged SHA performance summary
CHAPTER 3
Multiplying Digital-to-Analog Converter
3.1 Introduction to Multiplying Digital-to-Analog Converter (MDAC)
MDAC performs the function of quantification after signals are sampled. There are so many methods to quantize the analog signals and MADC is frequently used in pipelined ADC since it has advantages of low power and high speed. Recall that from Chapter 1 we listed the method that if we solve multiple bits in the first stage of pipelined ADC, then we could achieve low power circuit but may slow it down. To determine the numbers of bits solved in the first stage is a strong tradeoff between power and speed. A lot of designs would keep the design to be simple and radix-2 1.5-bit MDAC illustrated in Fig 3.1 is used to perform medium resolution and high speed [7]. We should note that solving multiple bits in the first stage does not always let the entire system be low power, since analog circuit therefore would be very difficult and even impossible to design. There are some properties we should know about radix-2 1.5-bit MDAC: (1) higher speed is required for opamp since the feedback factor (f=1/2) is small when amplification is two. (2) long latency for signals to pass through since we need 10 stages to perform 10-bit ADC. (3) small capacitors array are needed since the capacitors shown in Fig 3.1 are equal for amplification of two. (4) large numbers of opamps are needed since for a given resolution of ADC, each stage just solving one bit actually leads to 10 stages, i.e. ten opamps, if opamp sharing is not used.
In Fig 3.1 we see that we need the circuit components consisting of comparators, opamps and digital encoder. The following sections will show the design of these circuit components.
3.2 Differential Comparator Design
3.2.1 Differential Comparing Circuit Design
MDAC in Fig 3.1 needs two identical comparators with just their threshold voltages being set
differently, -1V (Vref+=0.5V, Vref-=2.5V) and 1V (Vref+=2.5V, Vref-=0.5V) respectively. Fig 3.2 shows the differential comparing circuit with the equivalence of four capacitors and performs the function described by the following equation:
/ 2
o i ref
V = −V V (3.1) ,which can be derived by the fact of charge conservation in two clock phases [7]. In ψ3 phase the circuit is connected like the one shown in Fig 3.3(a), in which reference voltages are sampled on capacitors. When in ψ1 phase the configuration change to connect input nodes to signals like the one shown in Fig 3.3(b). Then the charge will redistribute and lead to the output voltage in (3.1).
Capacitor sizes are chosen by considering KT/C noise (Tab 2.1), which must be smaller than 1 LSB when noises in each phase are added. For large signal to be passed, all of the switch symbols in Fig 3.2 are replaced by CMOS switches and is illustrated in Fig 3.4. When in ψ3 phase CMOS switches sizes are chosen according to Fig 3.3(a) to make sure that reference voltages are stable for a given time. When in ψ1 phase it follows the same way to determine the sizes of switches, but we should note that the charge injections are not the issue because the nodes X and Y see the high impedances.
3.2.2 Preamplifier Design
Now we continue to see the following two stages shown in Fig 3.5. In this figure the first stage is a simple differential amplifier with active loading. It is used to provide gain to enhance the input of latch for avoiding metastable problem [15]. It also can reduce the input-referred offset of latch and kickback noise [16][17]. Notice that the -3-dB frequency must be higher than input frequency and the gain should also have its proper value in order to tolerate temperature and process variations. The purpose with loading consisting of four p-type transistors is to ease the design of size for a given current [8], and essentially gm15 and gm16 should be smaller than gm13 and
3.2.3 Latch Design
The second stage in Fig 3.5 called latch is used to generate the digital outputs when M17 and M18 have unbalanced voltages apply to them. We should note that this action occurs when ψ1ba is going high, so it acts like positive edge trigger. The latch is very sensitive to random mismatches coming from process variation, so transistor sizes must be chosen carefully for small process variation, i.e, the larger size. Fortunately, radix-2 1.5-bit MDAC can tolerate 500mV (Vref/4) offset voltage if digital error correction circuit is used to combine comparator’s outputs [7][9].
3.3 Opamp Design
The two-stage opamp used in MDAC is shown in Fig 3.6. The main consideration here is that the output swing has to be at least 2Vp-p at each single side, so the second stage is mainly used to help increase the output swing. When designing the two-stage opamp the most difficult part is the compensation between the tradeoff of unity gain frequency and phase margin and also makes these two specifications reasonable. It is much easier to compensate when the first stage has cascode configuration. It is shown in Fig 3.6 that the compensation capacitors are connected between outputs and the sources of cascode transistors in order to eliminate the right-hand-plane (RHP) zero [18][19]. Now we move to determine some specifications of opamp to achieve the requirements. By seeing the configuration like Fig 3.7 we could use the equation written as:
1 1
to estimate the requirement of opamp’s DC gain. For close-loop gain accuracy being within 0.5 LSB we must meet the inequality written as:
For the left term of this inequality to be smaller than 0.5 LSB, we can easily obtain that the gain of 73dB is required when Cf=Cs=5Cp and N=10 are assumed. We then use the equations written as:
1 1 should be less than 0.1% of sampled voltage. Using (3.4), (3.5) to calculate the time constant needed for 0.1% settling accuracy and we obtain that unity gain frequency (ft) of 443MHz is required. We must notice that the beginning of settling behavior is nonlinear and is called the slew behavior. This means that the overall settling time includes both slew and small signal behaviors.
The slew rate is written as:
SR Iss
= Cc (3.6) , where Iss is the current flowing in Ms and Cc is the compensation capacitor. The higher the slew rate, the faster the speed that the circuit enters the small signal behavior, but just a waste of power.
The common mode feedback (CMFB) circuit is shown in Fig 3.8 [20]. When the circuit is stable, in ψ3 phase the desired voltage is stored on C3 and C4 and the opamp is performing its amplification. When in ψ1 phase the charge is then shared with C1 and C2 and keep the output voltages as desirable common mode voltages. In this figure Mcmc denotes MS and M9, M10 shown in Fig 3.6. Mcmc should be sized properly to accommodate the sum of currents flowing in current sources. The output common mode voltages are chosen by considering opamp’s DC characteristics, the two output common mode voltages chosen are also shown in Fig 3.6 (2V and 1.5V for the two stages respectively).
3.4 MDAC Design
Fig 3.9 shows the entire MDAC structure. The phase arrangement seems complicated and easily confused designers. We focus on phase arrangement first. Fig 3.10 shows the three phases used in MDAC. The ψ is used to positively trigger the comparators. It should be ensured that the
outputs of encoder come out after ψ1 is going low. When in ψ1 phase voltages sampled on Cf and Cs and in ψ3 phase the subtraction voltages (controlled by encoder) together with opamp and feedback capacitor Cf will operate the function written as:
1 the input-referred offset of opamp. We use Fig 3.11 to graphically illustrate the transfer function, where the dividing lines are at -1V and 1V (comparator’s threshold voltage). We also see that the matching of these two capacitors is important. According to Fig 3.11 and ignore the offset voltage we can write the general form of MDAC’s transfer function as:
( )
1 da
j j j j j
V + =G ×⎡⎣V V− D ⎤⎦ (3.8)
, where Gj is the gain of MDAC and Vjda(Dj) is the analog signal (-2V, 0V, 2V) corresponding to digital codes coming out of comparators. The linearity of MDAC is influenced the most by opamp while the switches are not much the issue. Making lots of efforts on designing opamp will improve MDAC’s performance and will be simulated in the next few sections.
3.5 Simulated Results
3.5.1 Differential Comparator Simulated Results
The sizes of transistors in comparator are shown in Tabs 3.1 and 3.2. First we should know how to set the reference voltage. In (3.1) we know that the threshold voltage is (Vref+-Vref-)/2. The output of the stage in Fig 3.2 satisfies (3.1). Fig 3.12(a) and Fig 3.12(b) are the simulated results that show the input /output transfer curve when threshold voltages are 1V and -1V respectively.
There is an important issue we should concern about, speed. The overdrive recovery is the ability that the comparator’s output should be changing fast enough when input signal level has
large amplitude transition [13]. Now we let the Vref+=2.5V and Vref-=0.5V, so the threshold voltage is 1V (Vref/2). Base on this initial setting we inputs the discreet-time signal sequence: {2V, 0.99V, 2V, 0.99V, -2V, 1.01V, -2V, 1.01V}, then we should obtain the digital output sequence: {1, 0, 1, 0, 0, 1, 0, 1}. Fig 3.13 shows the simulated waveforms which meet the requirement stated above.
3.5.1.1 Input-Referred Offset Voltage Simulation
The comparator is very sensitive to process variation although it is not much the issue in this design. The process variation would make the threshold voltage deviate seriously. Make sure that 3σ(Vos) is a tolerable value is important. To simulate the offset voltage we also only model all the widths of the transistors and values of capacitors with variations in the form of Gaussian distribution. A little different from what we did in the last chapter is that we have to see the transient behavior in each Monte Carlo index. First we set the threshold voltage at 1V and input a constant voltage (assuming 0.99V) during the hold mode of SHA, then we simulate 600 Monte Carlo indices to see how many times the output is digital one. There is an assumption that the input-referred offset voltage has Gaussian distribution with mean of 1V and unknown standard deviation. Fig 3.14 is the histogram of simulated output voltages, where we have 31.12% of samples are digital one.
We use X~P(μ,σ2)=P(1v, σ2) to denote the statements above, where σ is the standard deviation we want to obtain. Now we have P(X<0.99V)=0.3112. In order to consult the standard normal
We use X~P(μ,σ2)=P(1v, σ2) to denote the statements above, where σ is the standard deviation we want to obtain. Now we have P(X<0.99V)=0.3112. In order to consult the standard normal