CHAPTER 3
Multiplying Digital-to-Analog Converter
3.1 Introduction to Multiplying Digital-to-Analog Converter (MDAC)
MDAC performs the function of quantification after signals are sampled. There are so many methods to quantize the analog signals and MADC is frequently used in pipelined ADC since it has advantages of low power and high speed. Recall that from Chapter 1 we listed the method that if we solve multiple bits in the first stage of pipelined ADC, then we could achieve low power circuit but may slow it down. To determine the numbers of bits solved in the first stage is a strong tradeoff between power and speed. A lot of designs would keep the design to be simple and radix-2 1.5-bit MDAC illustrated in Fig 3.1 is used to perform medium resolution and high speed [7]. We should note that solving multiple bits in the first stage does not always let the entire system be low power, since analog circuit therefore would be very difficult and even impossible to design. There are some properties we should know about radix-2 1.5-bit MDAC: (1) higher speed is required for opamp since the feedback factor (f=1/2) is small when amplification is two. (2) long latency for signals to pass through since we need 10 stages to perform 10-bit ADC. (3) small capacitors array are needed since the capacitors shown in Fig 3.1 are equal for amplification of two. (4) large numbers of opamps are needed since for a given resolution of ADC, each stage just solving one bit actually leads to 10 stages, i.e. ten opamps, if opamp sharing is not used.
In Fig 3.1 we see that we need the circuit components consisting of comparators, opamps and digital encoder. The following sections will show the design of these circuit components.
3.2 Differential Comparator Design
3.2.1 Differential Comparing Circuit Design
MDAC in Fig 3.1 needs two identical comparators with just their threshold voltages being set
differently, -1V (Vref+=0.5V, Vref-=2.5V) and 1V (Vref+=2.5V, Vref-=0.5V) respectively. Fig 3.2 shows the differential comparing circuit with the equivalence of four capacitors and performs the function described by the following equation:
/ 2
o i ref
V = −V V (3.1) ,which can be derived by the fact of charge conservation in two clock phases [7]. In ψ3 phase the circuit is connected like the one shown in Fig 3.3(a), in which reference voltages are sampled on capacitors. When in ψ1 phase the configuration change to connect input nodes to signals like the one shown in Fig 3.3(b). Then the charge will redistribute and lead to the output voltage in (3.1).
Capacitor sizes are chosen by considering KT/C noise (Tab 2.1), which must be smaller than 1 LSB when noises in each phase are added. For large signal to be passed, all of the switch symbols in Fig 3.2 are replaced by CMOS switches and is illustrated in Fig 3.4. When in ψ3 phase CMOS switches sizes are chosen according to Fig 3.3(a) to make sure that reference voltages are stable for a given time. When in ψ1 phase it follows the same way to determine the sizes of switches, but we should note that the charge injections are not the issue because the nodes X and Y see the high impedances.
3.2.2 Preamplifier Design
Now we continue to see the following two stages shown in Fig 3.5. In this figure the first stage is a simple differential amplifier with active loading. It is used to provide gain to enhance the input of latch for avoiding metastable problem [15]. It also can reduce the input-referred offset of latch and kickback noise [16][17]. Notice that the -3-dB frequency must be higher than input frequency and the gain should also have its proper value in order to tolerate temperature and process variations. The purpose with loading consisting of four p-type transistors is to ease the design of size for a given current [8], and essentially gm15 and gm16 should be smaller than gm13 and
3.2.3 Latch Design
The second stage in Fig 3.5 called latch is used to generate the digital outputs when M17 and M18 have unbalanced voltages apply to them. We should note that this action occurs when ψ1ba is going high, so it acts like positive edge trigger. The latch is very sensitive to random mismatches coming from process variation, so transistor sizes must be chosen carefully for small process variation, i.e, the larger size. Fortunately, radix-2 1.5-bit MDAC can tolerate 500mV (Vref/4) offset voltage if digital error correction circuit is used to combine comparator’s outputs [7][9].
3.3 Opamp Design
The two-stage opamp used in MDAC is shown in Fig 3.6. The main consideration here is that the output swing has to be at least 2Vp-p at each single side, so the second stage is mainly used to help increase the output swing. When designing the two-stage opamp the most difficult part is the compensation between the tradeoff of unity gain frequency and phase margin and also makes these two specifications reasonable. It is much easier to compensate when the first stage has cascode configuration. It is shown in Fig 3.6 that the compensation capacitors are connected between outputs and the sources of cascode transistors in order to eliminate the right-hand-plane (RHP) zero [18][19]. Now we move to determine some specifications of opamp to achieve the requirements. By seeing the configuration like Fig 3.7 we could use the equation written as:
1 1
to estimate the requirement of opamp’s DC gain. For close-loop gain accuracy being within 0.5 LSB we must meet the inequality written as:
For the left term of this inequality to be smaller than 0.5 LSB, we can easily obtain that the gain of 73dB is required when Cf=Cs=5Cp and N=10 are assumed. We then use the equations written as:
1 1 should be less than 0.1% of sampled voltage. Using (3.4), (3.5) to calculate the time constant needed for 0.1% settling accuracy and we obtain that unity gain frequency (ft) of 443MHz is required. We must notice that the beginning of settling behavior is nonlinear and is called the slew behavior. This means that the overall settling time includes both slew and small signal behaviors.
The slew rate is written as:
SR Iss
= Cc (3.6) , where Iss is the current flowing in Ms and Cc is the compensation capacitor. The higher the slew rate, the faster the speed that the circuit enters the small signal behavior, but just a waste of power.
The common mode feedback (CMFB) circuit is shown in Fig 3.8 [20]. When the circuit is stable, in ψ3 phase the desired voltage is stored on C3 and C4 and the opamp is performing its amplification. When in ψ1 phase the charge is then shared with C1 and C2 and keep the output voltages as desirable common mode voltages. In this figure Mcmc denotes MS and M9, M10 shown in Fig 3.6. Mcmc should be sized properly to accommodate the sum of currents flowing in current sources. The output common mode voltages are chosen by considering opamp’s DC characteristics, the two output common mode voltages chosen are also shown in Fig 3.6 (2V and 1.5V for the two stages respectively).
3.4 MDAC Design
Fig 3.9 shows the entire MDAC structure. The phase arrangement seems complicated and easily confused designers. We focus on phase arrangement first. Fig 3.10 shows the three phases used in MDAC. The ψ is used to positively trigger the comparators. It should be ensured that the
outputs of encoder come out after ψ1 is going low. When in ψ1 phase voltages sampled on Cf and Cs and in ψ3 phase the subtraction voltages (controlled by encoder) together with opamp and feedback capacitor Cf will operate the function written as:
1 the input-referred offset of opamp. We use Fig 3.11 to graphically illustrate the transfer function, where the dividing lines are at -1V and 1V (comparator’s threshold voltage). We also see that the matching of these two capacitors is important. According to Fig 3.11 and ignore the offset voltage we can write the general form of MDAC’s transfer function as:
( )
1 da
j j j j j
V + =G ×⎡⎣V V− D ⎤⎦ (3.8)
, where Gj is the gain of MDAC and Vjda(Dj) is the analog signal (-2V, 0V, 2V) corresponding to digital codes coming out of comparators. The linearity of MDAC is influenced the most by opamp while the switches are not much the issue. Making lots of efforts on designing opamp will improve MDAC’s performance and will be simulated in the next few sections.
3.5 Simulated Results
3.5.1 Differential Comparator Simulated Results
The sizes of transistors in comparator are shown in Tabs 3.1 and 3.2. First we should know how to set the reference voltage. In (3.1) we know that the threshold voltage is (Vref+-Vref-)/2. The output of the stage in Fig 3.2 satisfies (3.1). Fig 3.12(a) and Fig 3.12(b) are the simulated results that show the input /output transfer curve when threshold voltages are 1V and -1V respectively.
There is an important issue we should concern about, speed. The overdrive recovery is the ability that the comparator’s output should be changing fast enough when input signal level has
large amplitude transition [13]. Now we let the Vref+=2.5V and Vref-=0.5V, so the threshold voltage is 1V (Vref/2). Base on this initial setting we inputs the discreet-time signal sequence: {2V, 0.99V, 2V, 0.99V, -2V, 1.01V, -2V, 1.01V}, then we should obtain the digital output sequence: {1, 0, 1, 0, 0, 1, 0, 1}. Fig 3.13 shows the simulated waveforms which meet the requirement stated above.
3.5.1.1 Input-Referred Offset Voltage Simulation
The comparator is very sensitive to process variation although it is not much the issue in this design. The process variation would make the threshold voltage deviate seriously. Make sure that 3σ(Vos) is a tolerable value is important. To simulate the offset voltage we also only model all the widths of the transistors and values of capacitors with variations in the form of Gaussian distribution. A little different from what we did in the last chapter is that we have to see the transient behavior in each Monte Carlo index. First we set the threshold voltage at 1V and input a constant voltage (assuming 0.99V) during the hold mode of SHA, then we simulate 600 Monte Carlo indices to see how many times the output is digital one. There is an assumption that the input-referred offset voltage has Gaussian distribution with mean of 1V and unknown standard deviation. Fig 3.14 is the histogram of simulated output voltages, where we have 31.12% of samples are digital one.
We use X~P(μ,σ2)=P(1v, σ2) to denote the statements above, where σ is the standard deviation we want to obtain. Now we have P(X<0.99V)=0.3112. In order to consult the standard normal distribution table we should standardize P(X<0.99V)=0.3112 to P[Z<(0.99v-1V)/σ]=0.3112 [21].
We then consult the table reversely, and obtain that the probability of 0.3112 lies in the range of -0.5<Z<-0.49. We choose -0.495 for simplicity. Then we can easily solve the equation of (0.99V-1V) /σ =-0.495 to obtain that σ=20.2mV. Tab 3.3 is the summary of the comparator’s performance.
3.5.2 Opamp Simulated Results
Tab 3.4 shows the transistor sizes of two-stage opamp and Tab 3.5 shows the switch sizes of CMFB. Fig 3.15 shows the frequency response of opamp. The dc gain of 5887 (75dB), unity gain frequency of 484MHz and phase margin of 70 degree can be read. Fig 3.16 shows the input common mode range by simulating the transconductance (gm) of input differential pairs. In this figure we see that the transconductance is much stable between 1.2V and 1.8V.
Fig 3.17 shows the settling behavior by inputting a voltage pulse when the unity feedback is formed. This figure tells that the slew rate is about 0.3V/ns and it takes about 5ns including slew and small signal behavior for 0.1% settling accuracy. Since the dynamic CMFB is used, the output common mode voltage is seen in Fig 3.18 by transient simulation. We can clearly see the voltage settling behavior and that its final stable voltage is 1.487V.
Now we model each transistor’s size as Gaussian distribution to simulate the offset voltage.
When there is no input signal the output differential voltage should be zero except that process variation exists. By simulating 200 Monte Carlo indices we can see 200 windows like the one shown in Fig 3.18 (where both the output voltages are 1.487V so the differential voltage is 0V) except that the stable differential voltage is not zero. We sample 200 stable voltages in these 200 windows and plot it as a histogram in Fig 3.19. In Fig 3.19 the standard deviation of output offset voltage is 0.61V and mean is -8mV. If what we want is input-referred offset voltage we divide it by DC gain of this opamp by ensuring that the outputs haven’t saturated in advanced. The standard deviation of input-referred offset voltage is then 0.104mV. This offset voltage is not the issue because in (3.7) we see that it just be amplified by two. Finally we use Tab 3.6 to summarize the performance of two-stage opamp.
3.5.3 MDAC Simulated Results
The MDAC is the system that processes the discreet-time signals. If we put the stairs-like voltage from -3V to 3V, we will get the output voltage we want like Fig 3.11. Tab 3.7 shows the switch sizes of MDAC. The simulated output of MDAC is shown in Fig 3.20 and it is pretty like a
one shown in Fig 3.11. If we want to see how the output of MDAC will be when sinewave signal entering the SHA, we connect two stages including SHA and the first stage of MDAC like the one shown in Fig 3.21 and use an ideal switch modeled by HSPICE to sample the settled signals (SW is high when MDAC’s outputs are settled). Fig 3.22 shows the simulated waveform at ideal switch’s (SW) output and it is consistent with the function shown in Fig 3.20. Now we should continue to check that whether the step heights in each step are equal or not. The equality of step heights means good linearity of the MDAC. Let us assume that no mismatch is presented and rewrite (3.8) if some noise and distortion are involved, then it can be written as:
( )
1 ( ) os .
j j j j j
V + = V Vr D− −V G (3.9)
, where Vjos means an unwanted noise including process variation, electronic noise and devices nonlinearity (in HSPICE transient simulation the electronic noise has not been included) and Gj is still two since we lump all the noises into Vjos. Solving Vjos in (3.9) and renames it by INL, then
’s are the simulated outputs in Fig 3.20. Fig 3.23 shows the values obtained from (3.10) and they are called integral-non-linearity (INL) error. We see that INLmax is 0.25 LSB and INLmin is -0.32 LSB. Generally, the INL errors less than 0.5 LSB are tolerable values.
Fig 3.1 A radix-2 1.5-bit switch-capacitor pipeline stage configuration
Fig 3.2 Differential comparing circuit
(a) (b)
Fig 3.3 Circuit connection in two phases (a) Sample the reference voltages on capacitors (b) Sample the signal voltages on capacitors
Fig 3.4 Differential comparing circuit with implementation of real transistors
Fig 3.5 Preamplifier and latch configurations
Fig 3.6 Two-stage opamp structure with two dynamic common mode feedback (CMFB) circuits.
Fig 3.7 Simplicity of a differential ×2 amplifier used for understanding the gain and speed requirements of opamp
Fig 3.8 Common mode feedback (CMFB) used in two-stage opamp
Fig 3.9 MDAC configuration
Fig 3.10 Clock phases used in MDAC
Fig 3.11 Transfer curve of MDAC
(a)
(b)
Fig 3.12 Simulated transfer curves when threshold voltage is (a)1V (b)-1V
Fig 3.13 Digital output of comparator when input is a certain signal pattern
Fig 3.14 Statistics of comparator’s output voltage over 600 Monte Carlo indices
Fig 3.15 Gain response and phase response of two-stage opamp
Fig 3.16 Transconductance of input differential pairs versus input common mode voltage
Fig 3.17 Transient simulation when unity-gain feedback is connected
Fig 3.18 Transient simulation of output common mode voltage
Fig 3.19 Simulated output offset voltage of two-stage opamp over 200 Monte Carlo indices
Fig 3.20 Simulated transfer curve of MDAC
Fig 3.21 Block diagram for catching the settled signal of MDAC’s output
Fig 3.22 Input and output signals of the circuit diagram shown in Fig 3.21
Fig 3.23 INL error of MDAC’s transfer function
Switch Type Size
S1, S2, S3, S4 CMOS NMOS:L=0.35u W=10u
PMOS: L=0.35u W=40u
S5 NMOS L=0.35u W=4u
Tab 3.1 Switch sizes of comparing circuit
Transistor Size Multiple
M11=M12 L=0.35u W=2u m=12
M13=M14 L=0.35u W=0.5u m=8
M15=M16 L=0.35u W=0.5u m=7
M17=M18 L=0.35u W=2u m=2
M19=M20 L=0.35u W=2u m=1
M21=M22=M23=M24 L=0.35u W=2u m=2
M25 L=1u W=2u m=6
M26 L=1u W=2u m=6