Chapter 1 Introduction
1.5 Organization of the Thesis
There are five chapters in this thesis. The overviews of nanowire technology, SONOS and nanocrystal NVM are presented in this chapter. The fabrication of NW-SONOS memory devices with embedded silicon nanocrystal are described in detail in Chapter 2. The measured data, such as P/E speed and reliability characteristics, are presented and discussed in Chapter 3. In Chapter 4, operation mechanisms about SONOS and comparisons regarding with/without embedded silicon nanocrystal devices are presented. Finally, we summarize the conclusions, and future works are suggested in Chapter 5.
Chapter 2 Device Fabrication
Two types of devices were fabricated and studied in this thesis. The first one is poly-Si NW SONOS memory. The other is planar thin-film transistor (TFT) SONOS memory. We compared the characteristics of SONOS from different channel structures. Differing from the bottom-up and top-down approaches, we employed the simple and low cost method recently developed by our group to fabricate NW devices [37-39]. Besides, we also adopted two different SONOS formation techniques, i.e., with and without embedded silicon nanocrystals (Si NCs), and studied their impacts on the devices. Furthermore, the positions of Si NCs were split into three parts, i.e., in the medium of nitride or at the interface of nitride and oxide. The detail of these process procedures are described in this chapter. Finally, we also briefly introduced some important mechanisms of SONOS memory operation, including P/E speed, data retention and endurance.
2.1 Structure and Fabrication of Nanowire SONOS Devices
Figure 2-1(a) shows the top view of the NW SONOS memory device. The dashed lines in the block of gate are the positions of NWs, which are located at the left and right sides of the gate, respectively. Fig. 2-1(b) shows the cross-sectional view along line AB in Fig.2-1(a) and the definition of NW channels thickness and width. It can be seen that the two rectangular-shaped poly-Si NW channels are embedded in the gate electrode.
Fabrication flow of the NW SONOS is illustrated in Fig. 2-2(a) ~ (h). The process of all devices in this work began on 6-inch wafers capped with a 250 nm silicon dioxide. First, an 80 nm bottom nitride layer was deposited by low pressure chemical vapor deposition (LPVCD). Next a 50 nm TEOS and 30 nm nitride (hard mask layer) were stacked sequentially as shown in Fig. 2-2(a). Then, the hard mask and TEOS oxide layers were patterned by anisotropic reactive plasma etching [Fig.
2-2(b)]. Note that the etching time should be carefully controlled because of low selectivity between nitride and TEOS. In the subsequent step, diluted HF (DHF) solution was used for lateral etching of TEOS oxide because of its high selectivity to nitride. Rectangular-shaped cavities were formed at the two sides of these patterns [Fig. 2-2(c)]. The dimension of cavities, which affects the size of NW, depends on the time of the TEOS lateral etching step and the thickness of TEOS oxide layer. Briefly, the thicker the TEOS oxide film or the longer the lateral etching time, the larger the cavities. Excellent filling capacity is a well-known feature of LPCVD process. By utilizing this merit of LPCVD, a 100 nm undoped amorphous silicon (a-Si) was deposited and the cavities formed in last step could be completely refilled by a-Si. To transform the a-Si into polycrystalline phase, solid phase crystallization (SPC) process was performed at 600 ℃ in N2 ambient for 24 hours [Fig. 2-2(d)]. Next, source and
drain (S/D) implant was carried out by P+ implantation with a dose of 5×1015 cm-2 and an energy of 25 keV. Since the process temperature of gate dielectric and poly-Si film depositions were higher than 700 ℃ and the time was sufficient for dopant activation, no additional S/D dopant activation step was necessary. Subsequently, the S/D photoresist patterns were defined by standard I-line lithography step, followed by an anisotropic plasma etching step to remove poly-Si not protected by the hard mask.
The over-etching time in this step was prolonged to completely clean the sidewall,
which might otherwise affect the nanowire formation in the subsequent step.
Protecting by the hard mask film in the dry etching step, poly-Si that filled the previously-existing cavities would be left intact and the NW channels were formed simultaneously [Fig. 2-2(e)]. To achieve the gate-all-around (GAA) structure, NWs must be suspended in the midair before the deposition of gate dielectric layers.
Therefore, the bottom nitride, TEOS and hard mask should be removed entirely. The remaining nitride hard mask was etched by H3PO4 after the poly-Si etching. By continuously removing the TEOS and bottom nitride layers by DHF and H3PO4, NWs were hanged in the air [Fig. 2-2(f)]. To fabricate SONOS memory, oxide-nitride-oxide (ONO) stack was used as gate dielectric. For the standard SONOS device, the three layers in the ONO stack were deposited sequentially consisting of a 3 nm TEOS as the tunneling oxide, 8 nm nitride as the trapping layer and a 11 nm TEOS as the blocking layer [Fig 2-2(g)]. For the SONOS memory with embedded Si NCs, the trapping layer was composed of nitride and Si-NCs and the process will be described in Section 2.3. Afterwards, a 150 nm in-situ-doped n+ poly-Si was deposited and patterned as the gate electrode [Fig. 2-2(h)]. Finally, all devices were capped with a 350 nm TEOS as a passivation layer. Contact holes and test pads were formed with a standard metallization scheme.
Figure 2-3 displays the TEM image of an NW SONOS memory device along line AB is illustrated in Fig 2-1(a). The sizes of channel height and thickness are approximately 15 nm. According to the color contrast in the gate dielectric, the ONO layer can be recognized clearly and the dark region corresponds to the nitride layer. In this study, we fabricate four different dimensions NW SONOS names S1, S2, S3 and S4 and list their conditions in Table I. S1 and S4 are the thickest and thinnest, respectively, and their TEM images are shown in Fig. 2-4.
2.2 Structure and Fabrication of Planar SONOS Devices
Planar SONOS devices were fabricated and characterized for comparison with the NW SONOS devices in this study. Figure 2-5 shows the top view of the NW SONOS memory device. The fabrication flow was similar to that of conventional TFTs and would be described here. First, the process started with bare silicon substrate capped with a 250 nm wet oxide layer. A 100 nm undoped a-Si film was then deposited and annealed at 600 ℃ in N2 ambient for 24 hours to transform the a-Si into poly-Si [Fig. 2-6(a)]. Subsequently, the channel and S/D photoresist patterns were defined by a standard I-line lithography step. Next an anisotropic plasma etching was performed to remove poly-Si not protected by photoresist [Fig. 2-6(b)].
Afterwards, the gate dielectric consisting of an ONO stack of 3/8/11 nm was deposited for the standard SONOS devices [Fig. 2-6(c)]. While the process of SONOS memory with embedded Si NCs in the nitride layer will be described in Section 2.3.
Next, the gate electrode formation and self-aligned S/D implant with a dose of 5×1015 cm-2 and an energy of 20 keV were carried out [Fig. 2-6(d)]. Finally, all devices were passivated with a 350 nm TEOS layer and the formation of contact holes was similar to the NW devices [Fig 2-6(e)]. There is no need for another annealing step because the process temperature of passivation layer deposition was high enough and the time was sufficiently long for dopant activation.
2.3 In-Situ Embedded Silicon Nanocrystals
In this study, the in-situ embedded Si NCs structures were split into three groups based on the locations of Si NCs. For the first split, denoted as the bottom Si NCs, the Si NCs were located at the interface of tunneling oxide and nitride layer [Fig. 2-7(a)].
The second split was denoted as the mid Si NCs, in which the Si NCs were embedded in the nitride layer [Fig. 2-8(a)]. The split with the location of Si NCs situated between the nitride and blocking oxide was denoted as the top Si NCs [Fig. 2-9(a)]. In the next paragraph, we will precisely describe the recipe of mid Si NCs, which is the most complex process among the three splits.
As shown in Fig 2-8(b), the mid Si NCs process includes three steps including bottom nitride, Si NCs and the top nitride. In the first step, LPCVD system was performed to deposit the 4 nm-thick bottom nitride film by using dichlorosilane (SiCl2H2 65-sccm) and ammonia (NH3 15-sccm) gases at 780 ℃. After the deposition of bottom nitride, Si NCs were formed in the same tube and at the same temperature.
By turning off the NH3 gas and increasing the flow rate of the SiCl2H2 to 100sccm, the Si NCs were in-situ deposited on the wafers. SiCl2H2 was a common gas source for the silicon layer deposition. Before the silicon film formation, silicon would nucleate and formed the Si NCs. Finally, by turning on the NH3 gas again, a 4 nm top nitride was capped on the Si NCs in the same tube. The change of gas flow rate of SiCl2H2 and NH3 during the mid Si NCs process is illustrated in Fig. 2-8(b). Figure 2-7(b) and Fig. 2-9(b) show the steps of bottom Si NCs and top Si NCs, respectively.
The density and size of Si NCs will depend on the deposition time of SiCl2H2. To verify the effects of the deposition time, we used the atomic force microscope (AFM) to examine the Si NCs on nitride. Figure 2-10 shows the AFM surface morphologies of Si NCs on nitride with four deposition conditions. Figure 2-10(a) is the bare nitride without Si NCs, which serves as the control sample. The four conditions differed in the SiCl2H2 deposition time, i.e., 20, 30, 45 and 60 seconds, respectively. The white spots are the relative higher point in the film. Figure 2-11 displays the top view of scanning electron microscopy (SEM) image of the nitride film without and with Si
NCs for a deposition time of 45 seconds. It is obviously that with Si NCs, the surface becomes more roughness than the nitride film. Figure 2-12 is the cross-sectional TEM image of Si NCs. The crystal structure is embedded in the nitride layer. Figure 2-13.
depicts the TEM image of mid Si NCs device. The dark region in ONO is the nitride layer and some lighter dots are embedded in nitride which correspond to the Si NCs.
2.4 The Measurement Setup
The experimental setup for the measurement of I-V characteristics consists of a semiconductor parameter analyzer-HP4156, a pulse generator Agilent-81110A, low leakage switch mainframe Agilent-E5250A and a Visual Engineering Environment (VEE). These equipments are controlled by the interactive characterization software (ICS) program. An exsiccator and a temperature regulator heater are used to keep the humidity and temperature at the same level.
The HP-4156 provides a high current resolution to pico-ampere range for the current measurement. The Agilent-81110A with high timing resolution generates the pulse for transient and P/E characteristics. The Agilent-E5250A switches the signal from the HP-4156 and the Agilent-81110A to the device automatically.
2.5 Program/Erase Mechanisms of SONOS Flash Memory
The basic mechanism behind the program and erase operations of SONOS is the charges transport through the tunnel dielectric. There are many charge transport mechanisms that can explain the operation behaviors of SONOS. In the following we will discuss these mechanisms of SONOS, including Fowler-Nordheim (FN) tunneling, direct tunneling, channel hot electron injection, and band-to-band tunneling.
2.5.1 Fowler-Nordheim (FN) Tunneling
FN tunneling [40] is a charge transport mechanism which depends on the gate stack composition and the applied voltage. The energy band diagram of electron injection from Si substrate to nitride under FN tunneling is illustrated in Fig. 2-14(a), in which Φ1 is the tunneling oxide barrier height for electron. FN tunneling occurs
where tox is the thickness of the oxide. The electrons may tunnel through a triangular energy barrier with a width dependent on the applied bias. The FN current density through the oxide can be describe as
free electron and mox is the effective mass of an electron in the oxide. Eq. 2-1 is the simplest formation of FN tunneling which doesn’t take into account the influence of temperature and image force barrier lowering.According to the aforementioned equations, the FN tunneling current is affected by the Eox rather than the thickness of the oxide. With the same Eox, the FN current densities are the same even through the oxide thickness is different.
2.5.2 Direct Tunneling (DT)
conduction band into the conduction band of nitride directly. The barrier width is the oxide thickness. The current density of DT can be written as
suitable for floating-gate type flash memory applications.2.5.3 Channel Hot Electrons Injection
Non-uniform injection has been proposed to operate the SONOS memory. Since it has discrete traps in the trapping layer, two-bit-per-cell operation is allowed by
using non-uniform injection. Channel hot electrons injection (CHEI) [42] has been widely used for non-volatile memory application. Figure 2-15 depicts the CHEI phenomenon for NMOS. While the transistor is biased under sufficiently high gate voltage (VG) and drain voltage (VD) and VD≧VDSAT = VG – Vth, pinch-off occurs close to drain region. The major voltage drop along the channel takes place in the pinch-off region and induces a large lateral electric field wherein. In this region, minority carriers are accelerated and gain a lot of energy, which are known as hot electrons. These hot electrons cause impact ionization and generate majority and minority carriers. The majority carriers are mostly collected and form the substrate current. The minority carriers drift into drain and contribute to drain current. Under a vertical oxide field, a fraction of highly energetic electrons would overcome the potential barrier and inject into the gate dielectric, which is so-called hot carrier injection gate current. These injected electrons will be locally trapped into the nitride layer near the drain side in SONOS memory.
2.5.4 Band-to-Band Tunneling
The mechanism of BTBT is illustrated in Fig. 2-16, which occurs in the overlap region of gate and n+ drain region. When a positive bias is applied to the drain and a highly negative gate bias will induced a deep depletion region in the n+ area next to the interface of oxide and silicon. Serious band bending in the deep depletion region will promote electrons to tunnel from valance band into conduction band.
Simultaneously, holes will be left in the valence band. Portion of these holes may gain enough energy to overcome the oxide barrier and inject into gate oxide, contributing to the gate leakage current. In SONOS memory, these hot holes will inject into the nitride trapping layer and recombine with the electrons.
2.5.5 Program/Erase Operation Principles
For P/E operation in flash memory devices, there are several approaches just as mentioned in previous sections. Since the channel of our device is formed with poly-Si, grain boundaries may scatter electrons when they are transporting in the channel. Therefore, these electrons are difficult to gain sufficient energy to become hot electrons. For this reason, CHEI is not a suitable method for programming operation in our device. In this study, FN tunneling is employed for P/E operation in the poly-Si NW SONOS devices. For programming operation, both source and drain are grounded and a positive voltage is applied to the gate to induce a large electric field across the gate dielectric. Electrons in the channel will tunnel through the thin tunneling oxide and captured by the traps in the nitride layer. For erasing operation, both source and drain are grounded and a negative voltage is applied to the gate. High electric field causes some holes to inject into nitride or the trapped electrons to de-trap to the channel.
2.6 Reliability of SONOS Flash Memory
Reliability of the nonvolatile flash memory is a crucial issue for practical application. In the following, we will briefly introduce the two important topics of reliability, namely, data retention and endurance.
2.6.1 Retention
Data retention refers to the ability to keep the storage charges in the trapping layer and provide enough difference of logic level that can be distinguished. A memory window larger than 0.5V after ten years is necessary for commercial
products.
Figure 2-17 depicts the migration paths of the trapped charge, including thermal excitation, Frenkel-Poole emission, trap-to-trap tunneling, band-to-trap tunneling, and trap-to-band tunneling. The charge which is trapped can move from site to site with level inside the bandgap by the Frenkel-Poole emission, especially under the high electric field. This phenomena occurs frequently when a material have many defects acting as trapping and de-trapping centers. Tunneling effect is also an important mechanism of data loss. Electrons near the edge of nitride and tunneling oxide can tunnel into the conduction band of Si-substrate or inject into the interface traps between tunneling oxide and Si-substrate. Besides, the holes may tunnel into the nitride traps from the valence band of Si-substrate [43]. For SONOS devices, P/E speed and retention are controlled by the thickness of tunneling oxide. Thicker tunneling oxide will lead to better data retention at the expense of P/E efficiency. The quality of oxide is another factor that can influence the data retention. If the tunneling oxide contains many defects, traps-assisted-tunneling will become a dominant path and induce charge loss.
2.6.2 Endurance
It is important for an SONOS memory to maintain acceptable memory window after repetitive P/E operations. Endurance refers to the measure of P/E cycle times that the device still can work normally with distinguishable logic level at different storage state. Accompanying the increase of memory density, the endurance requirement is relaxed from 106 P/E cycles for 128MB density to 104 P/E cycles for 2GB density [44].
During P/E cycle, high electric field occurs in the tunneling oxide and many
defects will be generated. These defects act as the sites for traps-assisted-tunneling and become data loss paths. However, due to the discrete traps in the nitride layer, the stored electrons will not be lost completely. To reduce the stress-induced damage in the tunneling oxide, operation voltage must be reduced. Nevertheless, decreasing the applied voltage will result in a slower P/E speed. Therefore, we have to address all related parameters carefully.
Table I. Conditions of these four different dimensions NW SONOS.
Split S1 S2 S3 S4
TEOS Thickness (nm) 50 50 40 40
Lateral Etching Time (s) 80 60 80 60
Chapter 3 Characteristics of Planar and Nanowire SONOS Devices with Various Dimensions
Basic transfer characteristics of planar devices and NW SONOS ones with four different NW cross-sectional dimensions will be presented in this chapter. Here, we will discuss the relation between subthreshold swing (SS) and the dimension of NW.
Then, several important parameters of NW SONOS devices, including P/E speed, data retention and endurance will be examined and compared with the planar SONOS counterpart.
3.1 Basic Transfer Characteristics of Planar and NW SONOS
Figure 3-1 depicts the ID-VG curves of planar and NW SONOS devices. All measured devices in this figure have channel length of 0.4 µm and equivalent gate oxide thickness of 20 nm. The measurements were performed at VD = 0.5 V and 2 V.
Compared with the planar device, NW device has better SS and negligible drain induce barrier lowering (DIBL) due to its ultra-thin channel body and superior gate controllability. Figure 3-1(b) shows the plot of drain current, normalized to the channel width, versus the gate voltage. Obviously, the NW device possesses larger drive current and lower off-current, hence its Ion/Ioff ratio is higher than that of the planar one.
Figure 3-2 shows the transfer characteristics for devices with four different
dimensions as a function of channel length. S1 to S4 devices are labeled in a dimensional order with S1 having the largest NW circumference and S4 the smallest.
The TEM pictures of these devices are shown in Fig. 2-3. Even though the DIBL
The TEM pictures of these devices are shown in Fig. 2-3. Even though the DIBL