Chapter 3 Characteristics of Planar and Nanowire SONOS Devices with Various
3.3 Reliability Characteristics of Planar and NW SONOS
For the endurance tests, different P/E conditions were applied to different devices to obtain a comparable initial memory window (~2 V). Figure 3-14 indicates that the memory window is still acceptable after 104 stressing cycles. As the cycle
number increases, the Vths are almost unchanged in the programmed state and move upwards gradually in the erased state for these four devices, which implies that a few electrons still remain in the trapping layer when erasing. Consequently, residual electrons lead to an increasing Vth. Figure 3-15 shows the ID-VG curves of the S1 device before and after 104 P/E cycles with P/E conditions of 11V 100 µs/-10 V 1 ms.
It is clear that the SS is nearly identical to the fresh state after 104 P/E cycles. This indicates the tunneling oxide is not seriously degraded during the P/E cycles.
3.3.2 Retention
To measure the retention characteristics, we chose appropriate P/E conditions for each device to achieve a comparable initial memory window. Figure 3-16 shows the retention of NW SONOS devices with an initial window of about 2 V. The memory windows of S1, S2, S3 and S4 after 10 years are about 1.8, 0.8, 0.5 and 0.2 V, respectively. It demonstrates that the thinner devices exhibit worse data retention. In previous chapter, we had discussed the relation between the leakage current and electric field. When electrons are trapped in the nitride layer, these electrons will induce electric field in the ONO layers. In thinner devices, higher electric field induces a larger leakage rate. Furthermore, thinner devices need fewer electrons to reach the same memory window. The same amount of leaked electrons may cause a greater impact for the thinner devices. Consequently, the thicker devices have better data retention characteristics than thinner ones
Chapter 4 Characteristics of SONOS Devices with In-Situ Embedded Silicon Nanocrystals
In this chapter, basic transfer characteristics of standard (STD) and Si NCs NW SONOS devices will be compared in the first section. Next, the P/E characteristics and reliability issues of Si NCs NW SONOS devices will be examined and compared with the STD NW SONOS devices.
4.1 Basic Transfer Characteristics
The ID-VG curves of STD and Si NCs NW SONOS devices are shown in Fig. 4-1.
All measured devices in this figure have channel length of 0.4 µm and the wire diameter of 30nm as shown in Fig. 2-13. Thickness of the ONO of the STD NW SONOS is 3.5/8/12 nm. For the Si NCs devices, we keep the thickness of tunneling oxide, nitride and blocking oxide as the same as the STD NW SONOS. The Si NCs are placed at different positions as mentioned before in Section 2.3. We call these devices as the bottom, mid or top Si NCs NW SONOS for the Si NCs located at the interface of tunneling oxide and nitride layer, in the nitride layer or between the nitride and blocking oxide, respectively. The SONOS device without Si NCs is relatively superior in terms of SS behavior which can be seen in Fig. 4-1. The discrepancy of SS between STD and Si NCs SONOS devices can be explained by the following two reasons. First, after depositing the Si NCs, the surface is unsmooth as
indicated by the AFM image shown in Fig. 2-9. Consequently, the effective oxide thickness of the Si NCs NW SONOS is not uniform across all gated area, which may lead to the worse SS. Second, embedded Si NCs will increase the effective oxide thickness because we didn’t change the thickness of TEOS oxide and nitride layers.
Therefore, the SS of STD NW SONOS device is better than that of the Si NCs NW SONOS devices.
4.2 Program/Erase Characteristics
The manners we used here to program and erase the STD and Si NCs devices were the same as we had described in Section 3.1. Before erasing, these devices were all programmed beforehand with 2.5 V shift of Vth relative to the fresh state.
4.2.1 Program Characteristics of STD and Si NCs NW SONOS
Figures 4-2 (a) ~(d) depict the Vth shift versus programming time for STD and Si NCs NW SONOS devices with gate biases of 9 V, 10 V, 11 V, 12 V, 13 V, 14 V and 15 V, respectively. The Vth shift increases when prolonging the operation time or increasing the gate bias for either STD or Si NCs device. Programming saturation, which has been explained in Section 3.2.2, also occurs in these devices. However, the Vth shift behaviors of Si NCs device are very dissimilar to the STD counterparts.
Figure 4-3 compares the program characteristics of STD and bottom Si NCs NW SONOS devices with the program voltages of 9 V, 11 V and 13 V. Compared with the STD device at gate bias of 9 V, the Vth shift of the bottom Si NCs device is smaller before the programming time reaches 100 µs. However, because of the larger increasing rate of the bottom Si NCs device during the whole programming process, the bottom Si NCs device shows larger Vth shift and increasing rate of Vth when 13 V
is applied to the gate, Obviously, the intersection of the Vth shift lines between STD and Si NC devices happens earlier when the gate bias is increased. The potential profiles of STD and bottom Si NCs NW SONOS devices, biased at the same gate voltage, are shown in Fig. 4-4. The dash and solid lines represent the potential of STD and Si NCs devices, respectively. Owing to the fact that EOT of the bottom Si NCs device is larger than the STD device, at the beginning of the programming process, the electric field across the tunneling oxide in STD NW SONOS is higher than that in the bottom Si NCs NW SONOS and will raise the tunneling probability of electrons.
However, the faster increasing rate of Vth shift for the bottom Si NC devices is due to the influence of Si NCs. According to the gate-sensing and channel-sensing method proposed by H. T. Lue et al. [45], the mean location of the trapped electrons migrates from the interface of the tunneling oxide and nitride toward the center of nitride layer in STD devices. Furthermore, the mean location shift to the center of nitride becomes faster when the program bias gets larger as shown in Fig. 4-5. Such situation can be changed with Si NCs embedded between the tunneling oxide and nitride layer which can be considered as additional quantum wells formed at the tunneling oxide/nitride interface that improve the trapping efficiency and make the mean location of the trapped electrons closer to the channel. Therefore, equal amount of trapped electrons will induce higher Vth shift in the bottom Si NCs device. Furthermore, the available trapping sites also increase due to the incorporation of the Si NCs as evidenced by the larger Vth shift in Fig.4-3.
In Fig. 4-6, we illustrate and compare the program characteristics of STD and mid Si NCs NW SONOS devices with the gate voltages of 9 V, 11 V and 13 V. Due to a larger EOT and thus a weaker electric field, the shift in Vth for the Si NCs samples is smaller in early stage of programming as compared with the STD ones. However, the
increasing rate of Vth is obviously higher for the Si NCs devices and therefore an interception between the two curves would occur. Moreover, the interception occurs earlier as the program gate voltage is higher. The above results can be explained as follows: As explained earlier, when the programming time gets longer, centroid of the trapped electrons gradually approaches the center of nitride layer. As the Si NCs are located at the center of the nitride, the deeper quantum wells will introduce additional trapping levels for electron trapping. As a result, a larger shift in Vth than that of STD devices can be achieved.
The program characteristics for STD and top Si NCs NW SONOS devices with gate biases of 9 V, 11 V and 13 V are shown in Fig. 4-7. The program performance of STD devices is better than that of the top Si NCs apparently. Nevertheless, the programming rates of the two splits look almost the same. The above results are attributed to the thicker EOT of the top Si NCs devices due to the incorporation of the NCs. Lower electric field across the tunneling oxide, which is shown in Fig. 4-8, will reduce the tunneling probability of electrons through the oxide and into the nitride layer. In addition, we had remarked that the mean location of trapped electrons will remain at the center of nitride layer finally. Consequently, these Si NCs, located at the interface of nitride and blocking oxide, will have negligible effect on storing electrons.
4.2.2 Erase Characteristics of STD and Si NCs NW SONOS
Figures 4-9 (a) ~ (d) show the erase results for STD and Si NCs NW devices with the gate biases of -9 V, -10 V, -11 V, -12 V and -13 V, respectively. The erase speed accelerates when the magnitude of gate bias is increased. The erase saturation phenomenon happens in these devices as Vth shift reaches a specific level depending
on the ways of incorporating the Si NCs in these devices. When the absolute value of gate bias increases, the time to reach saturation becomes shorter.
To compare the erasing efficiency, we plot the erase characteristics of STD and bottom Si NCs NW SONOS devices with gate bias of -9 V, -11 V and -13 V in Fig 4-10. We can easily observe that the STD devices possess better erasing efficiency in early stage of erasing due to its thinner EOT, which helps the de-trapping process of electrons trapped in the nitride into the channel. However, the thinner EOT also results in a reduction in the saturation Vth of the STD devices, which is around 2.4 V shown in the figure, around 0.4 V smaller than that of the bottom Si NCs one. This will limit the available window size of the devices in practical applications.
The erase characteristics of the mid Si NCs NW SONOS device, which illustrated in Fig.4-9(c), are very dissimilar to other devices apparently. As can be seen in the figures, the rate is initially slow and weakly dependent on the gate bias, but later becomes much faster at a certain moment which is closely related to the magnitude of gate bias. To clearly illustrate such transition, Fig. 4-11 shows the Vth shift curve with the gate bias of -9 V. We separate this curve into two stages by using the erasing time of 100 µs as a demarcation. As mentioned above, the first stage (erase time < 100 µs) exhibits much slower rate than that of the second stage (erase time >
100 µs). Origin for such unique phenomenon can be understood with the band diagrams shown in Figs. 4-12(a) ~(c). Figure 4-12(a) shows the situation of a programmed mid Si NCs NW SONOS device. The Si NCs incorporated in the middle of nitride form quantum wells which provide trapping sites with level lower than portion of the trapping sites located inside the middle of the nitride. After programming, most of the electrons are believed to be trapped inside the deep levels in the Si NCs or in the defects sites located in the middle of the nitride, resulting in
the rise of potential wherein. At the beginning of erasing, the electrons trapped inside the Si NCs can tunnel back to the channel directly or transfer to a vacant level in the nitride, as shown in Fig. 4-12(b). The former and latter processes tend to increase and decrease Vth, respectively. Competition of the two processes results in a slow rate in Vth shift. In this figure, two gate bias conditions are compared. Owing to the accumulation of a large amount of electrons in the middle of the trapping medium, an increase in gate voltage draws little impact on the aforementioned processes. This explains the weak dependence on the gate voltage applied in the first stage. As the erase time is sufficiently long that most of the electrons trapped in the Si NCs have gone, ejection of electrons to the channel from the trapping sites located in nitride becomes dominant, as shown in Fig. 4-12(c). This is what happens in the second stage indicated in Fig. 4-11 and results in an accelerated rate in Vth shift. Figure 4-13 shows and compares the erase speed for STD and mid Si NCs NW SONOS devices with the gate biases of -9 V, -11 V and -13 V. It can be seen that longer stress time is needed for the mid Si NCs device to reach the same Vth shift as the STD device.
Figure 4-14 compares the erase characteristics of STD and top Si NCs NW SONOS devices with the erase voltages of -9 V, -11 V and -13 V, respectively. In the time range the shift rates look comparable for the two splits of devices, although lags are seen for the Si NCs devices. Thinner EOT also bring about the faster erase speed of STD device over the top Si NCs one. However, as mentioned above, in this case the Si NCs are distant from the channel and thus unlikely to trap the electrons. In other words, distribution of the trapped electrons for the top Si NCs device after programming is similar to that of the STD one, thus they exhibit similar rate in Vth
shift. Another interesting phenomenon is also found in Fig. 4-14. When a gate voltage of -13 V is applied, the Vth of the top Si NCs device begins to shift upward when the
stress time is longer than 100 µs. According to the previous discussion, electrons injecting from the gate will cause the erase saturation. This can be explained with the band diagrams shown in Figs. 4-15(a) and (b). In the early stage of erasing, ejection of the trapped electrons from the storage nitride layer results in a decrease of Vth. When most of the electrons are out, the potential in the central nitride is lowered. This will increase the strength of electric field across the block oxide and electrons injection from the gate becomes significant. For the top Si NCs device, the incorporated Si NCs provide additional sites for storing the electrons. This is responsible for the rebound of Vth in the split of devices shown in Fig. 4-14.
4.3 Reliability Characteristics of Planar and NW SONOS 4.3.1 Endurance
Different P/E conditions were applied to different devices in order to obtain a similar memory window of about 2 V for the endurance tests. The results for all splits of devices are shown in Fig. 4-16. The figure indicates that the memory window is still acceptable after 104 stressing cycles. As the cycle number increases, the VTH remains almost unchanged in both the programmed and erased state for these devices, which implies the tunneling oxide is not degraded seriously during the P/E operation.
4.3.2 Retention
Figure 4-17 shows the retention characteristics of the devices. The memory window is initially set at about 2 V by choosing appropriate P/E conditions for each device. The memory windows of STD, bottom Si NCs, mid Si NCs and top Si NCs after 10 years are about 0.5, 0.5, 1.5 and 1.1 V, respectively. Among the splits, it can
be seen that the mid Si NCs one displays the best performance, owing to the deeper storage levels for electrons introduced by Si NC dots embedded in the middle of the nitride. The bottom Si NCs device exhibits retention behavior similar to that of the STD, as can be observed in Fig. 4-18. Even the incorporated Si NCs provide deeper levels for storing the electrons, the trapped electrons still tend to leak out as they are located closer to the channel. Therefore, the bottom Si NCs device has the worst data retention among these three types of Si NCs devices.
Chapter 5 Conclusion and Suggested Future Work
5.1 Conclusion
In this thesis, we employed a simple, low cost, and flexible way that was recently developed by our group to fabricate NW devices. With a slight modification in fabrication procedure, gate-all-around NW SONOS devices with various cross-sectional NW dimensions were fabricated and characterized. Compared with planar counterparts, NW devices possess higher on/off ratio, superior SS and DIBL.
Moreover, NW SONOS devices have apparent improvement on P/E speed which can be attributed to the higher curvature that induces a larger electric field across the tunneling oxide. Faster P/E speed implies the NW SONOS devices can be operated at a smaller voltage than planar devices to reach the same memory window.
Among our four NW splits of devices, the S4 split, which has the thinnest dimension, exhibits the best SS due to its best gate controllability. Regarding the program efficiency, these four NW SONOS splits present a totally consistent trend that thinner device shows higher programming speed and reaches the programming saturation more quickly. For the erase characteristics, the thinner device has a faster erase speed. Therefore, to achieve better P/E performance, the ONO thickness needs to be adjusted and optimized for devices with different channel dimensions. For endurance test, all four NW SONOS splits meet acceptable memory window after 104 P/E cycles. The data retention measurements of these four splits illustrate that the memory window can be larger than 0.5 V after 10 years at room temperature.
In this study, we have also fabricated Si NCs devices in which the Si NCs are incorporated at different location in the nitride trapping layer. According to the position of Si NCs, these devices can be classified into three types, namely, bottom Si NCs, mid Si NCs and top Si NCs. Accompanying with a change in Si NCs location, the memory devices exhibit very different P/E characteristics. During programming, the mean location of trapped electrons would be affected by Si NCs. As a result, the bottom Si NCs device shows a faster Vth increase rate over STD controls. Moreover, these Si NCs provide extra trapping sites that enable a larger Vth shift in bottom and mid Si NCs devices. The top Si NCs device shows no improvement in program operation because of the mean location of electrons is mainly positioned at the center of the trapping layer. While for the mid Si NCs devices, we can see that these Si NCs render the trapped electrons harder to be de-trapped. When prolonging the erasing time, the gate-injected electrons are trapped in the Si NCs, resulting in Vth increase as can be seen in the top Si NCs devices. For endurance test, all four NW SONOS splits can maintain acceptable memory window after 104 P/E cycles. The memory window of all splits of devices can be larger than 0.5 V after 10 years at room temperature.
Table II summarizes the operation performance of the devices investigated in this work. Based on the results, the most optimum NC location should be positioned somewhere between the middle and the bottom interface of the nitride layer.
5.2 Suggested Future Work
In this work, it has been shown that the cross-sectional dimensions of the NW channel closely affect the operation performance of the SONOS devices. The thickness of ONO layers should be optimized specifically for an SONOS device with particular cross-sectional dimensions. Besides, replacing the ONO composite layers
with suitable high-κ materials is also viable. Moreover, by slightly changing the process, a vertically stacked NW device array can be fabricated and employed to increase the NW count in a unit area.
We have also demonstrated many important and interesting results about NW SONOS by incorporating the Si NCs into different designated positions of the nitride
We have also demonstrated many important and interesting results about NW SONOS by incorporating the Si NCs into different designated positions of the nitride