Chapter 4 Characteristics of SONOS Devices with In-Situ Embedded Silicon
4.1 Basic Transfer Characteristics
4.2.2 Erase Characteristics of STD and Si NCs NW SONOS
Figures 4-9 (a) ~ (d) show the erase results for STD and Si NCs NW devices with the gate biases of -9 V, -10 V, -11 V, -12 V and -13 V, respectively. The erase speed accelerates when the magnitude of gate bias is increased. The erase saturation phenomenon happens in these devices as Vth shift reaches a specific level depending
on the ways of incorporating the Si NCs in these devices. When the absolute value of gate bias increases, the time to reach saturation becomes shorter.
To compare the erasing efficiency, we plot the erase characteristics of STD and bottom Si NCs NW SONOS devices with gate bias of -9 V, -11 V and -13 V in Fig 4-10. We can easily observe that the STD devices possess better erasing efficiency in early stage of erasing due to its thinner EOT, which helps the de-trapping process of electrons trapped in the nitride into the channel. However, the thinner EOT also results in a reduction in the saturation Vth of the STD devices, which is around 2.4 V shown in the figure, around 0.4 V smaller than that of the bottom Si NCs one. This will limit the available window size of the devices in practical applications.
The erase characteristics of the mid Si NCs NW SONOS device, which illustrated in Fig.4-9(c), are very dissimilar to other devices apparently. As can be seen in the figures, the rate is initially slow and weakly dependent on the gate bias, but later becomes much faster at a certain moment which is closely related to the magnitude of gate bias. To clearly illustrate such transition, Fig. 4-11 shows the Vth shift curve with the gate bias of -9 V. We separate this curve into two stages by using the erasing time of 100 µs as a demarcation. As mentioned above, the first stage (erase time < 100 µs) exhibits much slower rate than that of the second stage (erase time >
100 µs). Origin for such unique phenomenon can be understood with the band diagrams shown in Figs. 4-12(a) ~(c). Figure 4-12(a) shows the situation of a programmed mid Si NCs NW SONOS device. The Si NCs incorporated in the middle of nitride form quantum wells which provide trapping sites with level lower than portion of the trapping sites located inside the middle of the nitride. After programming, most of the electrons are believed to be trapped inside the deep levels in the Si NCs or in the defects sites located in the middle of the nitride, resulting in
the rise of potential wherein. At the beginning of erasing, the electrons trapped inside the Si NCs can tunnel back to the channel directly or transfer to a vacant level in the nitride, as shown in Fig. 4-12(b). The former and latter processes tend to increase and decrease Vth, respectively. Competition of the two processes results in a slow rate in Vth shift. In this figure, two gate bias conditions are compared. Owing to the accumulation of a large amount of electrons in the middle of the trapping medium, an increase in gate voltage draws little impact on the aforementioned processes. This explains the weak dependence on the gate voltage applied in the first stage. As the erase time is sufficiently long that most of the electrons trapped in the Si NCs have gone, ejection of electrons to the channel from the trapping sites located in nitride becomes dominant, as shown in Fig. 4-12(c). This is what happens in the second stage indicated in Fig. 4-11 and results in an accelerated rate in Vth shift. Figure 4-13 shows and compares the erase speed for STD and mid Si NCs NW SONOS devices with the gate biases of -9 V, -11 V and -13 V. It can be seen that longer stress time is needed for the mid Si NCs device to reach the same Vth shift as the STD device.
Figure 4-14 compares the erase characteristics of STD and top Si NCs NW SONOS devices with the erase voltages of -9 V, -11 V and -13 V, respectively. In the time range the shift rates look comparable for the two splits of devices, although lags are seen for the Si NCs devices. Thinner EOT also bring about the faster erase speed of STD device over the top Si NCs one. However, as mentioned above, in this case the Si NCs are distant from the channel and thus unlikely to trap the electrons. In other words, distribution of the trapped electrons for the top Si NCs device after programming is similar to that of the STD one, thus they exhibit similar rate in Vth
shift. Another interesting phenomenon is also found in Fig. 4-14. When a gate voltage of -13 V is applied, the Vth of the top Si NCs device begins to shift upward when the
stress time is longer than 100 µs. According to the previous discussion, electrons injecting from the gate will cause the erase saturation. This can be explained with the band diagrams shown in Figs. 4-15(a) and (b). In the early stage of erasing, ejection of the trapped electrons from the storage nitride layer results in a decrease of Vth. When most of the electrons are out, the potential in the central nitride is lowered. This will increase the strength of electric field across the block oxide and electrons injection from the gate becomes significant. For the top Si NCs device, the incorporated Si NCs provide additional sites for storing the electrons. This is responsible for the rebound of Vth in the split of devices shown in Fig. 4-14.
4.3 Reliability Characteristics of Planar and NW SONOS 4.3.1 Endurance
Different P/E conditions were applied to different devices in order to obtain a similar memory window of about 2 V for the endurance tests. The results for all splits of devices are shown in Fig. 4-16. The figure indicates that the memory window is still acceptable after 104 stressing cycles. As the cycle number increases, the VTH remains almost unchanged in both the programmed and erased state for these devices, which implies the tunneling oxide is not degraded seriously during the P/E operation.
4.3.2 Retention
Figure 4-17 shows the retention characteristics of the devices. The memory window is initially set at about 2 V by choosing appropriate P/E conditions for each device. The memory windows of STD, bottom Si NCs, mid Si NCs and top Si NCs after 10 years are about 0.5, 0.5, 1.5 and 1.1 V, respectively. Among the splits, it can
be seen that the mid Si NCs one displays the best performance, owing to the deeper storage levels for electrons introduced by Si NC dots embedded in the middle of the nitride. The bottom Si NCs device exhibits retention behavior similar to that of the STD, as can be observed in Fig. 4-18. Even the incorporated Si NCs provide deeper levels for storing the electrons, the trapped electrons still tend to leak out as they are located closer to the channel. Therefore, the bottom Si NCs device has the worst data retention among these three types of Si NCs devices.
Chapter 5 Conclusion and Suggested Future Work
5.1 Conclusion
In this thesis, we employed a simple, low cost, and flexible way that was recently developed by our group to fabricate NW devices. With a slight modification in fabrication procedure, gate-all-around NW SONOS devices with various cross-sectional NW dimensions were fabricated and characterized. Compared with planar counterparts, NW devices possess higher on/off ratio, superior SS and DIBL.
Moreover, NW SONOS devices have apparent improvement on P/E speed which can be attributed to the higher curvature that induces a larger electric field across the tunneling oxide. Faster P/E speed implies the NW SONOS devices can be operated at a smaller voltage than planar devices to reach the same memory window.
Among our four NW splits of devices, the S4 split, which has the thinnest dimension, exhibits the best SS due to its best gate controllability. Regarding the program efficiency, these four NW SONOS splits present a totally consistent trend that thinner device shows higher programming speed and reaches the programming saturation more quickly. For the erase characteristics, the thinner device has a faster erase speed. Therefore, to achieve better P/E performance, the ONO thickness needs to be adjusted and optimized for devices with different channel dimensions. For endurance test, all four NW SONOS splits meet acceptable memory window after 104 P/E cycles. The data retention measurements of these four splits illustrate that the memory window can be larger than 0.5 V after 10 years at room temperature.
In this study, we have also fabricated Si NCs devices in which the Si NCs are incorporated at different location in the nitride trapping layer. According to the position of Si NCs, these devices can be classified into three types, namely, bottom Si NCs, mid Si NCs and top Si NCs. Accompanying with a change in Si NCs location, the memory devices exhibit very different P/E characteristics. During programming, the mean location of trapped electrons would be affected by Si NCs. As a result, the bottom Si NCs device shows a faster Vth increase rate over STD controls. Moreover, these Si NCs provide extra trapping sites that enable a larger Vth shift in bottom and mid Si NCs devices. The top Si NCs device shows no improvement in program operation because of the mean location of electrons is mainly positioned at the center of the trapping layer. While for the mid Si NCs devices, we can see that these Si NCs render the trapped electrons harder to be de-trapped. When prolonging the erasing time, the gate-injected electrons are trapped in the Si NCs, resulting in Vth increase as can be seen in the top Si NCs devices. For endurance test, all four NW SONOS splits can maintain acceptable memory window after 104 P/E cycles. The memory window of all splits of devices can be larger than 0.5 V after 10 years at room temperature.
Table II summarizes the operation performance of the devices investigated in this work. Based on the results, the most optimum NC location should be positioned somewhere between the middle and the bottom interface of the nitride layer.
5.2 Suggested Future Work
In this work, it has been shown that the cross-sectional dimensions of the NW channel closely affect the operation performance of the SONOS devices. The thickness of ONO layers should be optimized specifically for an SONOS device with particular cross-sectional dimensions. Besides, replacing the ONO composite layers
with suitable high-κ materials is also viable. Moreover, by slightly changing the process, a vertically stacked NW device array can be fabricated and employed to increase the NW count in a unit area.
We have also demonstrated many important and interesting results about NW SONOS by incorporating the Si NCs into different designated positions of the nitride layer. Some advantages and disadvantages of using Si NCs have been observed in this study. The results indicate that the most optimum performance can be obtained as the Si NCs are located somewhere between the middle and the bottom interface of the nitride layer. This deserves future work to investigate. Moreover, the melioration of SONOS characteristics by integrating multiple stacks of nitride and Si NCs is also conceivable. These Si NCs structures also can be used in the planar device to examine the P/E characteristics. Nevertheless, a complete model to explain the characteristics of NW SONOS devices is lacking. Therefore, it is another urgent work to perform more simulations to justify the results and trends obtained in this study.
Table II. Comparisons between STD and Si NCs devices. ★Excellent ○○○○Good △△△△Fair.
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Poly-Gate
Gate Source
Drain
A B
NW SONOS
Nitride Nitride TEOS Wet Oxide Si Substrate
Nitride Nitride TEOS Wet Oxide Si Substrate
Nitride Nitride TEOS Wet Oxide Si Substrate
Fig. 2-1. (a) Layout and (b) cross-sectional view of NW SONOS.
(a) (b)
(a) (b)
(c) (d)
Nitride Nitride TEOS Wet Oxide Si Substrate
a-Si
Poly-Gate Nitride
Nitride TEOS Wet Oxide Si Substrate
Fig. 2-2. Process flow of NW SONOS memory device. (a) Deposition of hard mask/TEOS oxide/bottom nitride layers. (b) Patterning of hard mask and TEOS oxide by anisotropic etching. (c) DHF lateral etching. (d) a-Si deposition and SPC.
(e) Definition of S/D. (f) Removal of TEOS and nitride by wet etching. (g) Deposition of ONO layers. (h) Poly gate deposition.
(e) Definition of S/D. (f) Removal of TEOS and nitride by wet etching. (g) Deposition of ONO layers. (h) Poly gate deposition.