Organization of this thesis

This thesis is divides into several parts. The detail content is describe as follow.

In chapter 3, this chapter introduces experiment flow and measures these samples.

And discuss and analyze the result.

In chapter 4, We make a brief conclusion and future work in the last chapter.

EEPROM MOS Memories

RAM

’

s ROM

’

s

SRAM DRAM

ROM EPROM

Flash Volatile

Data lose after power off Nonvolatile

Data kept after power off

Fig. 1-1 MOS Memory tree

Fig. 1-3 SONOS structure memory

Source Drain

Substrate Silicon Nitride Tunneling oxide

Block oxide or control oxide Control Gate(poly)

Source Drain

Substrate Floating Gate(poly) Tunneling oxide

Block oxide or control oxide (ONO stack) Control Gate(poly)

Fig. 1-2 FG structure memory

Block oxide or control oxide

Source Drain

Substrate Tunneling oxide

Control Gate(ploy)

Fig. 1-4 Nanocrystal structure memory

Silicon dot

Chapter 2

Nonvolatile memory basic concept and operation mechanism

2.1 Introduce

2.1.1 SONOS nonvolatile memory devices

SONOS structure nonvolatile memory, charge traps distributed throughout the volume of the nitride layer. A typical trap has a density of the order 10¹⁸-10¹⁹ cm^-3 according to Yang et al [2.1]. SONOS nonvolatile semiconductor memories meet the memory challenges of scaling down issue. In general, NVSMs are required bear to 10K-100K times write/erase cycles (endurance) with 10-years memory retention at the temperatures as high as 125℃. The term “endurance” refers to the ability of the NVSM to bear repeated program cycles and still meet the specification. The term “retention”

describes the ability of the NVSM to store and recover information after a number of program cycles at specified temperature.

The SONOS memory device has received a lot of attention due to its advantages over the traditional FG memory device. These include reduced process complexity, lower voltage operation, improved cycling endurance, and elimination of drain induced

turn-on [2.2]. In SONOS memory device with SiO2 tunnel dielectric, the electrons and holes must tunnel through 3.15eV and 4.5eV energy barriers, respectively, to be injected into the Si3N4 charge trap layer. The energy band diagram during retention is show in Fig. 2-1. It can compare to the FG structure band diagram during retention show in Fig. 2-2. For FG structure, the electrons injected from the channel are trapped in poly-silicon conduction band. For SONOS structure, the electrons injected from the channel are trapped in forbidden gap below the nitride conduction band (label with the trap energy level of Et). In this device, the electrons cannot move freely between the discrete trap locations, hence the SONOS memory device is very robust against the defects inside the tunnel oxide and has better endurance than the floating gate flash memory. In the retention mode, electrons can leak to the substrae through the direct tunneling process shown as path “1” in Fig. 2-1. However, in this device the escape frequency is very small. Alternatively, electrons can be thermally de-trapped into the nitride conduction band and then tunnel back to the channel (this is path “2” in the fig.

2-1). This thermal de-trapping rate is exponentially reduced with a deep trap energy level. For these reasons, the SONOS flash memory can have much better retention time than the floating gate flash memory. A tunnel oxide of 3nm is thick enough to guarantee 10 years retention time in the SONOS flash memory.

2.1.2 Nanocrystal nonvolatile memory devices

That use silicon nanocrystals as the trapping material [2.4-2.5]. So the nanocrystal memory can robust against the defects inside the tunnel oxide like SONOS memory, and each dot will typically store only small amount of electrons. Collectively the charges stored in these dots control the channel-conductivity of the memory transistor.

As compared to conventional stacked-gate NVM devices, nanocrystal charge-storage offers several advantages, the main one being the potential to use thinner tunnel oxides without sacrificing nonvolatility. This is a quite attractive proposition, since reducing the tunnel oxide thickness is key to lowering operating voltages and/or increasing operating speeds. This claim of improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade [2.6]. Quantum confinement effects (band gap widening; energy quantization) can be exploited in sufficiently small nanocrystal geometries (sub-3 nm dot diameters) to further enhance the memory’s performance.

There are other important advantages though. First, nanocrystal memories use a more simplified fabrication process as compared to conventional stacked-gate FG NVM's by avoiding the fabrication complications and costs of a dual-poly process.

Further, due to the absence of drain to FG coupling, nanocrystal memories suffer less from drain-induced-barrier-lowering (DIBL) and therefore have intrinsically better punchthrough characteristics. One way to exploit this advantage is to use a higher drain bias during the read operation, thus improving memory access time. Alternatively, it allows the use of shorter channel lengths and therefore smaller cell area (i.e., lower cost). Finally, nanocrystal memories are characterized by excellent immunity to stress induced leakage current (SILC) and oxide defects due to the distributed nature of the

charge storage in the nanocrystal layer.

For fabrication demand, a typical requirement the aerial density of nanocrystal dots is at least 10¹²cm^-2. This is equivalent to approximately 100 particles controlling the channel of a memory FET with a 100 100 nm active area, and requires particle diameters of 5–6 nm and below. And the fabrication process should result in a planar nanocrystal layer, i.e., the thickness of the dielectric layer separating the nanocrystal and the substrate should be well controlled. Poor control of the tunnel oxide thickness will result in wider threshold voltage distributions and will increase the number of erratic bits. More generally, good process control is needed with regards to such nanocrystal features as: size and size distribution; inter-crystal interaction (lateral isolation); uniformity of aerial crystal density; and crystal doping (type and level).

Finally, it is preferred that that the fabrication process is simple and that it uses standard semiconductor equipment.

Several nanocrystal fabrication processes have been demonstrated. King et al.

[2.7] used Ge ion implantation subsequent high-temperature wet oxidation, which causes the implanted Ge atoms to pile up at the Si/SiO2 interface. And the number of electrons trapped in the Ge nanocrystals was estimated to be 3.5×10¹²cm^-2. Lin et al.

[2.8] make HfO2 by co-sputtering with pure silicon (99.9999% pure) and pure hafnium(99.9% pure) targets in an oxygen gas ambient deposition a 12-nm amorphous HfSiOx silicate layer. Then samples were subjected to RTA treatment in an O2 ambient

ambient to transfer the wetting layer into nanocrystals. This process is achieved through the relaxation of film stress and limited by the surface mobility [2.9]. Other than use deposition method, some special techniques formation nanocrystal are using ion implant [2.10-2.11] and sol-gel-spin-coating [2.12].

Nanocrystal memories have been presented in the midnineties as a possible alternative to conventional FG NVM devices, by allowing a further decrease in the tunnel oxide thickness. In particular, nanocrystal memories promise to enable a further scaling of the tunnel oxide, by relying on Coulomb blockade effects in small semiconductor geometries and on the enhanced robustness and fault-tolerance of distributed charge storage.

Research in this area has focused on the development of nanocrystal materials and fabrication processes, and on the integration of nanocrystal-based storage layers in actual memory devices. Promising device results have been presented, demonstrating low-voltage operation for comparable threshold voltage windows and operating speeds, and thin tunnel oxide retention behavior that suggest meeting long-term nonvolatility requirements.

In spite of these promising results, it is unclear whether nanocrystal memories will ever see commercialization. In order for that to happen, their claimed benefits will need to be more unambiguously substantiated, and a more appealing bundle of memory features will have to be demonstrated.

2.2 Memory basic concept

2.2.1 Reading operation

The data stored in a Flash cell can be determined measuring the threshold voltage of the memories. The best and fastest way to do that is by reading the current driven by the cell at a fixed gate bias show Fig. 2-3. When electrons stored in nanocrystal, the threshold voltage will shift (

∆

V_T ) that is proportional to the stored electron charge (Q).

The threshold voltage shift of a Flash transistor can be written as [2.13-2.14]:

T

V Q

∆ = −

C

(2.1)

Here Q is the carge stored in nanocrystal, and C is the capacitance between nanocrystal and control gate. It is possible to fix a reading voltage in such way that the current of the “1” cell is very high (in the range of tens of microamperes), while the current of the “0” cell is zero, in the microampere scale. In this way, it is possible to define the logical state “1” from a microscopic point of view as no electron charge (or positive charge) stored in the nanocrystal and from a macroscopic point of view as large reading current. Vice versa, the logical state “0” is defined, respectively, by electron charge stored in the nanocrystal and zero reading current.

semiconductor memory device are illustrated schematically in Fig. 2-4. During the write process, a positive gate voltage is applied to inject channel inversion-layer electrons into the nitride layer. During the erase process, a reverse gate bias is applied to cause the electrons to tunnel back into the channel and the accumulation layer holes to tunnel into the nitride from the channel. There are many ways to achieve

“programming” or “erasing”. In general, hot carrier electron injection and Fowler-Nordheim tunneling (F-N tunneling) are two kinds of common operation mechanism employed in novel nonvolatile memories.

2.2.2.1 Channel Hot-Electron Injection (CHEI)

The physical mechanism of CHEI is relatively simple to understand. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [2.15]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Fig. 2-5 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. In the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation.

2.2.2.2 F-N tunneling

Tunneling is another way writes electrons into nanocrystal from substrate. But during retention electrons could tunnel back to the channel too, constituting a large leakage current. The magnitude of the leakage current depends on both the thickness and the electron barrier height of the tunnel dielectric. The tunneling probability is expressed as:

0

exp( 2

^d

( )* x m

^e

)

T φ dx

= − ∫ ₌

(2.2)

Here

φ ( ) x

is barrier height. It is 3.1eV in Si-SiO2 for electrons see Table 2.1

[2.16-2.20]. d is tunnel dielectric thickness,

=

the Planck’s constant and me is the electron mass inside the tunnel dielectric and it is 0.5m0 for both nitride and oxide.

Many tunneling species can achieve charge transfer. Among them, in the memory operation mechanism, F-N tunneling is most often mentioned. The F-N tunneling mechanism occurs when applying a strong electric field (in the range of 8–10MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons passing through the energy barrier itself. The F-N tunneling [2.20] which can be expressed as follow:

total thickness of the tunnel and control oxide. As shown in Fig. 2-6, when the voltage drop across the tunnel dielectric exceeds the electron tunnel barrier height

φ

_B, F-N tunneling current depends more on the tunnel barrier height than on the tunnel dielectric thickness. Increasing the tunnel dielectric thickness will not decrease the tunneling current if the same electric field is applied.

2.2.2.3 Direct Tunneling

For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt.

2.2.3 Data retention

Any nonvolatile memory technology, Flash memories are specified to retain data for over ten years. This means the loss of charge stored in the memory must be as minimal as possible. In updated Flash technology, due to the small cell size, the capacitance is very small and at an operative programmed threshold shift—about 2 V—corresponds a number of electrons in the order of 10³ to 10⁴. A loss of 20% in this number (around 2–20 electrons lost per month) can lead to a wrong read of the cell and then to a data loss. Possible causes of charge loss are: 1) defects in the tunnel oxide; 2)

defects in the interpoly dielectric; 3) mobile ion contamination; and 4) detrapping of charge from insulating layers surrounding the FG [2.21].

2.2.4 Endurance

Flash products are specified for 10⁵ write/erase cycles. Cycling is known to cause a fairly uniform wear-out of the cell performance, mainly due to tunnel oxide degradation, which eventually limits the endurance characteristics. The oxide defect will increase stress induce leakage current (SILC), that let electrons store in memory will be lost. Threshold voltage gradually recovery the initial value that before writing, the memory window will be close. Data retention after cycling is the issue that definitely limits the tunnel oxide thickness scaling. For very thin oxide, below 8–9 nm, the number of leaky cells becomes so large that even error-correction techniques cannot fix the problem.

Tunneling layer Electron barrier (eV) Hole barrier (eV)

SiO

2

3.15 4.7

SiN 2.4 1.8

Al

₂

O

₃

2.9 4.3

HfO

₂

1.6 3.3

Ta

2

O

5

0.3 3.0

Table 2-1 Electron and hole barrier high for SiO

2

and Si

3

N

4

Ec Ev Φ1 = 3.15eV

Tunneling oxide

Blocking oxide Φ0

Et

Si3N4

trapping layer

N+ Gate

“1”

“2”

Fig. 2-1 SONOS band diagram during retention mode

Ec Ev

Φ1 = 3.15eV

Tunneling oxide

Blocking oxide Poly silicon

floating gate N+ Gate

Fig. 2-2 FG band diagram during retention mode Φ0 = 3.15eV

Id

Vg Neutral

state “1”

Charge state “0”

∆Vt

The state “1” threshold voltage is low, the state

“0” threshold voltage is high.

Fig. 2-3 Memory reading operation

Fig. 2-4 Memory band diagram in (a)write mode (b)Erase mode Ec

Ev

N+ Gate Si substrate

SiO2

SiO2 Si3N4

(a) write mode

Ec Ev

N+ Gate

Si substrate

SiO2

SiO2

Si3N4

(b) erase mode

Fig. 2-5 The procedure of channel hot electrons injection

N+ N+

P substrate

VD > 0V VG > 0V

Si substrate

Tox Φ1

Φ2

Chapter 3

Metal nanocrystal memory use Co nanodot

3.1 Motivation

Memory with discrete charge elements allows more advanced scaling of tunneling oxide and exhibit superior characteristics compared to conventional FG structure memories in terms of operation voltage, write/erase speed, retention and endurance [3.1-3.4]. Scaling tunneling oxide can increase write/erase speed, but simultaneous decrease data retention because of increase electrons tunneling back to substrate from nanocrystals. For the data retention characteristics, however, have not provided sufficient nonvolatility mainly due to the high leakage current of ultrathin SiO2

tunneling barrier. Metal NC has been proposed in [3.5-3.8] aiming to improve the data retention. Since there are many kinds of metals that have the greater work function than silicon (Pt 5.29eV, Ni 4.84eV, Co 4.18eV), the electrons trapped in such metal NC are less likely to tunnel back to the substrate due to the higher electron barrier height, resulting in the prolonged data retention time. And due to the absence of drain to FG coupling, nanocrystal memories suffer less from drain induced barrier lowering (DIBL) and therefore have intrinsically better punchthrough characteristics. In addition, the large variety of the metal work functions from various metals allows more design flexibility in such device application. Besides for data retention goal, used discrete

storage still one advantage. The advantage is it can store two different data in only one device (i.e. one bit stored near drain side, other one store near source side, see Fig. 3-1) [3.9-3.10]. That can effective use each device and increase the memory size but don’t increase die size. The cost will be lower than one bit memory device.

3.2 Experimental procedure

For manufacture nonvolatile memory device, we used P-type (100) silicon wafer.

After RCA clean, growth tunneling oxide by furnace system. The oxide measured by ellipsometer is 35~38 Ǻ. Then used E-Gun evaporator deposited Co wetting layer about 40 Ǻ. This Co wetting lay thickness used 40 Ǻ refer to Liu’s paper [3.7-3.8] and Lee’s paper [3.11]. Some characters about cobalt list in Table 3-1. Then used rapid thermal process (RTP) anneal system of 400℃ ~ 900℃ in N2 and O2 ambient was then performed to transform cobalt wetting-layer into cobalt nanocrystals. The split table show in the Table 3-2. The blocking oxide used PE-CVD method deposited about 250 Ǻ SiO2 for isolation each nanodots. Final deposited Al layer in front and back side as electrode. Here, we use shadow mask in front side to define the cell pattern. The process flowchart show in Fig. 3-2.

3.3 Result and discussion

The basic procedures for metal nanocrystal formation are starting with Si wafer covered by a thin layer of thermal oxide, a metal wetting layer of 1–5 nm is deposited by e-beam evaporation. Then, the film is annealed at elevated temperatures close to its eutectic temperature with the substrate in an inert ambient to transfer the wetting layer into nanocrystals. This process is achieved through the relaxation of film stress and limited by the surface mobility. Some long-range forces such as the dispersion force and the electrical double layers will also affect the nanocrystal size and location distributions [3.12-3.13].

Before RTA, the as-deposited film comes naturally with some thickness perturbation and even nanocrystals start to form (without a clear separation in between, though). When the film is RTA treated to give the atoms enough surface mobility, the film will self-assemble into a lower-total-energy state. To reduce the elastic energy carried by the stress built into the film during the deposition process, the film tends to break into islands along the initial perturbation. However, minimization of the surface energy and the dispersion force between the top and bottom interfaces can help stabilize the film. So the final geometry will depend on the balance between these driving forces. Once the nanocrystals have formed, the work function difference between the metal and the extrinsic substrate generates localized depletion or accumulation region in the substrate. The repulsion force between those regions helps stabilize the nanocrystals and keep a uniform distance between them.

Fig. 3-3 ~ Fig. 3-7 shows the AFM pictures of nanocrystal formation from Co films on top of 3.5 nm thermal oxide and the resulted nanocrystal size distribution. All samples went through the annealing cycle at different temperature for 30s and 60s.

After RTA, well-defined nanocrystals with round shape and certain size distribution

can be achieved. The density of NC is decreased and the size of NC is increased as the RTA annealing temperature is increased. These results show that the greater thermal energy induced agglomeration of the metal wetting layer into the larger NCs. For sample6, we observe very dense nanocrystal formation. It be estimated about 3×10¹¹cm^-2. For the sample7、 sample8、 sample9 and sample10, the dot is baldly bigger than the sample6. But sample6 density is the highest. The higher treatment temperature and time, dots growth larger and the density decreased is agreeable we anticipation. The density for each sample are 1.6×10¹¹cm^-2 (sample7)、1.37×10¹¹cm^-2 (sample8)、0.971×10¹¹cm^-2 (sample9)、0.556×10¹¹cm^-2 (sample10).

3.3.2 Memory characteristics

In order to confirm the memory operation, high-frequency capacitance–voltage (HF C–V) characteristic of a capacitor with a SiO2 –cobalt NC–SiO2 –Al stack was measured, as shown in Fig. 3-9 ~ Fig. 3-12. The observed large hysteresis in HF C–V indicates the charging and discharging process of the NC memory cell. The C-V curves

In order to confirm the memory operation, high-frequency capacitance–voltage (HF C–V) characteristic of a capacitor with a SiO2 –cobalt NC–SiO2 –Al stack was measured, as shown in Fig. 3-9 ~ Fig. 3-12. The observed large hysteresis in HF C–V indicates the charging and discharging process of the NC memory cell. The C-V curves

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