Result and discussion

The basic procedures for metal nanocrystal formation are starting with Si wafer covered by a thin layer of thermal oxide, a metal wetting layer of 1–5 nm is deposited by e-beam evaporation. Then, the film is annealed at elevated temperatures close to its eutectic temperature with the substrate in an inert ambient to transfer the wetting layer into nanocrystals. This process is achieved through the relaxation of film stress and limited by the surface mobility. Some long-range forces such as the dispersion force and the electrical double layers will also affect the nanocrystal size and location distributions [3.12-3.13].

Before RTA, the as-deposited film comes naturally with some thickness perturbation and even nanocrystals start to form (without a clear separation in between, though). When the film is RTA treated to give the atoms enough surface mobility, the film will self-assemble into a lower-total-energy state. To reduce the elastic energy carried by the stress built into the film during the deposition process, the film tends to break into islands along the initial perturbation. However, minimization of the surface energy and the dispersion force between the top and bottom interfaces can help stabilize the film. So the final geometry will depend on the balance between these driving forces. Once the nanocrystals have formed, the work function difference between the metal and the extrinsic substrate generates localized depletion or accumulation region in the substrate. The repulsion force between those regions helps stabilize the nanocrystals and keep a uniform distance between them.

Fig. 3-3 ~ Fig. 3-7 shows the AFM pictures of nanocrystal formation from Co films on top of 3.5 nm thermal oxide and the resulted nanocrystal size distribution. All samples went through the annealing cycle at different temperature for 30s and 60s.

After RTA, well-defined nanocrystals with round shape and certain size distribution

can be achieved. The density of NC is decreased and the size of NC is increased as the RTA annealing temperature is increased. These results show that the greater thermal energy induced agglomeration of the metal wetting layer into the larger NCs. For sample6, we observe very dense nanocrystal formation. It be estimated about 3×10¹¹cm^-2. For the sample7、 sample8、 sample9 and sample10, the dot is baldly bigger than the sample6. But sample6 density is the highest. The higher treatment temperature and time, dots growth larger and the density decreased is agreeable we anticipation. The density for each sample are 1.6×10¹¹cm^-2 (sample7)、1.37×10¹¹cm^-2 (sample8)、0.971×10¹¹cm^-2 (sample9)、0.556×10¹¹cm^-2 (sample10).

3.3.2 Memory characteristics

In order to confirm the memory operation, high-frequency capacitance–voltage (HF C–V) characteristic of a capacitor with a SiO2 –cobalt NC–SiO2 –Al stack was measured, as shown in Fig. 3-9 ~ Fig. 3-12. The observed large hysteresis in HF C–V indicates the charging and discharging process of the NC memory cell. The C-V curves are fail when samples treatment at low temperature (700℃). We guess maybe the metal film treat at low temperature not get enough energy translate film to nanodots. But sample7 although treatment at 700℃, but it C-V curve not express any memory character too. From sample AFM picture Fig. 3-3 and Fig. 3-4, although the dots have formation, but maybe not clear separation in each dot, so that these sample(sample6

design. In these samples, we found the sample8 have a larger flat-band voltage shift than other sample. It have more charge injection into cobalt NCs. And the sample9, it have a flat-band voltage shift up to 2 V too, but operating voltage is higher than sample8. The sample10 observe from its C-V curve, even then gate bias sweeps between 8V and -8V but not express memory window. And the sample10 AFM picture Fig.3-7, we look the lower dot density than other sample (sample10 only 5.56×10¹⁰cm^-2). It maybe a reason explain this phenomenon. In RTO sample we observe each samples have stable C-V curve Fig. 3-8 but not show any memory window. Maybe the Co’s metal-oxide hasn’t trap ability.

3.3.3 Programming/Erase characteristics

Programming transient characteristics of cobalt NC memory devices are demonstrate in Fig. 3-13. Only programming in a low voltage 5V can get an obvious flat-band voltage shift. This is due to the fact that cobalt NC provides considerably greater density of available energy states, resulting in the larger amount of electrons stored inside the NC after programming. We compare Fig. 3-13 and Fig. 3-17, we find in the same programming voltage, sample8 flat-band voltage shift is larger than sample9. This is matching our measure in C-V curve. When operate in Erasing mode the gate apply negative bias, operation time over 0.01s the over-erase situation take place see Fig. 3-14. It maybe the hole be writing into NCs from channel or the free electrons in the cobalt be erasing.

3.3.4 Data retention characteristics

Fig. 3-15 and Fig. 3-19 illustrated the retention characteristics of Co NCs at the room temperature. The retention time is very poor for a nonvolatile memory. The charge loss 76% and it can’t reach 10 year data retention. Sample9 only remain 0.264V flat-band voltage shift and sample10 remain 0.173V flat-band voltage shift. Some charge loss reasons have be mention in chapter 2. In these reasons, we guess the PE-oxide maybe a main reason for charge loses. Because dots in the surface, their inter-distance are very close only tens nanometer. If PE-oxide quality not very good, it will cause large charge loss in NCs. The blocking oxide leakage current illustrated in Fig. 3-21. Except for this reason, according to Liu’s paper [3.7] some dots have inter-connect will induce large leakage current show in Fig. 3-21. The tunneling oxide defect also can make large charge lose, but other experiment can prove the furnace system is clear. One reason can make the tunneling oxide defect generate. When metal film deposition on the tunneling oxide, it rely on heating process to translate metal film into dots. This process is achieved through the relaxation of metal film stress. During stress relaxation, maybe underlay oxide stand the stress. Make the oxide crack or defect generate so that the leakage current get more. Fig. 3-16 and Fig. 3-20 show these samples leakage current.