Reading operation

The data stored in a Flash cell can be determined measuring the threshold voltage of the memories. The best and fastest way to do that is by reading the current driven by the cell at a fixed gate bias show Fig. 2-3. When electrons stored in nanocrystal, the threshold voltage will shift (

∆

V_T ) that is proportional to the stored electron charge (Q).

The threshold voltage shift of a Flash transistor can be written as [2.13-2.14]:

T

V Q

∆ = −

C

(2.1)

Here Q is the carge stored in nanocrystal, and C is the capacitance between nanocrystal and control gate. It is possible to fix a reading voltage in such way that the current of the “1” cell is very high (in the range of tens of microamperes), while the current of the “0” cell is zero, in the microampere scale. In this way, it is possible to define the logical state “1” from a microscopic point of view as no electron charge (or positive charge) stored in the nanocrystal and from a macroscopic point of view as large reading current. Vice versa, the logical state “0” is defined, respectively, by electron charge stored in the nanocrystal and zero reading current.

semiconductor memory device are illustrated schematically in Fig. 2-4. During the write process, a positive gate voltage is applied to inject channel inversion-layer electrons into the nitride layer. During the erase process, a reverse gate bias is applied to cause the electrons to tunnel back into the channel and the accumulation layer holes to tunnel into the nitride from the channel. There are many ways to achieve

“programming” or “erasing”. In general, hot carrier electron injection and Fowler-Nordheim tunneling (F-N tunneling) are two kinds of common operation mechanism employed in novel nonvolatile memories.

2.2.2.1 Channel Hot-Electron Injection (CHEI)

The physical mechanism of CHEI is relatively simple to understand. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [2.15]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Fig. 2-5 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. In the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation.

2.2.2.2 F-N tunneling

Tunneling is another way writes electrons into nanocrystal from substrate. But during retention electrons could tunnel back to the channel too, constituting a large leakage current. The magnitude of the leakage current depends on both the thickness and the electron barrier height of the tunnel dielectric. The tunneling probability is expressed as:

0

exp( 2

^d

( )* x m

^e

)

T φ dx

= − ∫ ₌

(2.2)

Here

φ ( ) x

is barrier height. It is 3.1eV in Si-SiO2 for electrons see Table 2.1

[2.16-2.20]. d is tunnel dielectric thickness,

=

the Planck’s constant and me is the electron mass inside the tunnel dielectric and it is 0.5m0 for both nitride and oxide.

Many tunneling species can achieve charge transfer. Among them, in the memory operation mechanism, F-N tunneling is most often mentioned. The F-N tunneling mechanism occurs when applying a strong electric field (in the range of 8–10MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons passing through the energy barrier itself. The F-N tunneling [2.20] which can be expressed as follow:

total thickness of the tunnel and control oxide. As shown in Fig. 2-6, when the voltage drop across the tunnel dielectric exceeds the electron tunnel barrier height

φ

_B, F-N tunneling current depends more on the tunnel barrier height than on the tunnel dielectric thickness. Increasing the tunnel dielectric thickness will not decrease the tunneling current if the same electric field is applied.

2.2.2.3 Direct Tunneling

For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt.

2.2.3 Data retention

Any nonvolatile memory technology, Flash memories are specified to retain data for over ten years. This means the loss of charge stored in the memory must be as minimal as possible. In updated Flash technology, due to the small cell size, the capacitance is very small and at an operative programmed threshold shift—about 2 V—corresponds a number of electrons in the order of 10³ to 10⁴. A loss of 20% in this number (around 2–20 electrons lost per month) can lead to a wrong read of the cell and then to a data loss. Possible causes of charge loss are: 1) defects in the tunnel oxide; 2)

defects in the interpoly dielectric; 3) mobile ion contamination; and 4) detrapping of charge from insulating layers surrounding the FG [2.21].

2.2.4 Endurance

Flash products are specified for 10⁵ write/erase cycles. Cycling is known to cause a fairly uniform wear-out of the cell performance, mainly due to tunnel oxide degradation, which eventually limits the endurance characteristics. The oxide defect will increase stress induce leakage current (SILC), that let electrons store in memory will be lost. Threshold voltage gradually recovery the initial value that before writing, the memory window will be close. Data retention after cycling is the issue that definitely limits the tunnel oxide thickness scaling. For very thin oxide, below 8–9 nm, the number of leaky cells becomes so large that even error-correction techniques cannot fix the problem.

Tunneling layer Electron barrier (eV) Hole barrier (eV)

SiO

2

3.15 4.7

SiN 2.4 1.8

Al

₂

O

₃

2.9 4.3

HfO

₂

1.6 3.3

Ta

2

O

5

0.3 3.0

Table 2-1 Electron and hole barrier high for SiO

2

and Si

3

N

4

Ec Ev Φ1 = 3.15eV

Tunneling oxide

Blocking oxide Φ0

Et

Si3N4

trapping layer

N+ Gate

“1”

“2”

Fig. 2-1 SONOS band diagram during retention mode

Ec Ev

Φ1 = 3.15eV

Tunneling oxide

Blocking oxide Poly silicon

floating gate N+ Gate

Fig. 2-2 FG band diagram during retention mode Φ0 = 3.15eV

Id

Vg Neutral

state “1”

Charge state “0”

∆Vt

The state “1” threshold voltage is low, the state

“0” threshold voltage is high.

Fig. 2-3 Memory reading operation

Fig. 2-4 Memory band diagram in (a)write mode (b)Erase mode Ec

Ev

N+ Gate Si substrate

SiO2

SiO2 Si3N4

(a) write mode

Ec Ev

N+ Gate

Si substrate

SiO2

SiO2

Si3N4

(b) erase mode

Fig. 2-5 The procedure of channel hot electrons injection

N+ N+

P substrate

VD > 0V VG > 0V

Si substrate

Tox Φ1

Φ2

Chapter 3

Metal nanocrystal memory use Co nanodot

3.1 Motivation

Memory with discrete charge elements allows more advanced scaling of tunneling oxide and exhibit superior characteristics compared to conventional FG structure memories in terms of operation voltage, write/erase speed, retention and endurance [3.1-3.4]. Scaling tunneling oxide can increase write/erase speed, but simultaneous decrease data retention because of increase electrons tunneling back to substrate from nanocrystals. For the data retention characteristics, however, have not provided sufficient nonvolatility mainly due to the high leakage current of ultrathin SiO2

tunneling barrier. Metal NC has been proposed in [3.5-3.8] aiming to improve the data retention. Since there are many kinds of metals that have the greater work function than silicon (Pt 5.29eV, Ni 4.84eV, Co 4.18eV), the electrons trapped in such metal NC are less likely to tunnel back to the substrate due to the higher electron barrier height, resulting in the prolonged data retention time. And due to the absence of drain to FG coupling, nanocrystal memories suffer less from drain induced barrier lowering (DIBL) and therefore have intrinsically better punchthrough characteristics. In addition, the large variety of the metal work functions from various metals allows more design flexibility in such device application. Besides for data retention goal, used discrete

storage still one advantage. The advantage is it can store two different data in only one device (i.e. one bit stored near drain side, other one store near source side, see Fig. 3-1) [3.9-3.10]. That can effective use each device and increase the memory size but don’t increase die size. The cost will be lower than one bit memory device.

3.2 Experimental procedure

For manufacture nonvolatile memory device, we used P-type (100) silicon wafer.

After RCA clean, growth tunneling oxide by furnace system. The oxide measured by ellipsometer is 35~38 Ǻ. Then used E-Gun evaporator deposited Co wetting layer about 40 Ǻ. This Co wetting lay thickness used 40 Ǻ refer to Liu’s paper [3.7-3.8] and Lee’s paper [3.11]. Some characters about cobalt list in Table 3-1. Then used rapid thermal process (RTP) anneal system of 400℃ ~ 900℃ in N2 and O2 ambient was then performed to transform cobalt wetting-layer into cobalt nanocrystals. The split table show in the Table 3-2. The blocking oxide used PE-CVD method deposited about 250 Ǻ SiO2 for isolation each nanodots. Final deposited Al layer in front and back side as electrode. Here, we use shadow mask in front side to define the cell pattern. The process flowchart show in Fig. 3-2.

3.3 Result and discussion

The basic procedures for metal nanocrystal formation are starting with Si wafer covered by a thin layer of thermal oxide, a metal wetting layer of 1–5 nm is deposited by e-beam evaporation. Then, the film is annealed at elevated temperatures close to its eutectic temperature with the substrate in an inert ambient to transfer the wetting layer into nanocrystals. This process is achieved through the relaxation of film stress and limited by the surface mobility. Some long-range forces such as the dispersion force and the electrical double layers will also affect the nanocrystal size and location distributions [3.12-3.13].

Before RTA, the as-deposited film comes naturally with some thickness perturbation and even nanocrystals start to form (without a clear separation in between, though). When the film is RTA treated to give the atoms enough surface mobility, the film will self-assemble into a lower-total-energy state. To reduce the elastic energy carried by the stress built into the film during the deposition process, the film tends to break into islands along the initial perturbation. However, minimization of the surface energy and the dispersion force between the top and bottom interfaces can help stabilize the film. So the final geometry will depend on the balance between these driving forces. Once the nanocrystals have formed, the work function difference between the metal and the extrinsic substrate generates localized depletion or accumulation region in the substrate. The repulsion force between those regions helps stabilize the nanocrystals and keep a uniform distance between them.

Fig. 3-3 ~ Fig. 3-7 shows the AFM pictures of nanocrystal formation from Co films on top of 3.5 nm thermal oxide and the resulted nanocrystal size distribution. All samples went through the annealing cycle at different temperature for 30s and 60s.

After RTA, well-defined nanocrystals with round shape and certain size distribution

can be achieved. The density of NC is decreased and the size of NC is increased as the RTA annealing temperature is increased. These results show that the greater thermal energy induced agglomeration of the metal wetting layer into the larger NCs. For sample6, we observe very dense nanocrystal formation. It be estimated about 3×10¹¹cm^-2. For the sample7、 sample8、 sample9 and sample10, the dot is baldly bigger than the sample6. But sample6 density is the highest. The higher treatment temperature and time, dots growth larger and the density decreased is agreeable we anticipation. The density for each sample are 1.6×10¹¹cm^-2 (sample7)、1.37×10¹¹cm^-2 (sample8)、0.971×10¹¹cm^-2 (sample9)、0.556×10¹¹cm^-2 (sample10).

3.3.2 Memory characteristics

In order to confirm the memory operation, high-frequency capacitance–voltage (HF C–V) characteristic of a capacitor with a SiO2 –cobalt NC–SiO2 –Al stack was measured, as shown in Fig. 3-9 ~ Fig. 3-12. The observed large hysteresis in HF C–V indicates the charging and discharging process of the NC memory cell. The C-V curves are fail when samples treatment at low temperature (700℃). We guess maybe the metal film treat at low temperature not get enough energy translate film to nanodots. But sample7 although treatment at 700℃, but it C-V curve not express any memory character too. From sample AFM picture Fig. 3-3 and Fig. 3-4, although the dots have formation, but maybe not clear separation in each dot, so that these sample(sample6

design. In these samples, we found the sample8 have a larger flat-band voltage shift than other sample. It have more charge injection into cobalt NCs. And the sample9, it have a flat-band voltage shift up to 2 V too, but operating voltage is higher than sample8. The sample10 observe from its C-V curve, even then gate bias sweeps between 8V and -8V but not express memory window. And the sample10 AFM picture Fig.3-7, we look the lower dot density than other sample (sample10 only 5.56×10¹⁰cm^-2). It maybe a reason explain this phenomenon. In RTO sample we observe each samples have stable C-V curve Fig. 3-8 but not show any memory window. Maybe the Co’s metal-oxide hasn’t trap ability.

3.3.3 Programming/Erase characteristics

Programming transient characteristics of cobalt NC memory devices are demonstrate in Fig. 3-13. Only programming in a low voltage 5V can get an obvious flat-band voltage shift. This is due to the fact that cobalt NC provides considerably greater density of available energy states, resulting in the larger amount of electrons stored inside the NC after programming. We compare Fig. 3-13 and Fig. 3-17, we find in the same programming voltage, sample8 flat-band voltage shift is larger than sample9. This is matching our measure in C-V curve. When operate in Erasing mode the gate apply negative bias, operation time over 0.01s the over-erase situation take place see Fig. 3-14. It maybe the hole be writing into NCs from channel or the free electrons in the cobalt be erasing.

3.3.4 Data retention characteristics

Fig. 3-15 and Fig. 3-19 illustrated the retention characteristics of Co NCs at the room temperature. The retention time is very poor for a nonvolatile memory. The charge loss 76% and it can’t reach 10 year data retention. Sample9 only remain 0.264V flat-band voltage shift and sample10 remain 0.173V flat-band voltage shift. Some charge loss reasons have be mention in chapter 2. In these reasons, we guess the PE-oxide maybe a main reason for charge loses. Because dots in the surface, their inter-distance are very close only tens nanometer. If PE-oxide quality not very good, it will cause large charge loss in NCs. The blocking oxide leakage current illustrated in Fig. 3-21. Except for this reason, according to Liu’s paper [3.7] some dots have inter-connect will induce large leakage current show in Fig. 3-21. The tunneling oxide defect also can make large charge lose, but other experiment can prove the furnace system is clear. One reason can make the tunneling oxide defect generate. When metal film deposition on the tunneling oxide, it rely on heating process to translate metal film into dots. This process is achieved through the relaxation of metal film stress. During stress relaxation, maybe underlay oxide stand the stress. Make the oxide crack or defect generate so that the leakage current get more. Fig. 3-16 and Fig. 3-20 show these samples leakage current.

3.4 Summay

Cobalt general character

Name, Symbol, Number cobalt, Co, 27 Chemical series transition metals

Group, Period, Block 9, 4, d

Density 8.90 g·cm−3

Melting point 1768 K

(1495 °C, 2723 °F)

Boiling point 3200 K

(2927 °C, 5301 °F)

Heat of fusion 16.06 kJ·mol−1

Heat of vaporization 377 kJ·mol−1 Heat capacity (25 °C) 24.81 J·mol−1·K−1

Work function 4.18eV

Table 3-1 Some character about cobalt

Time (s)

Temperature 30s 60s

400℃ Sample1 Sample2

500℃ Sample3 Sample4

600℃ Sample5 Sample6

700℃ Sample7 Sample8

800℃ Sample9

900℃ Sample10

Table 3-2 Experiment split table

Source Drain

Substrate Control Gate(ploy)

Fig. 3-1 2-bit memory device

Bit - 1 Bit - 1

P type (100)

P type (100) P type substrate use pre-furnace RCA clean

Growth 35

Ǻ thin oxide as tunneling oxide

P type (100)

E-Gun evaporator deposited Co

P type (100)

Use RTA system transform Co layer to nanodots

P type (100)

Deposite 250 Ǻ SiO

₂

Deposite Al as

electrode

Fig. 3-3 Co RTA 600℃ 60s sample AFM pictcure

Fig. 3-4 Co RTA 700℃ 30s sample AFM pictcure

Fig. 3-5 Co RTA 700℃ 60s sample AFM pictcure

Fig. 3-7 Co RTA 900℃ 30s sample AFM pictcure

-8 -6 -4 -2 0

1.0x10^-11 2.0x10^-11 3.0x10^-11 4.0x10^-11 5.0x10^-11 6.0x10^-11 7.0x10^-11 8.0x10^-11 9.0x10^-11

Capcitance

VG

0 ~ -8v -8 ~ 0v RTO sample

Fig. 3-8 RTO samples C-V curve

-8 -6 -4 -2 0 2 4

-6 -4 -2 0 2 4 6

1E-4 1E-3 0.01 0.1 1

Erase at different gate voltage

10^-1 10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Normalize V fb shift (%)

Time (s)

700^oC RTA leakage current

Fig. 3-16 RTA 700℃ 60s sample leakage current

1E-4 1E-3 0.01 0.1 1

800^oC 30s sample program at different voltage

Fig. 3-17 RTA 800℃ 30s sample program speed

-0.1 Erase at different gate voltage

10^-1 10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Normalize V fb shift (%)

Time (s) 23%

sample 9 data retention

Fig. 3-19 RTA 800℃ 30s sample data retention

-10 -8 -6 -4 -2 0 2 4 6 8 10 800^oC RTA Leakage current

Fig. 3-20 RTA 800℃ 30s sample leakage current

-10 -8 -6 -4 -2 0 2 4 6 8 10 1E-10

1E-9 1E-8 1E-7 1E-6

Leakage current

VG

0 ~ 10v 0 ~ -10v Oxide 25nm Leakage current

Fig. 3-21 Silicon oxide 25nm leakage current

Chapter 4

Conclusions and recommendations for future works

4.1 Conclusion

In this thesis “The memory characterization and investigation of metal nanocrystal”, we have investigated the memory effects and performance of cobalt metal nanocrystal memory devices. From our experiment, this memory can use low operation voltage to program and erase. But it has a big problem in data retention that is most important for nonvolatile memory. In our sample demonstrate poor data retention. It has some existing problem need analyze and solve that discuss in the before chapter. Maybe we can find another recipe (process) to improve this problem or maybe this metal is not suit for metal nanocrystal nonvolatile memory.

4.2 Recommendation for future works

1)

Use Co and SiO2 co-sputter that can let the Co dots surround by SiO2. It can get batter isolation in each dot.

2) Find other metal material has large work function.

3) Used TEM analysis to find exactly dot density and some problems which make poor retention.

4) Use high-K material and metal dots simultaneously to improve data retention.

5) Use cobalt to manufacture nonvolatile memory device. Some high temperature process step in MOSFET manufacture after metal film anneal must be avoid. High temperature process can make metal dots unstable or affect other character. One high temperature process will be encounter that is after S/D implant anneal. We can use implant S/D and anneal before gate oxide growth. After S/D anneal, star gate oxide growth and following process. And use metal gate TiN can avoid in furnace system that to deposition poly-gate.

References

Chapter 1

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Chapter 2

[2.1] M. White, Y. Yang, P. Ansha and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol.20, pp.190-195, 1997.

[2.2] M. K. Cho and D. M. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology”, IEEE Electron Device Letters, pp.399-401, Vol.21, No.8, 2000.

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