Outline of thesis

In this thesis, voltage tuned dielectric resonator oscillator (VTDRO) and Phase-lock loop controller is discussed in Chapter 2. In Chapter 3, an automatic gain control (AGC) loops that circuit and implementation of the structure is shown. Finally, full structure of Ku-band frequency synthesizer is done.

At the last, the integration of the CMOS RF circuit, including VCO and frequency divider is done in Chapter 4. The conclusions are given in Chapter 5.

Chapter 2

KU-Band Frequency Control Loop Design

In this chapter, we will discuss theory KU-Band frequency control loop design and implementation. The block diagram is shown as figure 2-1.

Data , Clock and LE Control lines

out out

f P .

Dir Coupler

. ( 8) Freq Divider

÷

PLL Circuit Loop Filter

f ref

VTDRO

. RF AMP

Figure 2-1 KU-Band frequency control loop block diagram

2-1 Outline of Theory

2-1-1 Outline of Phase-Lock Loop [3][4]

Figure 2-2 shows a basic Phase-Lock Loop. The compared frequency of the phase detector is

f _comp

and

comp div ref

f

=

f

=

f

(2-1)

The output frequency of the VCO is expressed by

VCO div

f

= ×

N f

(2-2)

The frequency switching is performed by changing the count number N. The spacing between channels is given by

( 1)

ch comp comp comp

f

=

f

×

N

+ −

f

=

f

(2-3)

Figure 2-2 basic Phase-Lock Loop

From (2-3), clearly shows that reference frequency is equal to the frequency spacing. The primary function of loop filter is reducing ripple into the VCO. That bandwidth determines how fast the PLL can correct any phase error. In generally, the resultant versus bandwidth can be describe as follows:

(1) A PLL with narrow bandwidth can reject the input noise but cannot correct the VCO timing errors quickly. The resultant output noise is VCO noise limited and provides more stable PLL design.

(2) A PLL with wider bandwidth can correct VCO errors. However, if the bandwidth is too wide, the resultant system is input noise limited.

In addition, the following categories cover most of the common causes of PLL output noise.

(a) Power supply noise.

(b) PLL dead-zoom region.

(c) Noise from input reference/feedback signal.

(d) Internal switching noise.

(e) Internal and external crosstalk/reflection noise.

Figure 2-3 shows a third order filter topology and constant define as follow:

Figure 2-3 third order filter topology

and transfer function of the loop filter is given by

0 2 2

The close-loop transfer function for figure 2-2 is

0

In this case, (2-6) will be approximated by a second order expression. It is assumed that these higher order terms are small relative to the lower order terms. The Initial Value Theorem (2-7) suggests that the consequences of ignoring these terms are more

on the initial characteristics, such as overshoot, and less on long time behavior, such as lock time.

lim ( ) lim ( )0

s sY s t y t

→∞ = → (2-7) The simplified second order close-loop transfer function expression is

0

Now consider a PLL, which is initially locked at frequency

f

₁, and the N counter is changed such to cause the PLL to switch to frequency

f

₂. It should be noted that the

value for N that is used in all of these equations should be the value of N corresponding to

f

₂. This event is equivalent to changing the reference frequency from

f

¹

N

to

f

²

N

. The first terms in the numerator (2-8) shows the primary effects, and the second expression shows the secondary effects due to the zero. The zero in the transfer function has a lot of effect on the overshoot and the rise time, but has little effect on the lock time.

Using inverse Laplace transforms it follows that the time frequency response is:

2 2 2 2

Since the term in brackets has a maximum value of

2 2

It follows that the lock time in seconds is given by

2

Many times , this is approximated by

2

Figure 2-4 shows the second order model for the frequency response.

F r e q u e n c y

Figure 2-4 second order model for the frequency response

For second order filter, the following relationships exist for loop filters design. These relationships are given by

2

This section describes a method of designing oscillators using small signal S-parameters. Microwave transistors can be used for both amplifier and oscillator application. Form the small signal S-parameters of the transistor, the stability factor k

can be calculated form:

2 2 The k>1 is unconditionally stable of transistor at any frequency. This condition guarantees that at the specified frequency the transistor will not oscillate into any termination at either port that has a positive resistance.

If we can design a circuit for which k<1 and either

Γ

or

Γ _L

is in the unstable region, we will in reality have designed an oscillator (See figure 2-5).

Input

Figure 2-5 Block diagram of microwave oscillator

The necessary conditions for oscillation is given by:

K<1 (2-18)

* 1

S

₁₁Γ =

_r

and

S

₂₂^*Γ =

_L

1 (2-19) If the active device selected has a stability factor grater than one at the desired frequency of oscillation, condition (2-18) can be achieved either by changing the two-port configuration or by adding feedback .For example, the source reactance will define the amount of negative resistance at gat of active device (see figure 2-6).

[ ] ^S

Figure 2-6 negative resistance generator

The new S-parameters will redefine as follower:

From (2-21), we will adjust the electrical length (θ) of open-stub to generation for the

S

₁₁

^T

>1

or S

₂₂

^T

> . Condition (2-19) simply confirms that the oscillator 1 produces power at both ports. If either condition in (2-19) is satisfied, the other condition is automatically satisfied. Once we have achieved k<1, condition (2-19) gives the necessary relationship to complete the oscillator design. We will adopt the technique of resonating the input port and designing a match that satisfies condition (2-19) at the output.

With k<1 we know that an input matching circuit having

Γ _r

which produces 22* 1

S

> can be found. The design condition is therefore

22* 1

S

> (2-22) This condition can be viewed as stating that there is a negative resistance at that output port of the terminated transistor. There are many techniques for realizing such an input circuit, or resonator. One method is to use a computer simulation and optimize for the condition that of the one port consisting of the resonator cascaded with the transistor is greater than unity. A resonator satisfying the property that

S

11

r 1

Γ =

is

lossless. In general, the lossless resonator have cavity resonator,YIG, Dielectric Resonator, lossless transmission lines and lossless lumped Element. With the input circuit established, the load circuit is designed to satisfy

*

1

L

22

Γ =

S

(2-23)

which follows directly form condition (2-19). Note that since

S

22^* > , this equation 1 guarantees

Γ < _L 1

, i.e. the load resistor will be positive.

For the special case where the oscillator is intended to oscillate directly into a 50Ω

load, no load circuit needs to be designed , and the condition for oscillation can be re–expressed . If the load is 50Ω,

Γ = _L 0

. Therefore, since

S

22^* Γ = , we have

_L

1

22*

S

= ∞ . In practices it has proven sufficient to design for

22* 100

S

> (2-24) Satisfying condition (2-19)requires

Γ < _L 0.01

, which corresponds to a load that is essentially 50Ω.

The above method will only predict the frequency of oscillation. It provides no information about output power, harmonics, phase noise, or other parameters of possible interest. In general the output power of the oscillator will approach the 1 dB compression power ( ) of the transistor used as an amplifier if the dc bias is designed for maximum . Other performance parameters would typically have to be measured from the finished oscillator.

P

1dB

P

1dB

2-1-3 Outline of frequency resonator [1][14] [37]

Resonant circuits are importance for oscillator circuit. It will be worthwhile to review some of these by using a lumped RLC parallel network. Figure 2-7 show a typical resonant circuit.

I

Z in

R C L

Figure 2-7 typical resonant circuit

The resonant frequency

ω

₀ is found by

0

1

ω

=

LC

(2-25)

The quality factor is important parameter specifying the frequency selectivity. It general definition given by

Q RC R ω L

= =

ω

(2-26)

Because of resistor R represents the losses in the resonant circuit, The Q is called the unloaded Q and denoted Q. From RLC parallel network, the input impedance can be expressed in a relatively simple form. We have

1 0 1

and

Figure 2-8 BW of resonator plot

The frequency bandwidth between the

0.707R

point is twice this; hence

0 1

If the resonant circuit is coupled to an external load that loading effect can be represented by an additional resistor RL in parallel with R. It is reduce the resistance and the new quality factor is also smaller.

The new quality factor is called the loaded Q and denoted Q

L

. hence

L

Unfortunately, the lumped circuit has too high losses at microwave frequency that are from conductor loss and radiation loss. In order to achieve the purpose of high-quality microwave system, the primary characteristics of the ceramic material to be used for dielectric resonators (DR) are:

(1) The dielectric constant (

ε _r

), which can reduce the size of the DR.

(2) The quality factor (Q), which is approximately equal to the inverse of the loss tangent.

(3) The temperature coefficient of the resonant frequency (

τ _f

), which include the combined effects of the temperature coefficient of the dielectric constant and the thermal expansion of the dielectric resonator and the shielding package.

The dielectric calculations can be performed using techniques given by Kajfez

[2]

. The DR resonates in various mode at frequency determined both by its dimensions and its surroundings. Figure 2-9 shows the cylindrical dielectric is placed on a dielectric substrate. From the electromagnetic wave theory, both magnetic and electric field of outside and inside of dielectric material must satisfy the Maxwell equation and boundary condition.

Z

( ) _s Substrate

ε

( ) _r

DR

ε

Metal

Metal 1

L L

2 L

Air

Figure 2-9 a shows the cylindrical dielectric is placed on a dielectric substrate

In the

TE

_01δ mode, magnetic field lines are contained in the meridian plane while the electric field lines are concentric circles around z-axis as shown in figure 2-10.

For a distant observer, this mode appears as a magnetic dipole, and for this reason it is sometimes referred-to as the “magnetic dipole mode”. When the relative dielectric constant is around 40,more than 95％ of the stored electric energy, and more than 60％

of the stored magnetic energy is located within the cylinder. The remaining energy is distributed in the air around the resonator, decaying rapidly with distance away from the resonator surface.

x y z

H f i e l d E f i e l d

D R

Figure 2-10 Field distribution of

TE

_01δ mode in a DR

The DR is often used in conjunction with a microstrip line. Figure 2-11 a shows the DR coupled to a microstrip line and corresponding equivalent circuit.

Microstrip

Metal Enclosure MetleTunning Screw

DR

h Substrate

(a)

R

r

C

_r

Figure 2-11 Basic DR coupling structure (a) DR coupled to a microstrip line (b) corresponding equivalent circuit

The characteristics in corresponding equivalent circuit of DR are defined by the resonator capacitance(Cr), resonator impedance(Lr), resonator resistance(Rr), while mutual inductance(Lm) give the coupling factor. These parameters are related to the distance from the lines to the DR and surrounding metallic enclosure.

The DR equivalent circuit transforms into parallel RLC resonator in series with the line (see figure 2-12). The RLC value are given by:

2

R r C _r

Figure 2-12 DR equivalent circuit transforms into parallel RLC resonator

This circuit generally provides sufficient accuracy for computer simulation and all parameter are easily extracted via the fitting of measurements.

At the resonant frequency of the DR, The S-parameters of the configuration can be extraction. it are given by[14]:

11

At present, commercially available temperature stable DR materials exhibit dielectric constants of about 36 to 40. Numerous references are available describing the advantages of different ratio in height (h), and diameter (D) from dielectric resonator manufacturers. However, a choice of H/D = 0.4 is recommended to avoid spurious modes oscillations and optimal

Q _U

.

2-1-4 Basic Configuration DRO Type [38]

The basic configurations of the DRO are series feedback and parallel feedback.

Figure 2-13 shows different configurations of each type.

Microstrip line DR

Feedback Element

Matching Network

50Ω RL

Active Device

( ) a

Microstrip line Microstrip line Active Device

Matching Network 50Ω

( ) c

( ) d

Figure 2-13 Basic DRO configurations (a) series feedback DRO (b) VTDRO (c) parallel feedback (d) Push-Push DRO

The Push-Push DRO is special circuit and it uses a common DR for two transistors. The fundamental frequency is cancelled and second harmonics are added at output of the oscillator.

2-2 VTDRO Design Procedures

The Ku-band VTDRO design technique based on small-signal parameter in a linear simulation. The linear simulation will provide a good initial circuit layout. In this thesis, the simulation software of Microwave Office is used.

The DRO can be designed using following design procedure

[14]

: (1) The first step is choosing the DRO configuration.

(2) Select a DR that is resonant at design frequency, and measure the S-parameters of DR with microstrip line.

(3) This step is choosing the active device that is capable of oscillation at the design frequency. The linear S-parameters are taken from manufacturers’ data. A linear simulation will provide a good initial circuit layout before fin tuning the design.

For the available output power, that will then be about 10 to 20 percent of the product

V I _{ds dss}

.

(4) Add a feedback element to ensure that the stability factor of the active device is less than unity. It is negative resistance of active device to make oscillation. For

example, the source reactance will define the amount of negative resistance at gat of active device (see figure 2-14).

Feedback Element

Active Device

g ( ) Z

ω

Matching Network

RL Termination

Network

Figure 2-14 negative resistance of active device

(5) From an active one-port that consists of the feedback element, the active device, the matching network and the load, as shown in figure 2-14.

(6) This step is adjustment of the electrical length (θ) to compensate for the imaginary part of

Z _g

( )

ω

by the opposite value (see figure 2-15).

Microstrip line

Figure 2-15 VTDRO design configuration

2-2-1 Frequency Resonator Simulations

In this case, the Ku-band DRO design was achieved by the design procedure.

The DRO configuration chosen is series feedback VTDRO (see figure 2-13(b)), An advantage of the series feedback design is the relative ease of coupling to a single line, compared to the parallel circuit’s requirement for coupling to two lines. The parameters of DR acquirement show as follows:

1.We can be extracted parameters of DR by the network analyzer.

2.The parameter is providing by the manufacturers.

From method 1, the DR is placed on top of the microstrip substrate in the metal

enclosure and extracting the intrinsic parameters of the DR equivalent circuit. We can be extracted parameters of DR by the network analyzer. This is easily achieved with the use of software programs such as microwave offices. Figure 2-16 shows the measurement setup of DR.

d DR D

Microstrip line

Network Analyser

Port 1 (S11) Port 2 (S22)

DUT (include PCB with shield)

Figure 2-16 DR parameter measurement setup

In this case, we took parameters from Trans-Tech Inc. Figure 2-18 shows the module and simulation result.

MLIN

(b)

Figure 2-18 DR module for software (a) equivalent circuit (b) simulation result

2-2-2 Negative Resister Generator Simulations

The active device chosen is a NE54586 FET and the small-signal parameters are given for a bias of

V _ds

=2

V

at

I _ds

=10

mA

. In the drain of FET, the matching circuit was optimized at design frequency. Because of the structure is easy tuning, the feedback element chosen is a open-stub . It is connect with gate of FET. The open-stub is optimized so that the real part of the gate is as negative as possible. Figure 2-19 shows the one-port topology and simulation value.

MLOC

(b)

Figure 2-19 The negative resister generator of NE54586 simulation circuit

2-2-3 VTDRO Measurement

The final linear circuit is provided in figure 2-20. We can adjustment of the electrical length (θ) to compensate for the imaginary part of

Z _g

( )

ω

by the opposite value . The linear simulation will provide a good initial circuit layout before fine tuning . Figure 2-22 presents the layout of the DRO that was tested. Figure 2-23 and figure 2-24 presents the measured output power and phase noise performance that was achieved.

Figure 2-25 presents the measured frequency tune range.

Microstrip line DR

Feedback Element 50Ω

Microstrip line Frequency Control Voltage

Matching Network

RL Termination

Network Varactor Diode

(MA46470_1056)

NE54586

θ

Figure 2-20 VTDRO block diagram

(a)

(b)

Figure 2-22 Layout and module of the VTDRO (a) layout (b) VTDRO module

(a)

(b)

Figure 2-23 VTDRO Output measure (a) Output power spectrum (b) Output power flatness.

Figure 2-24 VTDRO phase noise @ 100 KHz

VTDRO Tunning Range

11.2 11.21 11.22 11.23 11.24 11.25 11.26 11.27 11.28 11.29

0 2 4 6 8 10 12 14

Control Voltage (V)

Output Frequency (GHz)

數列1

Figure 2-25 VTDRO frequency tune range

2-3 Microwave Amplifier and Direction Coupler Design

The amplifier and direction coupler provide the amplitude gain and tape amplitude from main signal path. They can be performed using techniques given by McGraw-Hill[1]. In this case, the amplifier device is NBB-300. It is broadband InGaP/GaAs MMIC amplifier and provides 8dB gain from 11GHz to 12 GHz. We illustrate a microstrip directional coupler that involves two coupled microstrip lines.

The design frequency is 11.25 GHz and coupling of -13 dB.

2-4 PLL Controller Design

The PLL controller schematic is shown as figure 2-35. The controller uses a serial interface from a computer to load data to the PLL chip. PLL chip of LMX1600L frequency operates up to 2.5GHz. The HMC363S8G is a low noise divide-by-8 static divider. This device operates from dc to 12GHz input frequency with a single +5.0V DC supply.

Figure 2-35 PLL controller schematic

The loop filter integrates the pulsed output from the phase detector to produce a smoothed "DC" VCO control voltage. The loop performance can be set by varying the component values in the loop filter.

The simplest is an RC low pass section (see figure 2-36 (a)). This will always include a second resistor in series with the capacitor. A further section of RC filtering can be added to produce a third order loop with improved sideband and noise performance(see figure 2-36 (b)). However it is more difficult to analyse higher order loops for stability and other parameters. If a simple RC filter is used, the VCO control voltage swing is limited to 0-5V in systems with a digital phase detector. For best phase noise performance it is necessary to use the full available control range of the varactor diode. To do this, a second OP amplifier can be configured as a DC amplifier to bring the output voltage to a higher figure (see figure 2-36 (c)). All components in the loop filter should be designed for low noise (eg. low noise OP amplifier and metal film resistors). The calculation of loop filter is shown in Appendix A.

R1

R2

C2

C1 +15V

Output Input

R1

R2

C2 C1 From phase

detector To VCO

R1

R2

C2 From phase

detector To VCO

(a) (b)

(c) Vref

Figure 2-36 Loop filter type (a) basic second order filter (b) passive third order filter (c) active third order filter

2-5 KU-Band frequency control loop measurement

Figure 2-37 shows the KU-Band frequency control loop measurement setup diagram. This is the software that can be used to program a PLL via the parallel port of a computer. The software introduction is shown in Appendix B.

Parallel Port

Spectrum analyser

NoteBook

DUT

Data , Clock and LE Control lines

out

out

f P .

Dir Coupler

. ( 8) Freq Divider

÷

PLL Circuit Loop Filter

f

ref

VTDRO

. RF AMP

Figure 2-37 KU-Band frequency control loop measurement setup diagram

Figure 2-38 is the lock-in time measurement of frequency control loop. Figure2-39 shows the spurious of the reference frequency leakage. The spur due to reference leakage is about 66.8 dBc. Figure 2-40 is the phase noise measurement of Ku-band frequency control loop. The value of phase noise is 97.17 dBc/Hz at 100KHz offset.

Figure 2-38 Lock-in time measurement of frequency control loop (11.225GHz jump to 11.275GHz)

Figure 2-39 Spurious of the reference frequency leakage

Figure 2-40 phase noise measurement of Ku-band frequency control loop at 100KHz offset

Chapter 3

RF Power Control Loop

In this chapter, we will discussed theory and design of the RF power automatic gain control (AGC) loop. The block diagram is shown as figure 3-1.

.

DC Level Sh ift Low Pass Filter

Figure 3-1 RF Power Control Loop block diagram

The function of RF control loop discussed as follow:

1、The input signal passes through the VCA to produce the output level to be stabilized.

The D/A converter was set by the computer and produces a reference DC voltage (AGC Set voltage).

2、The directional coupler tap the output power and feed it to RF detector and produces

a DC voltage proportional to the RF output power.

3、The DC amplifier provides a DC gain and produce detector’s output voltage.

4、The detector’s output voltage is compared against a AGC Set voltage to produce an

error signal, which is then integrated to produce a control positive voltage.

5、The DC level shift circuit transforms the control positive voltage into negative voltage for the VCA and adjusts RF output power.

3-1 Outline of Power Control Loop 3-1-1 Outline of AGC [5][6][19]

Many attempts have been made to fully describe an AGC system in terms of control system theory, from pseudo linear approximations to multivariable systems. Each model has its advantages and disadvantages, first order models are easy to analyze and understand but sometimes the final results show a high degree of inaccuracy when they are compared with practical results. On the other hand, non-linear and multivariable systems show a relative high degree of accuracy but the

theory and physical implementation of the system can become really tedious.

The basic block of automatic gain control loop show in figure 3-2. The input signal is amplified by a variable gain block (VGB) whose gain is controlled by a control

voltage . A cascade amplifier to generate and adequate level of can amplify the output from the VGB. The power detector senses the output level, any undesired component is filtered out and the remaining signal is compared with a reference signal

voltage . A cascade amplifier to generate and adequate level of can amplify the output from the VGB. The power detector senses the output level, any undesired component is filtered out and the remaining signal is compared with a reference signal

在文檔中 KU-Band 頻率合成器設計 (頁 14-0)