KU-Band 頻率合成器設計

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(1)國立交通大學電機資訊學院電信學程碩士論文. KU-Band 頻率合成器設計. KU-Band frequency synthesizer design. 研究生：林明忠指導教授：周復芳. 教授. 中華民國九十三年六月 i.

(2) 授權書 (博碩士論文). 本授權書所授權之論文為本人在國立交通大學(學院) 電機資訊學院專班系所電. 信組九十二學年度第二學期取得碩士學位之論文。論文名稱： KU-Band 頻率合成器設計 1.■同意 □不同意本人具有著作財產權之論文全文資料，授予行政院國家科學委員會科學技術資料中心、國家圖書館及本人畢業學校圖書館，得不限地域、時間與次數以微縮、光碟或數位化等各種方式重製後散布發行或上載網路。本論文為本人向經濟部智慧財產局申請專利的附件之一，請將全文資料延後兩年後再公開。(請註明文號: ). 2.■同意 □不同意本人具有著作財產權之論文全文資料，授予教育部指定送繳之圖書館及本人畢業學校圖書館，為學術研究之目的以各種方法重製，或為上述目的再授權他人以各種方法重製，不限地域與時間，惟每人以一份為限。上述授權內容均無須訂立讓與及授權契約書。依本授權之發行權為非專屬性發行權利。依本授權所為之收錄、重製、發行及學術研發利用均為無償。上述同意與不同意之欄位若未鉤選，本人同意視同授權。指導教授姓名：周復芳. 研究生簽名：（親筆正楷）. 林明忠. 日期：民國. 93. 年. 學號： 8967553 （務必填寫） 7. 月. 1. 日. 1. 本授權書請以黑筆撰寫並影印裝訂於書名頁之次頁。 2. 授權第一項者，所繳的論文本將由註冊組彙總寄交國科會科學技術資料中心。 3. 本授權書已於民國 85 年 4 月 10 日送請內政部著作權委員會（現為經濟部智慧財產局）修正定稿。 4. 本案依據教育部國家圖書館 85.4.19 台(85)圖編字第 712 號函辦理。. ii.

(3) KU-Band 頻率合成器設計 KU-Band frequency synthesizer design. 研究生：林明忠. Student：MING-CHUNG LIN. 指導教授：周復芳. Advisor：Christina F. Jou. 國立交通大學電機資訊學院電信學程碩士論文. A Thesis Submitted to Degree Program of Electrical EngineeringComputer Science College of Electrical Engineering and Computer Science National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master of Science in Communication Engineering June 2004 Hsinchu, Taiwan, Republic of China. 中華民國九十三年六月. iii.

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(5) KU-Band 頻率合成器設計學生：林明忠. 指導教授：周復芳教授. 國立交通大學電機資訊學院電信學程﹙研究所﹚碩士班. 摘. 要. 本論文主要分為二部份，使用離散元件(distributed component)設計 Ku-band 頻率合成器及利用 0.25um CMOS 技術來模擬 5GHz RF 電路。在 Ku-band 的頻率合成器的設計上，以壓控介質振盪器(VTDRO)為基礎，加上鎖相迴路(PLL)及自動增益控制(AGC)電路。其中，PLL 電路將根據控制界面的設定值，來控制 VTDRO 的頻率。而 AGC 電路使整個頻率合成器的輸出功率保持在一個固定值，改善 VTDRO 因為輸出頻率的變化而產生輸出功率的變動(output power flatness) 。相對的，AGC 電路也能根據控制界面的設定值，來控制 VTDRO 的輸出功率。最後我們利用 LabVIEW*來設計控制界面，使頻率合成器的頻率和輸出功率皆能被電腦的 Print port 控制和設定。最後，頻率合成器的頻率可由 11.22GHz 到 11.28GHz 之間變換，相位雜訊為–96dBc/Hz at 100kHz，輸出功率平坦度為 +0.62dB，輸出功率從+4dBm 到 –15dBm。在第二部份，利用 0.25um CMOS 技術來模擬 5GHz 壓控振盪器和除頻器電路。整理出積體電路(integrated circuit) 在設計上所必須遵行的流程與準則。 * : LabVIEW 是由 National Instruments 所發展的圖控系統。. v.

(6) KU-Band frequency synthesizer design student：MING-CHUNG LIN. Advisors：Christina F. Jou. Degree Program of Electrical Engineering Computer Science National Chiao Tung University ABSTRACT. The thesis is divided into two parts. In the section 1, we describe the Ku-band synthesizer. Section 2 describes the CMOS RF circuits simulation for the 5GHz frequency range. In the Ku-band synthesizer, the voltage tuned dielectric resonator oscillator (VTDRO), Phase-locked loop (PLL) controller and automatic gain control (AGC) circuits are combined by the distributed devices. The synthesizer frequency and output power level could be control by PLL and AGC control loop. Finally, the measured phase noise is –96dBc/Hz at 100kHz offset from 11.25GH. The dynamic range of output power from +4dBm to –15dBm was achieved by the AGC function and +0.62dB output power flatness. In the CMOS RF circuits simulation section, the 5GHz LC-tank voltage controlled oscillator and high frequency divider has been designed in a standard 0.25u CMOS process.. vi.

(7) 誌. 謝. 在此感謝周老師的熱心指導及實驗學長學弟的幫忙，才能順利完成本論文。另外，也感謝家人的支持，才能使我順利完成學業。. vii.

(8) 目. 錄. 中文提要英文提要誌謝. …………………………………………………………………………….... 一、. Introduction. 1.1 1.2 1.3 二、 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.2.2 2.2.3 2.3 2.4 2.5 三、 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.2.3. ……………………………………………………………………………... …………………………………………………………………………….... ………………………………………..…………………….. Outline of Ku-band synthesizer. …….……………………..…………. Outline of CMOS RF circuit simulation Outline of thesis. 1 1. ….…………..…………….... 5. ………………………………………………………. 5. KU-Band Frequency Control Loop Design Outline of Theory. v vi vii. ……………………………... 6. ……………………………………………………... 7. Outline of Phase-Lock Loop Outline of Oscillator. ……………………………………….. 7. ……………………………………………….. 12. Outline of frequency resonator. …………………………………….. 17. ……………………………………. 24. VTDRO Design Procedures ………………………………………….. 26. Basic Configuration DRO Type Frequency Resonator Simulations. …………………………………. Negative Resister Generator Simulations VTDRO Measurement. ………………………….. 31. …………………………………………….. 33. Microwave Amplifier and Direction Coupler Design PLL Controller Design. ………………... 38. ……………………………………………….. 38. KU-Band frequency control loop measurement RF Power Control Loop. 28. …………………….... 41. …………………………………………………. 45. Outline of Power Control Loop. ………………………………………. 46. Outline of AGC …………………………………………………….. 46. Outline of VCA …………………………………………………….. 55. Power Control Loop Design. ………………………………………….. Ku-band Power Detector Design. 58. …………………………………... 58. Ku-band VCA Design …………………………………………….... 60. AGC Loop Design …………………………………………………. 63. viii.

(9) 3.3. Power Control Loop Measurements. ………………………………….. 四、 4.1 4.1.1 4.1.2 4.2 4.2.1 五、. CMOS LC Oscillator and Frequency Divider Design. ………………………………………………………………. 65 69 70 72 75 79 82 87. Reference Appendix A Appendix B. ……………………………………………………………………………... ……………………………………………………………………………... …………………………………………………………………………….... 89 94 97. …………………... CMOS Voltage controlled oscillator (VCO) Design Topology of an NMOS-PMOS LC oscillator. …………………. …………………….... Simulation result of a 5GHz NMOS-PMOS LC VCO ……………. Frequency divider design. ……………………………………………... Simulation result of a 5GHz frequency divider Conclusion. ix. …………………….

(10) Chapter 1 Introduction The thesis is divided into two parts. In the section 1, we describe the Ku-band synthesizer. The major goals in the design of a Ku-band frequency synthesizer are achieve low phase noise and output power can be set. Section 2 describes the CMOS RF circuit simulation for the 5GHz frequency range.. 1-1 Outline of Ku-band synthesizer Nowadays in communication technology, the communication system, were all requests to have the stable communication frequency, the channel switching and stable input/output power. Figure1-1 shows the conventions Ku-band frequency synthesizer. The structure can be tuned frequency by the Phase-locked loop (PLL) control lines and the output power is fixed. Unfortunately, the output power was changed by the tuning frequency of Voltage Controlled Oscillator. (See figure1-2). 1.

(11) VCO f out. Dir. Coupler. Loop Filter. Pout. PLL Circuit Control Lines f ref. Figure 1-1 the structure of conventions Ku-band frequency synthesizer. Pout. ∆P. fL. fH. f. Figure 1-2 the output spectrum conventions Ku-band frequency synthesizer. The amplitude stability method of oscillator is presented. [40][41][42][43].. Conventional diagram are shown in figure1-3. The Diode is automatic gain control (AGC) circuit and it controls the active device current and stables the amplitude of oscillator. In this thesis, we will discuss how to achieve frequency and power level control loops.. 2.

(12) -β (AGC). K. Resonator. +α (a). Output Match and Resnator. RL. Active Device C. R. D L R. (b) Figure 1-3 the convention diagram of Oscillator with AGC circuit (a) convention diagram (b) typical circuit. Usually, if we add AGC circuit into oscillator, we'll consider some condition. The condition shows as follows: (1) In the fast channel switch case, oscillator maybe cannot oscillation. (2) Keeping open loop gain of oscillator on the width temperature range operation. The suitable open loop gain can reduce phase noise.. 3.

(13) The Ku-band frequency synthesizer of this thesis is shown as figure 1-4. The voltage tuned dielectric resonator oscillator (VTDRO), Phase-locked loop (PLL) controller and automatic gain control (AGC) circuits are combined by the distributed devices. The VTDRO produced high quality Ku-band frequency and output power. PLL controller does changing frequency of VTDRO. The flatness of output power can be compensated by the AGC function (see figure figure1-5). VTDRO. RF VCA. RF AMP.. RF AMP. Dir. Coupler. Dir. Coupler Freq. Divider (÷8). RF AMP. DC Level Sh ift Low Pass Filter. Loop Filter f ref PLL Circuit. RF Detector. Integrator +. C. 12 bit D / A. PLL Control Lines. C onverter. AGC Set. RF Signal Set. R. DC Amp.. LabVIEW. Parallel Port. Figure 1-4 the structure of new Ku-band frequency synthesizer. Pout PH. Dynamic Ramge PL. fL. fH. f. Figure 1-5 the output spectrum new Ku-band frequency synthesizer. 4. f out Pout.

(14) In other words, the synthesizer frequency and output power level could be control by PLL and AGC control loop. Finally, the measured phase noise is –96dBc/Hz at 100kHz offset from 11.25GH. The dynamic range of output power from +4dBm to –15dBm was achieved by the AGC function and 75MHz bandwidth frequency tuned range.. 1-2 Outline of CMOS RF circuit simulation In the CMOS RF circuit simulation section, the 5GHz LC-tank voltage controlled oscillator and high frequency divider has been designed in a standard 0.25u CMOS process.. 1-3 Outline of thesis. In this thesis, voltage tuned dielectric resonator oscillator (VTDRO) and Phase-lock loop controller is discussed in Chapter 2. In Chapter 3, an automatic gain control (AGC) loops that circuit and implementation of the structure is shown. Finally, full structure of Ku-band frequency synthesizer is done.. At the last, the integration of the CMOS RF circuit, including VCO and frequency divider is done in Chapter 4. The conclusions are given in Chapter 5.. 5.

(15) Chapter 2 KU-Band Frequency Control Loop Design. In this chapter, we will discuss theory KU-Band frequency control loop design and implementation. The block diagram is shown as figure 2-1.. VTDRO. RF AMP. Dir. Coupler Freq. Divider (÷8). Loop Filter f ref PLL Circuit. Data , Clock and LE Control lines. Figure 2-1 KU-Band frequency control loop block diagram. 6. f out Pout.

(16) 2-1 Outline of Theory. 2-1-1 Outline of Phase-Lock Loop [3][4]. Figure 2-2 shows a basic Phase-Lock Loop. The compared frequency of the phase detector is f comp and. f comp = f div = f ref. (2-1). The output frequency of the VCO is expressed by fVCO = N × f div. (2-2). The frequency switching is performed by changing the count number N. The spacing between channels is given by f ch = f comp × ( N + 1) − f comp = f comp. (2-3). VCO f ref. Phase Detector. Loop Filter. Kφ. Z (s). fVCO. KVCO s. f div =. fVCO N. Frequency Divider 1/N. Figure 2-2 basic Phase-Lock Loop. 7.

(17) From (2-3), clearly shows that reference frequency is equal to the frequency spacing. The primary function of loop filter is reducing ripple into the VCO. That bandwidth determines how fast the PLL can correct any phase error. In generally, the resultant versus bandwidth can be describe as follows: (1) A PLL with narrow bandwidth can reject the input noise but cannot correct the VCO timing errors quickly. The resultant output noise is VCO noise limited and provides more stable PLL design. (2) A PLL with wider bandwidth can correct VCO errors. However, if the bandwidth is too wide, the resultant system is input noise limited.. In addition, the following categories cover most of the common causes of PLL output noise. (a) Power supply noise. (b) PLL dead-zoom region. (c) Noise from input reference/feedback signal. (d) Internal switching noise. (e) Internal and external crosstalk/reflection noise.. 8.

(18) Figure 2-3 shows a third order filter topology and constant define as follow:. R3. From Charge Pump. C1. To VCO. R2. C3. C2. Figure 2-3 third order filter topology. and transfer function of the loop filter is given by T0 = C2 R2 T1 = C1C2C3 R2 R3 T2 = C2C3 R2 + C1C2 R2 + C1C3 R3 + C2C3 R3. (2-4). T3 = C1 + C2 + C3. and Z ( s) =. 1 + sT0 s[ s T1 + sT2 + T3 ]. (2-5). 2. The close-loop transfer function for figure 2-2 is Z CL ( s ) =. Kφ KVCO N (1 + sT0 ) s NT1 + s NT2 + s 2 NT3 + sKφ KVCOTo + Kφ KVCO 4. 3. (2-6). In this case, (2-6) will be approximated by a second order expression. It is assumed that these higher order terms are small relative to the lower order terms. The Initial Value Theorem (2-7) suggests that the consequences of ignoring these terms are more 9.

(19) on the initial characteristics, such as overshoot, and less on long time behavior, such as lock time.. lim sY ( s ) = lim y (t ) s →∞. (2-7). t →0. The simplified second order close-loop transfer function expression is Kφ KVCO ](1 + sNT0 ) NT3 Z CL ( s ) = Kφ KVCOT0 s 2 + s( ) T3 N [. (2-8). and. ωn =. Kφ KVCO N (C1 + C2 + C3 ). (2-9). RCω ξ= 2 2 n 2 It can be seen that the poles of this function are at: −ξω n ± jω n 1 − ξ 2. (2-10). Now consider a PLL, which is initially locked at frequency f1 , and the N counter is changed such to cause the PLL to switch to frequency f 2 . It should be noted that the value for N that is used in all of these equations should be the value of N corresponding to f 2 . This event is equivalent to changing the reference frequency from. f1 f to 2 . N N. The first terms in the numerator (2-8) shows the primary effects, and the second expression shows the secondary effects due to the zero. The zero in the transfer function has a lot of effect on the overshoot and the rise time, but has little effect on the lock time. Using inverse Laplace transforms it follows that the time frequency response is:. 10.

(20) F (t ) = f 2 + ( f1 − f 2 )e−ξωnt [cos(ω n t 1 − ξ 2 ) +. ξ − R2C2ω n 1−ξ. 2. sin(ω nt 1 − ξ 2 )]. (2-11). Since the term in brackets has a maximum value of 1 − 2ξ R2C2ω n + R2 C2 ω n 2. 2. (2-12). 1−ξ 2 It follows that the lock time in seconds is given by. − ln[ LockTime =. 1−ξ 2 tol ] f 2 − f1 1 − 2ξ R2C2ω n + R2 2C2 2ω n. (2-13). ξω n. Many times , this is approximated by − ln[ LockTime =. tol 1−ξ 2 ] f 2 − f1. (2-14). ξω n. Figure 2-4 shows the second order model for the frequency response. V. F in a l F requ en cy. F re q u e n c y Ju m p. e −ξω nt. I n itia l F requ en cy. T im e. Figure 2-4 second order model for the frequency response. 11.

(21) For second order filter, the following relationships exist for loop filters design. These relationships are given by. ω c = 2ξω n sec φ − tan φ =. (2-15). 1 4ξ 2. 2-1-2 Outline of Oscillator [1][39] This section describes a method of designing oscillators using small signal S-parameters. Microwave transistors can be used for both amplifier and oscillator application. Form the small signal S-parameters of the transistor, the stability factor k can be calculated form: 1 + D − S11 − S22 2. k=. 2. 2. (2-16). 2 S21 S12. where D = S11S 22 − S 21S12. (2-17). The k>1 is unconditionally stable of transistor at any frequency. This condition guarantees that at the specified frequency the transistor will not oscillate into any termination at either port that has a positive resistance. If we can design a circuit for which k<1 and either Γ r or Γ L is in the unstable region, we will in reality have designed an oscillator (See figure 2-5).. 12.

(22) Transistor s parameters k<1. Input Resonator Γ r S11*. Output Match. RL. S 22* Γ L. Figure 2-5 Block diagram of microwave oscillator. The necessary conditions for oscillation is given by: K<1. (2-18). * S11* Γ r = 1 and S 22 ΓL = 1. (2-19). If the active device selected has a stability factor grater than one at the desired frequency of oscillation, condition (2-18) can be achieved either by changing the two-port configuration or by adding feedback .For example, the source reactance will define the amount of negative resistance at gat of active device (see figure 2-6).. [S ]. D. G. =. Γz. θ. G. Tow Port. ⎡⎣ S T ⎤⎦. Open − Stub. Figure 2-6 negative resistance generator 13. D.

(23) The new S-parameters will redefine as follower:. ⎡ S11 [ S ] = ⎢⎢ S21 ⎢⎣ S31. ⎡ST ⎡⎣ S T ⎤⎦ = ⎢ 11T ⎣ S 21. S12 S 22 S32. S13 ⎤ S 23 ⎥⎥ S33 ⎥⎦. S31S13Γ z ⎡ S + 11 1 − S33Γ z S12T ⎤ ⎢ =⎢ T ⎥ S31S 23Γ z S 22 ⎦ ⎢ ⎢ S21 + 1 − S Γ 33 z ⎣. (2-20). S13 S32 Γ z ⎤ 1 − S33Γ z ⎥ ⎥ S23 S32 Γ z ⎥ S22 + 1 − S33Γ z ⎥⎦ S12 +. (2-21). From (2-21), we will adjust the electrical length (θ) of open-stub to generation T for the S11T > 1 or S 22 > 1 . Condition (2-19) simply confirms that the oscillator. produces power at both ports. If either condition in (2-19) is satisfied, the other condition is automatically satisfied. Once we have achieved k<1, condition (2-19) gives the necessary relationship to complete the oscillator design. We will adopt the technique of resonating the input port and designing a match that satisfies condition (2-19) at the output.. With k<1 we know that an input matching circuit having Γ r which produces. S 22* > 1 can be found. The design condition is therefore. 14.

(24) S 22* > 1. (2-22). This condition can be viewed as stating that there is a negative resistance at that output port of the terminated transistor. There are many techniques for realizing such an input circuit, or resonator. One method is to use a computer simulation and optimize for the condition that S11 of the one port consisting of the resonator cascaded with the transistor is greater than unity. A resonator satisfying the property that Γ r = 1 is lossless. In general, the lossless resonator have cavity resonator,YIG, Dielectric Resonator, lossless transmission lines and lossless lumped Element. With the input circuit established, the load circuit is designed to satisfy. ΓL =. 1 S 22*. (2-23). which follows directly form condition (2-19). Note that since S 22* > 1 , this equation guarantees Γ L < 1 , i.e. the load resistor will be positive. For the special case where the oscillator is intended to oscillate directly into a 50Ω load, no load circuit needs to be designed , and the condition for oscillation can be re–expressed . If the load is 50Ω, Γ L = 0 . Therefore, since S 22* Γ L = 1 , we have S 22* = ∞ . In practices it has proven sufficient to design for. 15.

(25) S 22* > 100. (2-24). Satisfying condition (2-19)requires Γ L < 0.01 , which corresponds to a load that is essentially 50Ω. The above method will only predict the frequency of oscillation. It provides no information about output power, harmonics, phase noise, or other parameters of possible interest. In general the output power of the oscillator will approach the 1 dB compression power ( P1dB ) of the transistor used as an amplifier if the dc bias is designed for maximum P1dB . Other performance parameters would typically have to be measured from the finished oscillator.. 16.

(26) 2-1-3 Outline of frequency resonator [1][14] [37] Resonant circuits are importance for oscillator circuit. It will be worthwhile to review some of these by using a lumped RLC parallel network. Figure 2-7 show a typical resonant circuit.. I C. R. L. Z in. Figure 2-7 typical resonant circuit. The resonant frequency ω 0 is found by. ω0 =. 1 LC. (2-25). The quality factor is important parameter specifying the frequency selectivity. It general definition given by Q = ω RC =. R ωL. (2-26). Because of resistor R represents the losses in the resonant circuit, The Q is called the unloaded Q and denoted Q. From RLC parallel network, the input impedance can be expressed in a relatively simple form. We have 1−. Z in = (. ∆ω. ω 0 −1 1 1 1 + + jω C ) −1 = ( + jω 0C + j ∆ω C + ) R jω L R jω 0 L 17. (2-27).

(27) and. ω = ω 0 + ∆ω A plot of Z in as a function of. (2-28) ∆ω. ω0. is given in figure 2-8. Z in R. 0.707R Z in. +900. ∆ω. ω0. ∠Z in −900. BW. Figure 2-8 BW of resonator plot. The frequency bandwidth between the 0.707R point is twice this; hence Q=. ω0 1 = 2∆ω BW. (2-29). If the resonant circuit is coupled to an external load that loading effect can be represented by an additional resistor RL in parallel with R. It is reduce the resistance and the new quality factor is also smaller. The new quality factor is called the loaded Q and denoted QL. hence RRL QL =. R + RL ωL. (2-30) 18.

(28) Unfortunately, the lumped circuit has too high losses at microwave frequency that are from conductor loss and radiation loss. In order to achieve the purpose of high-quality microwave system, the primary characteristics of the ceramic material to be used for dielectric resonators (DR) are: (1) The dielectric constant ( ε r ), which can reduce the size of the DR. (2) The quality factor (Q), which is approximately equal to the inverse of the loss tangent. (3) The temperature coefficient of the resonant frequency ( τ f ), which include the combined effects of the temperature coefficient of the dielectric constant and the thermal expansion of the dielectric resonator and the shielding package.. The dielectric calculations can be performed using techniques given by Kajfez[2]. The DR resonates in various mode at frequency determined both by its dimensions and its surroundings. Figure 2-9 shows the cylindrical dielectric is placed on a dielectric substrate. From the electromagnetic wave theory, both magnetic and electric field of outside and inside of dielectric material must satisfy the Maxwell equation and boundary condition.. 19.

(29) Z Metal. L1. Air. DR(ε r ). L. Substrate(ε s ). L2. Metal. Figure 2-9 a shows the cylindrical dielectric is placed on a dielectric substrate. In the TE01δ mode, magnetic field lines are contained in the meridian plane while the electric field lines are concentric circles around z-axis as shown in figure 2-10. For a distant observer, this mode appears as a magnetic dipole, and for this reason it is sometimes referred-to as the “magnetic dipole mode”. When the relative dielectric constant is around 40,more than 95％ of the stored electric energy, and more than 60％ of the stored magnetic energy is located within the cylinder. The remaining energy is distributed in the air around the resonator, decaying rapidly with distance away from the resonator surface.. 20.

(30) z E fie ld. H fie ld. x. y. DR. Figure 2-10 Field distribution of TE01δ mode in a DR. The DR is often used in conjunction with a microstrip line. Figure 2-11 a shows the DR coupled to a microstrip line and corresponding equivalent circuit.. MetleTunning Screw. Metal Enclosure. Microstrip. DR. Substrate. (a). 21. h.

(31) D. DR. Rr d. Zo. Microstrip line. =. Lr. Cr. Lm. Zo. Zo. Zo. Figure 2-11 Basic DR coupling structure (a) DR coupled to a microstrip line (b) corresponding equivalent circuit. The characteristics in corresponding equivalent circuit of DR are defined by the resonator capacitance(Cr), resonator impedance(Lr), resonator resistance(Rr), while mutual inductance(Lm) give the coupling factor. These parameters are related to the distance from the lines to the DR and surrounding metallic enclosure. The DR equivalent circuit transforms into parallel RLC resonator in series with the line (see figure 2-12). The RLC value are given by: R = ω 0QU. L2m Lr. (2-31). L=. L2m Lr. (2-32). C=. Lr ω o2 L. (2-33). 22.

(32) L Rr. Lr. Cr. Zo. R. =. Lm. Zo. Zo. C. Zo. Figure 2-12 DR equivalent circuit transforms into parallel RLC resonator. This circuit generally provides sufficient accuracy for computer simulation and all parameter are easily extracted via the fitting of measurements. At the resonant frequency of the DR, The S-parameters of the configuration can be extraction. it are given by[14]:. β=. QU R R S = = = 11 QE RE 2 Z 0 S21. (2-34). The QU is the unloaded Q of the circuit. That is. QU =. ω R = ω o RC = 0 BW ωo L. (2-35). 23.

(33) At present, commercially available temperature stable DR materials exhibit dielectric constants of about 36 to 40. Numerous references are available describing the advantages of different ratio in height (h), and diameter (D) from dielectric resonator manufacturers. However, a choice of H/D = 0.4 is recommended to avoid spurious modes oscillations and optimal QU .. 2-1-4 Basic Configuration DRO Type [38] The basic configurations of the DRO are series feedback and parallel feedback. Figure 2-13 shows different configurations of each type.. Matching Network. DR. RL. 50Ω Microstrip line. Active Device Feedback Element. (a). 24.

(34) Frequency Control Voltage. Varactor Diode Microstrip line. Matching. DR. Network 50Ω. RL. Active Device. Microstrip line. Feedback Element. (b ). Microstrip line. DR 50Ω. Microstrip line. Active Device. Matching Network. RL. (c ). 50Ω. Microstrip line. Active Device. Matching DR. Network RL. 50Ω. Microstrip line. Active Device. (d ). Figure 2-13 Basic DRO configurations (a) series feedback DRO (b) VTDRO (c) parallel feedback (d) Push-Push DRO. 25.

(35) The Push-Push DRO is special circuit and it uses a common DR for two transistors. The fundamental frequency is cancelled and second harmonics are added at output of the oscillator.. 2-2 VTDRO Design Procedures The Ku-band VTDRO design technique based on small-signal parameter in a linear simulation. The linear simulation will provide a good initial circuit layout. In this thesis, the simulation software of Microwave Office is used. The DRO can be designed using following design procedure [14]: (1) The first step is choosing the DRO configuration. (2) Select a DR that is resonant at design frequency, and measure the S-parameters of DR with microstrip line. (3) This step is choosing the active device that is capable of oscillation at the design frequency. The linear S-parameters are taken from manufacturers’ data. A linear simulation will provide a good initial circuit layout before fin tuning the design. For the available output power, that will then be about 10 to 20 percent of the product Vds I dss . (4) Add a feedback element to ensure that the stability factor of the active device is less than unity. It is negative resistance of active device to make oscillation. For. 26.

(36) example, the source reactance will define the amount of negative resistance at gat of active device (see figure 2-14).. Z g (ω ). Termination Network. Active Device. Matching Network RL. Feedback Element. Figure 2-14 negative resistance of active device. (5) From an active one-port that consists of the feedback element, the active device, the matching network and the load, as shown in figure 2-14. (6) This step is adjustment of the electrical length ( θ ) to compensate for the imaginary part of Z g (ω ) by the opposite value (see figure 2-15).. 27.

(37) Frequency Control Voltage. Z r (ω ) Rr. Lr. Z g (ω ). Cr. Termination Network. Lm Active Device. Microstrip line 50Ω. Matching. θ. Network Feedback Element. RL. Figure 2-15 VTDRO design configuration. 2-2-1 Frequency Resonator Simulations. In this case, the Ku-band DRO design was achieved by the design procedure. The DRO configuration chosen is series feedback VTDRO (see figure 2-13(b)), An advantage of the series feedback design is the relative ease of coupling to a single line, compared to the parallel circuit’s requirement for coupling to two lines. The parameters of DR acquirement show as follows: 1.We can be extracted parameters of DR by the network analyzer. 2.The parameter is providing by the manufacturers.. From method 1, the DR is placed on top of the microstrip substrate in the metal. 28.

(38) enclosure and extracting the intrinsic parameters of the DR equivalent circuit. We can be extracted parameters of DR by the network analyzer. This is easily achieved with the use of software programs such as microwave offices. Figure 2-16 shows the measurement setup of DR.. Network Analyser Port 1 (S11). Port 2 (S22). DR. D d. Microstrip line DUT (include PCB with shield). Figure 2-16 DR parameter measurement setup. 29.

(39) In this case, we took parameters from Trans-Tech Inc. Figure 2-18 shows the module and simulation result. MLIN ID=TL1 W=1.2 mm L=4 mm. MLIN ID=TL2 W=1.2 mm L=4 mm. XFMR ID=XF2 N=1. 1. VIA ID=V2 D=0.7 mm H=0.508 mm T=0.01778 mm RHO=1. CAP ID=C2 C=1 pF. o. CAP ID=C1 C=1 pF. 4. 1 : n1 o. 3. 2. PRLC ID=RLC1 R=5000 Ohm L=0.00455 nH C=44 pF. o. XFMR MLIN ID=XF1 ID=TL14 W=1.2 mm N=1 L=4 mm. 4. 1 : n1 o. 3. VIA ID=V3 D=0.7 mm H=0.508 mm T=0.01778 mm RHO=1. 1. 2. MLIN ID=TL3 W=0.5 mm L=4 mm. PORT P=1 Z=50 Ohm. RES ID=R1 R=50 Ohm MSUB Er=3.38 H=0.508 mm T=0.01778 mm Rho=1 Tand=0.0025 ErNom=3.38 Name=SUB1. VIA ID=V1 D=0.7 mm H=0.508 mm T=0.01778 mm RHO=1. (a). 30.

(40) (b) Figure 2-18 DR module for software (a) equivalent circuit (b) simulation result. 2-2-2 Negative Resister Generator Simulations. The active device chosen is a NE54586 FET and the small-signal parameters are given for a bias of Vds = 2V at I ds = 10mA . In the drain of FET, the matching circuit was optimized at design frequency. Because of the structure is easy tuning, the feedback element chosen is a open-stub . It is connect with gate of FET. The open-stub is optimized so that the real part of the gate is as negative as possible. Figure 2-19 shows the one-port topology and simulation value.. 31.

(41) MLOC ID=TL5 W=2 mm L=0.75 mm. SUBCKT ID=S1 NET=Ne32584a. 2 MTEE ID=TL6 W1=1.2 mm W2=2 mm W3=0.25 mm 1. MLIN ID=TL12 PORT P=1 W=0.5 mm Z=50 Ohm L=1.06 mm. MLIN ID=TL7 W=0.25 mm L=1.2 mm 3. CAP ID=C1 C=1 pF. 2. 1. 1 3 2. MCROSS ID=TL2 W1=0.25 mm W2=1.2 mm W3=1.2 mm W4=1.2 mm. VIA ID=V1 D=0.7 mm H=0.508 mm T=0.01778 mm RHO=1. 3. MLOC ID=TL3 W=1.2 mm L=0 mm. MTEE ID=TL1 W1=1.2 mm W2=1.2 mm W3=1.2 mm. MLIN ID=TL4 W=1.2 mm L=4 mm. MLIN ID=TL8 W=0.25 mm L=4 mm. MLOC ID=TL10 W=1.2 mm L=3.696 mm. 2. 3. 1. MSUB Er=3.38 H=0.508 mm T=0.01778 mm Rho=1 Tand=0.0025 ErNom=3.38 Name=SUB2. 4. RES ID=R1 R=50 Ohm. MLIN ID=TL11 W=1.2 mm L=4 mm. PORT P=2 Z=50 Ohm. VIA ID=V2 D=0.7 mm H=0.508 mm T=0.01778 mm RHO=1. (a). 32.

(42) (b) Figure 2-19 The negative resister generator of NE54586 simulation circuit. 2-2-3 VTDRO Measurement. The final linear circuit is provided in figure 2-20. We can adjustment of the electrical length (θ) to compensate for the imaginary part of Z g (ω ) by the opposite value . The linear simulation will provide a good initial circuit layout before fine tuning . Figure 2-22 presents the layout of the DRO that was tested. Figure 2-23 and figure 2-24 presents the measured output power and phase noise performance that was achieved. Figure 2-25 presents the measured frequency tune range.. 33.

(43) Frequency Control Voltage Varactor Diode (MA46470_1056) Microstrip line. Termination Network. DR 50Ω. NE54586. Microstrip line. Matching. θ. Network Feedback Element. Figure 2-20 VTDRO block diagram. 34. RL.

(44) (a). (b) Figure 2-22 Layout and module of the VTDRO (a) layout (b) VTDRO module. 35.

(45) (a). (b) Figure 2-23 VTDRO Output measure (a) Output power spectrum (b) Output power flatness.. 36.

(46) Figure 2-24 VTDRO phase noise @ 100 KHz. 11.29 11.28 11.27 11.26 11.25 11.24 11.23 11.22 11.21 11.2 14. 12. 10. 8. 6. 4. 2. 數列1. 0. Output Frequency (GHz). VTDRO Tunning Range. Control Voltage (V). Figure 2-25 VTDRO frequency tune range 37.

(47) 2-3 Microwave Amplifier and Direction Coupler Design. The amplifier and direction coupler provide the amplitude gain and tape amplitude from main signal path. They can be performed using techniques given by McGraw-Hill[1]. In this case, the amplifier device is NBB-300. It is broadband InGaP/GaAs MMIC amplifier and provides 8dB gain from 11GHz to 12 GHz. We illustrate a microstrip directional coupler that involves two coupled microstrip lines. The design frequency is 11.25 GHz and coupling of -13 dB.. 2-4 PLL Controller Design The PLL controller schematic is shown as figure 2-35. The controller uses a serial interface from a computer to load data to the PLL chip. PLL chip of LMX1600L frequency operates up to 2.5GHz. The HMC363S8G is a low noise divide-by-8 static divider. This device operates from dc to 12GHz input frequency with a single +5.0V DC supply.. 38.

(48) +3.6V +5V 100nF. 1N4148. 100nF. +5DV. 100 100nF. 10pF. Crystal OSC 20MHz. 30pF. 8. 7. 6. 5. 4. 3. 2. 1. 14. 15. 16. LMX1600 9. 10. 11. 12. 13. 100nF Clock Data LE. 100 100nF. 100nF. 50. 100nF. HMC363S8G 1 2 3 4. 10pF +5V. 1nF. 8 7 6 5. From VCO (Dir. Coupler port3). 100nF +5V 100 +15V. 100nF. +3.6V 1k. 10nF. To VCO Control Voltage. 1k 6.8k 6.8k. +5V. 44nF. +5DV ACM4532 EMI Filter. Digital GND 10nF Analog GND. Figure 2-35 PLL controller schematic. 39.

(49) The loop filter integrates the pulsed output from the phase detector to produce a smoothed "DC" VCO control voltage. The loop performance can be set by varying the component values in the loop filter. The simplest is an RC low pass section (see figure 2-36 (a)). This will always include a second resistor in series with the capacitor. A further section of RC filtering can be added to produce a third order loop with improved sideband and noise performance(see figure 2-36 (b)). However it is more difficult to analyse higher order loops for stability and other parameters. If a simple RC filter is used, the VCO control voltage swing is limited to 0-5V in systems with a digital phase detector. For best phase noise performance it is necessary to use the full available control range of the varactor diode. To do this, a second OP amplifier can be configured as a DC amplifier to bring the output voltage to a higher figure (see figure 2-36 (c)). All components in the loop filter should be designed for low noise (eg. low noise OP amplifier and metal film resistors). The calculation of loop filter is shown in Appendix A.. 40.

(50) From phase detector. R1. From phase detector. To VCO. R2. R1. To VCO. R2. C1. C2. C2. (a). (b) +15V. Vref R1. Output. Input. R2 C2 C1. (c). Figure 2-36 Loop filter type (a) basic second order filter (b) passive third order filter (c) active third order filter. 2-5 KU-Band frequency control loop measurement. Figure 2-37 shows the KU-Band frequency control loop measurement setup diagram. This is the software that can be used to program a PLL via the parallel port of a computer. The software introduction is shown in Appendix B.. 41.

(51) VTDRO. Spectrum analyser RF AMP.. Dir. Coupler. f out Pout. Freq. Divider (÷8) Loop Filter f ref. PLL Circuit Data , Clock and LE Control lines Parallel Port. DUT. NoteBook. Figure 2-37 KU-Band frequency control loop measurement setup diagram. Figure 2-38 is the lock-in time measurement of frequency control loop. Figure2-39 shows the spurious of the reference frequency leakage. The spur due to reference leakage is about 66.8 dBc. Figure 2-40 is the phase noise measurement of Ku-band frequency control loop. The value of phase noise is 97.17 dBc/Hz at 100KHz offset.. 42.

(52) Figure 2-38 Lock-in time measurement of frequency control loop (11.225GHz jump to 11.275GHz). Figure 2-39 Spurious of the reference frequency leakage 43.

(53) Figure 2-40 phase noise measurement of Ku-band frequency control loop at 100KHz offset. 44.

(54) Chapter 3 RF Power Control Loop In this chapter, we will discussed theory and design of the RF power automatic gain control (AGC) loop. The block diagram is shown as figure 3-1.. RF VCA. RF AMP.. RF Signal Input. Dir. Coupler. f out Pout. RF AMP. DC Level Sh ift Low Pass Filter RF Detector. Integrator +. C. 12 bit D / A C onverter. RF Signal Set. A G C Set V olta ge. R. DC Amp.. Figure 3-1 RF Power Control Loop block diagram. The function of RF control loop discussed as follow: 1、The input signal passes through the VCA to produce the output level to be stabilized. The D/A converter was set by the computer and produces a reference DC voltage (AGC Set voltage). 2、The directional coupler tap the output power and feed it to RF detector and produces 45.

(55) a DC voltage proportional to the RF output power. 3、The DC amplifier provides a DC gain and produce detector’s output voltage. 4、The detector’s output voltage is compared against a AGC Set voltage to produce an error signal, which is then integrated to produce a control positive voltage. 5、The DC level shift circuit transforms the control positive voltage into negative voltage for the VCA and adjusts RF output power.. 3-1 Outline of Power Control Loop 3-1-1 Outline of AGC [5][6][19] Many attempts have been made to fully describe an AGC system in terms of control system theory, from pseudo linear approximations to multivariable systems. Each model has its advantages and disadvantages, first order models are easy to analyze and understand but sometimes the final results show a high degree of inaccuracy when they are compared with practical results. On the other hand, non-linear and multivariable systems show a relative high degree of accuracy but the theory and physical implementation of the system can become really tedious.. The basic block of automatic gain control loop show in figure 3-2. The input signal is amplified by a variable gain block (VGB) whose gain is controlled by a control. 46.

(56) voltage Vc . A cascade amplifier to generate and adequate level of Vo can amplify the output from the VGB. The power detector senses the output level, any undesired component is filtered out and the remaining signal is compared with a reference signal VR. The result of the comparison is used to generate the Vc and adjust the gain of the VGB.. Vi. Vo. Variable Gain Block (VGB). Vc Difference amplifier Low-pass Filter F(s). −. V2. Logarithmic amplifier. V1. Power Detector. + VR. Figure 3-2 basic block of automatic gain control loop. From figure 3-2, the AGC block diagram is essentially a negative feedback system and the system can be described in terms of its transfer function.. 47.

(57) The idealization of AGC transfers function show in figure 3-3. For low input level the AGC is disabled and the output is a linear function of the input, when the output reaches a threshold value, Vi1 , the AGC becomes operative and maintains a constant output level until it reaches a second threshold value ( Vi 2 ). At point of Vi 2 , the AGC becomes inoperative again; this is usually done in order to prevent stability problems at high levels of gain.. Vo. Real Curve ∆Vo. Ideal Curve. Vi1. Vi 2. Vi. Figure 3-3 the idealization of transfer function for an AGC system. Unfortunately, the AGC system is considered a nonlinear systems and it is very hard to find solutions for the nonlinear analysis.. 48.

(58) However, there is a linear model that describes the AGC loop function with a good degree of accuracy and are relatively easy to implement when the small signal transfer equations of the main blocks are known. The block diagram for this model is show in figure 3-2. The variable gain block has the following transfer function and it expression is by. P = K1e + aVc. (3-1). Vo = Vi K1e + aVc. (3-2). and. Where Vi and VO are the input and output level. K1 is a constant and a is a constant factor of the VGB.. The logarithmic amplifier gain can be defined as follow. V2 = ln V1 = ln K 2Vo. (3-3). Where K 2 represents the gain of the envelope detector.. 49.

(59) In order to simplify, we assume that the output of the envelope detector is always positive. The control voltage becomes:. Vc = F ( s )(VR − V2 ) = F ( s )(VR − ln K 2Vo ). (3-4). where F(s) represents the filter transfer function. By expending (3-2), the Vc can be written as:. aVc = ln Vo − ln K1Vi. (3-5). From (3-4) and (3-5), we get :. ln Vo [1 + aF ( s )] = ln Vi + aF ( s )VR + ln K1 − aF ( s )VR ln K 2. (3-6). Since we are only interested in the output-input relationship, let K1 and K 2 be equal to one. Thus, the above equation becomes:. 50.

(60) ln Vo [1 + aF ( s )] = ln Vi + aF ( s )VR. (3-7). If Vo and Vi are expressed in decibels, we can use the following equivalence. ln Vo = 2.3log Vo. ln Vo =. (3-8). 2.3 VodB = 0.115VodB 20. (3-9). Finally, the equation (3-7) that relates input and output can be rewritten as. VodB =. VidB 8.7 aF ( s )VR + 1 + aF ( s ) 1 + aF ( s ). (3-10). The equation (3-10) shows a linear relationship as long as input and output quantities are expressed in decibels and it is easy to see that the function of the system is determined by the filter F(s) and the a factor of the VGB. F(s) is usually a low pass filter, since the bandwidth of the loop must be limited to avoid stability problems and to ensure that the AGC does not respond to any amplitude modulation that could be present in the input signal. 51.

(61) In any control system, an important parameter is the steady-state error that is defined as : ess = lim e(t ) = lim sE ( s ) t →∞. (3-11). s →0. where E(s) is the error signal in the feedback path.. Applying the definition given above to the AGC loop we find that the position error constant is given by:. ess =. 1 1 + aF (0). (3-12). where F(0) is the DC gain of the F(s) block. a is the constant factor of the variable gain block .. Thus, in order to maintain the steady state error as small as possible the DC gain of the F(s) block must be as large as possible .The F(s) block that can be used in the loop is a first order low pass filter whose transfer function is defined as follows:. F ( s) =. K s +1 B. (3-13). 52.

(62) where K is the DC gain of the filter. B is the bandwidth.. Using this expression in the equation of the steady state error we find that:. ess =. 1 1 + aK. (3-14). The total DC output of the AGC loop is given by:. VoDC =. VIDC 8.7aKVR + 1 + aK 1 + aK. (3-15). It can be seen that if the gain loop K is much greater than 1, the output is almost equal to 8.7 VR and the steady state change in the input is greatly reduced. AGC loop that include a reference voltage inside the control loop are referred as delayed AGC.. Since we are interested in the change in the output voltage due to a change in the input voltage we can take the derivative of Vo with respect to Vi . From (3-1) and (3-2), the output voltage becomes: Vo = PVi. (3-16). therefore. 53.

(63) dVo d dP = ( PVi ) = P + Vi dVi dVi dVi From. (3-17). dP , we can be further developed applying the chain rule and using the dVi. equation for the control voltage, thus:. dP dP dVc dP dVc dVo dP dVo − F = = = ( ) dVi dVc dVi dVc dVo dVi dVc dVi Vo. (3-18). Therefore, the equation (3-17) can be rewritten as:. dVo F dP [1 + Vi ]= P dVi Vo dVc. (3-19). Alternatively dVo Vo 1 = dVi F dP [1 + ] P dVc Vi. (3-20). From (3-20), It is clear that the loop gain is a function of the input signal. That translates into a relative degree of non-linearity and complicates the analysis of the transient response of the system. However, it is possible to numerically evaluate the characteristic parameters of the loop if the P (Vc ) function is know and a set of initial conditions is taken as a starting point.. 54.

(64) 3-1-2 Outline of VCA. In the microwave circuit, attenuators are useful in reducing the power level of RF signals by a specific amount. The basic structure is shown as figure 3-4.. Ra. RFin. Rb. Rb. (a). RFin. R1. R1. RFout. R2. (b) Figure 3-4 Basic structure of attenuator (a)π type (b) T type. In the application, the fixed attenuators and variable attenuators are two general configurations. The fixed attenuators allow one or more discrete levels of attenuation. The variable attenuators allow a specific value of attenuation to be selected from an analog control voltage.. 55.

(65) The PIN diode and the FET are commonly used in variable attenuators. In this case, we discuss the FET voltage variable attenuator of the T type. Figure 3-5 shows the T type resistance attenuator and equivalent circuit of FET.. R1. RFin. R1. RFout. R2. (a). V1. RFin. D. V2. RFout. S. S. D S. (b) Figure 3-5 The T type resistance attenuator (a) resistance attenuator (b) equivalent circuit of FET. In generally, the attenuator of FET requires two bias voltages, one applied to the series FETs ( V1 ) and one applied to the shunt FETs ( V2 ). As voltages V1 and V2 are. 56.

(66) varied between Vc1 and Vc2 the FETs “on” resistance changes. At Vc1 control, the FET is turned fully “on” resulting in a low resistance state. At Vc2 control, the FET is in a fully “pinchedoff” state resulting in a high resistance state. When the control voltages are between Vc1 and Vc2, the FETs are neither fully “on” nor fully “off” but are in a variable resistance state that is a function of control voltage. The control voltage vs. attenuation curve is shown in Figure 3-6 and is typical for the AT006N3-01 of Alpha Industries, Inc. We can find the curves are not a linear function. This occurs because the FET’s resistance is a non-linear relationship with respect to control voltage and increases very quickly as the control voltage approaches “pinch-off”.. Figure 3-6 Typical for the AT006N3-01 of Alpha Industries, Inc. 57.

(67) 3-2 Power Control Loop Design 3-2-1 Ku-band Power Detector Design Figure 3-7 shows the basic construction of the RF detector[1]. The matching network is necessary so the maximum power can reach the diode and the conversion from RF to DC can take place efficiently.. RF Signal Input. MA4E2054 Schottky Diode. Matching Network 10K. DC Output. 100nF. Figure 3-7 Basic construction of the RF detector The RF power from amplifier and feeds it to a Schottky diode detector. It produces a DC voltage proportional to the output, which is then fed back to the AGC controller. The linear equivalent circuit can provide insight into the performance of the Schottky diode (see figure 3-8). Lp and Cp are package parasitics. A three eelement equivalent circuit can represent the diode chip itself, including Rs (parasitic series resistance), Cj (parasitic junction capacitance) and Rj (the junction resistance). Figure 3-10 shows the RF imputer power versus output dc voltage.. 58.

(68) 11 ohm. 1000K. 0.1pF. Diode linear equivalent circuit. 0.13pF. 0.13pF. Pin2 0.7nH. 0.05pF 0.65nH. Pin3. 0.13pF. 0.65nH. 0.13pF. 0.05pF Pin1 0.13pF. 0.13pF. Diode with Package M odel. Figure 3-8 equivalent circuit of Schottky diode. RF Detector Performance 1.2. Detect Voltage (V). 1 0.8 0.6. 數列1. 0.4 0.2 0 -11. -9. -7. -5. -3. -1. 1. 3. Input Power (dBm). Figure 3-10 RF imputer power versus output dc voltage 59.

(69) 3-2-2 Ku-band VCA Design The GaAs MESFETs at zero drain bias have been used as variable resistors to construct a new module of T-type attenuator. The S parameter of new module must reconstruction. In this case, the NE32584c can provided Rds by the Vgs . The test setup is shown figure 3-11.. Network Analyser Port 1 (S11). Port 2 (S22) VC1 100pF. L1. D. S. S. 100K. −0.5V. D S. R 0.1uF. L2. C. DUT L1 , L2 =>1/4λTransmission Line @11.25GHz. Figure 3-11 T-type attenuator module of NE32584c. 60.

(70) In second step, input and output the simulation software designed match circuits. The final circuit and simulation result are shown as figure 3-12 and figure 3-13. It can provide 18 dB dynamic range by the VC1 and 3 dB insertion loss. The network analyzer and spectrum analyzer measured the characteristic of VCA. The measurement data are shown as figure 3-14 and figure 3-15.. VC1. 15P f. C. C. C. C. 15Pf. 1 λ 4 = 0 .2 m m. L = W. 1 λ 4 = 0 .2 m m. L = W. RFin VC 2. D. S. S. D. M icrostrip Line 1 λ 4 = 0 .2 m m. L =. C. W. 1 λ 4 = 0 .2 m m. L =. 1 L = λ 4 W = 0 .2 m m. S. Figure 3-12 VCA final circuit. 61. W. RFout. D. F ET :. NE 32584C. VC1 = 0 : − 2V VC 2 = − 0.5V.

(71) Spectrum analyser. SG. Signal input. VCA. Signal outputput. SG output power = 0 dBm. Control Voltage (a). (b). (c) Figure 3-14 VCA measurement (a) measurement setup (b)insertion loss measure(c) attenuation performance at 0V control voltage 62.

(72) VCA Attenuation Performance @ 11.25GHz. Attenuation Power (dBm). 0 -5 -10 -15 -20. -0 .95. -0 .8. -0 .6 5. -0 .5. 5 -0 .42. -0 .35. -0 .27 5. -0 .15. 0. -25. VCA Control Voltage (V). Figure 3-15 VCA attenuation performance. 3-2-3 AGC Loop Design The AGC loop controller block diagram and schematic are shown figure 3-16. The LT1112 is dual op amps and achieve DC amplifier, Integrator and DC level shift circuits. The LTC1448 is a dual rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC). It includes rail-to-rail output buffer amplifiers and an easy-to-use 3-wire serial interface.. 63.

(73) To VCA DC Level Sh ift Low Pass Filter Integrator +. C. Form RF Detector. 12 bit D / A C onverter. RF Signal Set. A G C Set V o lta g e. R. DC Amp.. (a). 10nF. Form RF Detector. 100nF 56k. To VCA Control Voltage. 1u. 10k. 10k. 100. MA4E2054 Schottky Diode. +5V Digital GND. 10k. LT1112. 20k. LT1112. 10k. LT1112. 1k 1uF. 2.5V. Analog GND 10nF. 0.22uF 10nF. DA_Clck DA_Data. LTC1448. DA_CS. 1 8 2 7 3 D/A 6 4 5. +5DV. 7.5k. 15k 0.1uF 1uF. 1k 1uF. 10k. 10k. LT1112. +5VD. 2.5V. OP AMP DC power supplely : +/ 5V. 100Hz active LPF. (b) Figure 3-16 AGC loop structure (a) block diagram (b) schematic. 64.

(74) 3-3 Power Control Loop Measurements Finally, we should measure the power control loop performance. The test setup is shown as figure 3-17. VTDRO. RF VCA. RF AMP .. RF AMP .. D ir . Coupler. D ir . Coupler. f out. Pout. Freq . Divider. RF AMP .. ( ÷ 8). D C Level Sh ift. Loop Filter. Low Pass Filter. f ref PLL Circuit. RF Detector. Integrator. +. C. 1 2 b it D / A. PLL Control Lines. C o n ve rter. RF Signal Set. A G C S et. R. D C Amp .. LabVIEW. Parallel Port. (a). (b) Figure 3-17 Power control loop measurement setup (a) block diagram (b) measurement etup. 65.

(75) The dynamic range of control loop measurement is shown figure 3-18. The range adjust from 4 dB to -15 dB and the flatness of output measurement is shown figure 3-19.. (a). (b) Figure 3-18 Dynamic range measurement. 66.

(76) Figure 3-19 synthesizer output flatness The synthesizer phase noise measure is shown figure 3-20. The power control loop not degrades phase noise performance.. (a) Figure 3-20 synthesizer phase noise at 100 KHz offset 67.

(77) Figure 3-19 presents the measured frequency tune range. The output power of synthesizer was kept by the power control loop and adjustment output power. The table 3-1 shows the synthesizer specifications.. Frequency Range. 11.23GHz to 11.85GHz. Output Power. +4 dBm to –15dBm. Phase noise DC power supply. 97.83 dBc @ 100KHz +15V ; -5V. Table 3-1 The synthesizer specifications.. 68.

(78) Chapter 4 CMOS LC Oscillator and Frequency Divider Design. In this chapter, we present a method for design of CMOS Voltage controlled oscillator (VCO) and frequency divider. They are fully integrated in bulk CMOS technology operating at 5GHz. Figure 4-1 is shown the block diagram.. VCO Vct. f out. ( a) f in 2 fin. Div 2. Div 2. f out =. f in 4. (b). Figure 4-1 CMOS simulation block diagram (a) CMOS VCO simulation block diagram (b) frequency divider simulation block diagram. 69.

(79) 4-1 CMOS Voltage controlled oscillator (VCO) Design For fully integrated CMOS oscillator, two common approaches are ring oscillators and LC oscillators (see figure 4-2). The advantage of ring oscillators is without any passive element such as inductors and capacitors. Because of there is no filtering action shaping the phase noise of the output signal, the ring oscillators generally show a very poor phase noise performance compared to LC oscillators [32].. Vin. Vout. + +. (a) VDD. VDD. Vout1. Vout 2. NMOS. NMOS. Ibias. (b) Figure 4-2 CMOS common approaches oscillator (a)Three-stage ring oscillators (b) LC oscillators. A LC oscillator consists of a parallel LC tank and active circuit that compensated for the losses in the passive elements. The LC tank resonates at the 70.

(80) frequency 1 LC. ω0 =. (4-1). In the RF CMOS design, the lack of high-quality on-chip inductors is one of the major drawbacks. The most common topology of on-chip inductors is the square spiral and circular spiral inductors. In the VCO, the oscillators frequency must be tunable by the varactor element .The capacitance of a varactor can be controlled between C1 and C2 by a control voltage. For ideal VCO, it is a linear function of the control voltage .The function and block of VCO are shown in figure 4-3.. VCO Vct. ωout. (a). ω out ω1 ω2. ω out = ω 0 + KVCOVct. V1. Vct. V2 (b). Figure 4-3 VCO function and block diagram (a) VCO diagram (b) VCO function. 71.

(81) 4-1-1 Topology of an NMOS-PMOS LC oscillator. In this case, the conventions NMOS-PMOS cross-coupled oscillator (see figure 4-4) is used as the design for several reasons. The differential operation mitigates undesirable common-mode effects such as DC supply noise and extrinsic substrate. For the same bias circuit, the oscillation amplitude of this configuration is a factor of two large than that of the NMOS-only structure. The rise and fall time symmetry of oscillation waveform reduces the up-conversion of the transistor noise.. VDD. Ibias. PMOS. PMOS. L. Vout1 Cload 1. Varactor. NMOS. Vout 2 Cload 2. NMOS. Figure 4-4 NMOS-PMOS cross-coupled oscillator schematic. 72.

(82) The small-signal equivalent model of NMOS-PMOS cross-coupled oscillator is shown in figure 4-5. The equivalent capacitance of a NMOS-pair and a PMOS-pair between the two nodes are thus [33]:. AC ground CL. CL. Spiral Inductor. Rp. Rp. Ls. Rs. Rs. Ls. Cv. Rv. Rv. Cv. g on + g op. Varactor. g on + g op. −( g mn + g mp ) −( g mn + g mp ) CNMOS + CPMOS CNMOS + CPMOS. Cload 1. NMOS+PMOS Pair. Cload 2. Figure 4-5 Small-signal equivalent circuit of the VCO core. The small-signal transconductance of a single NFET and PFET were defined g mn and g mp . In the NMOS-PMOS LC VCO, the output signal is the differential voltage. Vout1 − Vout 2 . From figure 4-4, the Vtan k = Vout1 − Vout 2 . The tank voltage can be expressed as [32][33]:. 73.

(83) Vtan k. I bias ⎧ ⎪ I bias Rtan k = g tan k =⎨ ⎪V ⎩ lim it. for current limited regime. (4-2). for voltage limited regime. The design process can be summed up in following steps: 1、 Set g mn = g mp to improved the. 1. f3. corner of phase noise.. 2、The tail current is set depending on the power consumption limit .. 3、 The conductance is calculated keeping in mind the voltage swing specification Vout ≤ I bias Rtan k. (4-3). 4、 To ensure start-up the gm of cross-couple devices are set 4 time more than g tan k gm ≥4 g tan k. (4-4). 5 、The maximum and minimum capacitance value needed for the required tuning range of frequency is calculated as. ω min =. 1 Ltan k Ctotal ,max. ω max =. 1 Ltan k Ctotal ,min. 6、 The phase noise in. 1. f2. (4-5). region can be predicted using Leeson’s equation [][]:. ⎧⎪ ⎡⎛ F ⎞ 2 ⎤ ⎛ F ⎞ ⎛ FkT ⎞ ⎫⎪ L(∆f ) = 10 log ⎨0.5 ⎢⎜ 0 ⎟ + 1⎥ ⎜ c + 1⎟ ⎜ ⎟⎬ ⎥⎦ ⎝ ∆f ⎠ ⎝ P0 ⎠ ⎪⎭ ⎪⎩ ⎣⎢⎝ 2Q∆f ⎠. where 74. dBc / Hz. (4-6).

(84) F0 =Oscillator frequency. Q =Loaded resonator quality ∆f =Frequency offset with respect to the carrier Fc =Flicker noise cutoff frequency of the transistor amplifier. F =Noise factor of the transistor amplifier k =Boltzmann’s constant. T =Temperature in Kelvin P0 =Output power of the oscillator. 4-1-2 Simulation result of a 5GHz NMOS-PMOS LC VCO In this case, the Hspice and Laker software achieved the 5GHz NMOS-PMOS LC VCO design. Figure 4-6 presents the schematic of the VCO. The post simulation result is show in Figure 4-7. Figure 4-8 and table 4-1 are shown the VCO layout and VCO specifications.. 75.

(85) VDD. VDD. MP1. MP2. R VDD. VDD MP4. MP3. Vout1 VC2. Cload 1. Vout 2. L VC1. C1. C2. Cload 2. Vct. MN1. MN2. (a). Device L/W Device. MP1. MP2. MP3,MP4. MN1,MN2. 0.24u / 50u 0.24u / 140u 0.24u / 120u 0.24u / 40u L. Cload 1 , Cload 2. VC1, VC2. 2nH. 0.4pF. 0.5pF. C1,C2. R. NC. 2.7K. (b). Figure 4-6 VCO schematic (a) schematic (b) CMOS size. 76.

(86) (a). (c). 77.

(87) (d) Figure 4-7 CMOS VCO simulation result (a) VCO start up (b) phase noise (c) VCO tuning range. Item Voltage Supply. 2.5V. Frequency Tuning range. 5.3GHz to 5.7GHz. Output Load. 0.4pF. Output Swing Amplitude. 1.3 Vp-p. Power Consumption. < 20 mW. Table 4-1 VCO specification. 78.

(88) 4-2 Frequency divider design. In the 5GHz frequency synthesizer, the frequency divider is important circuit . It is to be used in a phase locked loop to step down the frequency of VCO. The circuit most difficult to design is the first stage of diver, which should operated at 5GHz .In the case, the source-coupled latch has a reduced output swing that facilitates high speed. The block diagram of the frequency divider is shown in figure 4-1(b). This divider implemented a cascade of 2 divider by 2 circuits.. The conventions schematic of source-coupled latch is shown in figure 4-9. It consists of a differential amplifier (M3, M4) and a regenerator (M5, M6) . Two FETs are placed between the current source and differential/regenerator, they are acting switches controlled by the CK and CK signals. When the M2 is turn on by the clock activated, the function of differential amplifier is passing the input signal to the outputs. When the M1 is turn on by the clockbar activated, the regenerator lactching the outputs Q and. Q .. 79.

(89) VDD. VDD. Vbias PMOS. Q. Q M3. M5. D. M6. NMOS. NMOS. M1. M4. D. NMOS. CK Ibias. M2. NMOS. CK Ibias. Figure 5-9 conventions schematic of source-coupled latch. The two latches achieved the unit stage of divider. Two latches can be connected as shown in figure 4-10. The output of one latch is fed to the input of the second, whose output is inverted and tied back to the inputs of the first latch. This results in an output signal, taken from the outputs of the second latch, that has half the frequency of the clock signal.. 80.

(90) Master. Slave. D D. CK. CK. Q. D. Q. D. CK. CK. Q. f out. Q. f out f out =. CK. CK 2. CK. Figure 4-10 unit stage of divider. The design considerations of the basic latch are as follows: 1、 The FETs are biasing in the active region , they will allow for fast operation of the FETs. The proper overdrive voltages and sizeing of the FETs can cerated by the proper biasing of the gate voltage. 2、 The regenerator FETs have a large enough gm can overcome the pull up resistors . This is keep the outputs Q and Q latched to VDD and id*R.. 81.

(91) 4-2-1 Simulation result of a 5GHz frequency divider In this case, the 5GHz frequency divider design was achieved by the Hspice and Laker software. Figure 4-11 presents the block diagram of the divider and the schematic of divider is shown figure 4-12. The post simulation result as show in Figure 4-13. Figure 4-14 and table 4-2 are shown the divider layout and VCO specifications.. f in 2. fin CK. CK. C1. CK1. CK1. Vbias2. CK 2. Divider 1. C2. R2. Q1. Q1. Divider 2 Q1. CK 2. R1. Vbias1. Figure 4-11 Frequency divider block diagram. 82. Q1. f in 4.

(92) VDD. VDD. R3. R3. Q1. Q1 MN5. C1. CK1. MN9. MN10. MN6. CK MN1. VDD. MP1. CK1. R1. MN13 MN2. CK1. C2. CK1. CK. VDD VDD MP2. VDD. R2 R3. MN14. MN7. R3. MN11. MN12. MN3. Q1. CK1. Q1. MN4. CK1. (a) 83. MN8.

(93) VDD. VDD. R3. R3. Q2. Q2 MN19. MN23. MN24. MN20. MN15. CK 2. MN16. CK 2 MN27. Vbias. VDD. VDD. R3. R3 VDD. MN21 MN25. MP3. MN26. MN22. Vbias. MN29. MN17. CK 2. CK 2 MN18. CK 2 Q. CK 2. 2. MN28. Q2. Vbias. (b) 84.

(94) Device MP1,MP2 L/W. 0.24u / 35u. MN1,MN3. MN2,MN4. MN5,MN6. MN7,MN8 MN9,MN10. 0.24u / 40u. 0.24u / 80u. 0.24u / 80u. 0.24u / 80u. 0.24u / 40u. Device MN11,MN12 MN13,MN14 MN15,MN16 MN17,MN18 MN19,MN20 MN21,MN22 L/W. 0.24u / 40u. 0.24u / 10u. 0.24u / 40u. Device MN23,MN24 MN25,MN26 MN27,MN28 L/W. 0.24u / 40u. Device. C1,C2. R1,R2. R3. L/W. 30u / 30u. 1.6k. 0.2k. 0.24u / 40u. 0.24u / 40u. MN29. MP3. 0.24u / 40u 0.24u / 160u 0.24u / 10u. 0.24u / 40u. 0.24u / 35u. (c) Figure 4-12 Frequency divider schematic (a) divider1 schematic (b) divider2 schematic (c)CMOS size. 85.

(95) Figure 5-13 CMOS frequency divider simulation result Figure 4-13 the post simulation result Item Voltage Supply. 2.5V. Input Frequency range. 5.3GHz to 5.7GHz. Output Frequency range. 1.325Ghz to 1.425GHz. Input Swing Amplitude. 0.6 Vp-p. Output Swing Amplitude. 1Vp-p. Power Consumption. < 80 mW. Table 4-2 divider specification 86.

(96) Chapter 5 Conclusion. In this thesis, the basic principles of phase-locked loop, automatic gain control loop and CMOS integrated circuit are explored. Special attentions have been directed to the performance of power level control and frequency control.. In the Ku-band frequency synthesizer, this new structure is realized by inserting AGC loop behind the phase-locked loop. The power level and frequency can be controlled. The frequency change and output power level of synthesizer will be compensated or set by the computer. In the thesis, we show the measurement data of AGC loop function. It can reduce VTDRO output power flatness from +3dB to +0.6dB and the output power of synthesizer can be set from +4dBm to –15dBm. Unfortunately, we found some problem of synthesizer. The output power flatness had varied +0.7dB by the AGC loop steady-state error. That is from device nonlinear characteristic. Other problem of synthesizer, the divider of PLL controller degrades phase noise at 10KHz offset. We will cope with problems in the future. For application, this synthesizer connects with mixer or frequency multiplier generator and adjusting the synthesizer output power and frequency for the optimum performance.. 87.

(97) In the CMOS integrated circuit, the conventional analysis of mentioned briefly. The analysis method gives designers a clear insight so the high performance voltage-controlled oscillator and frequency divider can be obtained. The circuit design process, simulation and layout are shown in the thesis.. 88.

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