Power Control Loop Measurements

Finally, we should measure the power control loop performance. The test setup is shown as figure 3-17.

.

DC Level Sh ift Low Pass Filter

Figure 3-17 Power control loop measurement setup (a) block diagram (b) measurement etup

The dynamic range of control loop measurement is shown figure 3-18. The range adjust from 4 dB to -15 dB and the flatness of output measurement is shown figure 3-19.

(a)

(b)

Figure 3-18 Dynamic range measurement

Figure 3-19 synthesizer output flatness

The synthesizer phase noise measure is shown figure 3-20. The power control loop not degrades phase noise performance.

(a)

Figure 3-20 synthesizer phase noise at 100 KHz offset

Figure 3-19 presents the measured frequency tune range. The output power of synthesizer was kept by the power control loop and adjustment output power. The table 3-1 shows the synthesizer specifications.

Frequency Range 11.23GHz to 11.85GHz Output Power +4 dBm to –15dBm Phase noise 97.83 dBc @ 100KHz DC power supply +15V ; -5V

Table 3-1 The synthesizer specifications.

Chapter 4

CMOS LC Oscillator and Frequency Divider Design

In this chapter, we present a method for design of CMOS Voltage controlled oscillator (VCO) and frequency divider. They are fully integrated in bulk CMOS technology operating at 5GHz. Figure 4-1 is shown the block diagram.

VCO V ct

2

Div Div 2

f in

2 f in

4

in out

f = f ( ) a

( ) b

f out

Figure 4-1 CMOS simulation block diagram (a) CMOS VCO simulation block diagram (b) frequency divider simulation block diagram

4-1 CMOS Voltage controlled oscillator (VCO) Design

For fully integrated CMOS oscillator, two common approaches are ring oscillators and LC oscillators (see figure 4-2). The advantage of ring oscillators is without any passive element such as inductors and capacitors. Because of there is no filtering action shaping the phase noise of the output signal, the ring oscillators generally show a very poor phase noise performance compared to LC oscillators [32].

VDD

NMOS NMOS

1

V out V _{out 2}

VDD

Ibias

( ) b ( ) a +

+

V in V _out

Figure 4-2 CMOS common approaches oscillator (a)Three-stage ring oscillators (b) LC oscillators

A LC oscillator consists of a parallel LC tank and active circuit that compensated for the losses in the passive elements. The LC tank resonates at the

frequency

0

1

ω

=

LC

(4-1) In the RF CMOS design, the lack of high-quality on-chip inductors is one of the major drawbacks. The most common topology of on-chip inductors is the square spiral and circular spiral inductors.

In the VCO, the oscillators frequency must be tunable by the varactor element .The capacitance of a varactor can be controlled between C1 and C2 by a control voltage. For ideal VCO, it is a linear function of the control voltage .The function and block of VCO are shown in figure 4-3.

VCO

ω

out

V

ct

ω

out

V

ct

V

2

V

1

ω

2

ω

1

0

out

K

VCO

V

ct

ω = ω + ( ) a

( ) b

Figure 4-3 VCO function and block diagram (a) VCO diagram (b) VCO function

4-1-1 Topology of an NMOS-PMOS LC oscillator

In this case, the conventions NMOS-PMOS cross-coupled oscillator (see figure 4-4) is used as the design for several reasons. The differential operation mitigates undesirable common-mode effects such as DC supply noise and extrinsic substrate. For the same bias circuit, the oscillation amplitude of this configuration is a factor of two large than that of the NMOS-only structure. The rise and fall time symmetry of oscillation waveform reduces the up-conversion of the transistor noise.

VDD

Ibias

PMOS PMOS

L

Varactor

NMOS NMOS

1

V out V _out

₂

2

C load

1

C load

Figure 4-4 NMOS-PMOS cross-coupled oscillator schematic

The small-signal equivalent model of NMOS-PMOS cross-coupled oscillator is shown in figure 4-5. The equivalent capacitance of a NMOS-pair and a PMOS-pair between the two nodes are thus

[33]

:

Figure 4-5 Small-signal equivalent circuit of the VCO core

The small-signal transconductance of a single NFET and PFET were defined and . In the NMOS-PMOS LC VCO, the output signal is the differential voltage

. From figure 4-4, the

tan tan tan

lim

for current limited regime for voltage limited regime

bias

The design process can be summed up in following steps:

1、 Set

g _mn

=

g _mp

to improved the 1 3

f

corner of phase noise.

2、The tail current is set depending on the power consumption limit .

3、 The conductance is calculated keeping in mind the voltage swing specification

tan

out bias k

V

≤

I R

(4-3) 4、 To ensure start-up the gm of cross-couple devices are set 4 time more than

g

_{tan k}

tan

4

k

gm

g

≥ (4-4) 5 、The maximum and minimum capacitance value needed for the required tuning range

of frequency is calculated as

min

f

region can be predicted using Leeson’s equation [][]:

F =Oscillator frequency

0

Q =Loaded resonator quality

∆ =Frequency offset with respect to the carrier

f

F =Flicker noise cutoff frequency of the transistor amplifier c

F

T

=Noise factor of the transistor amplifier

k

=Boltzmann’s constant

=Temperature in Kelvin

P =Output power of the oscillator

0

4-1-2 Simulation result of a 5GHz NMOS-PMOS LC VCO

In this case, the Hspice and Laker software achieved the 5GHz NMOS-PMOS LC VCO design. Figure 4-6 presents the schematic of the VCO. The post simulation result is show in Figure 4-7. Figure 4-8 and table 4-1 are shown the VCO layout and VCO specifications.

L VC1

MN1 MN2

1

V out V _out

₂

2

C load

1

C load

VDD VDD

R

VC2

C1 C2

MP1 MP2

MP3 MP4

VDD VDD

Vct

(a)

Device MP1 MP2 MP3,MP4 MN1,MN2 C1,C2 R

L/W 0.24u / 50u 0.24u / 140u 0.24u / 120u 0.24u / 40u NC 2.7K

Device L

C load

1,

C _load

₂ VC1, VC2

2nH 0.4pF 0.5pF

(b)

Figure 4-6 VCO schematic (a) schematic (b) CMOS size

(a)

(c)

(d)

Figure 4-7 CMOS VCO simulation result (a) VCO start up (b) phase noise (c) VCO tuning range

Item

Voltage Supply 2.5V

Frequency Tuning range 5.3GHz to 5.7GHz

Output Load 0.4pF

Output Swing Amplitude 1.3 V

_p-p

Power Consumption < 20 mW

Table 4-1 VCO specification

4-2 Frequency divider design

In the 5GHz frequency synthesizer, the frequency divider is important circuit . It is to be used in a phase locked loop to step down the frequency of VCO. The circuit most difficult to design is the first stage of diver, which should operated at 5GHz .In the case, the source-coupled latch has a reduced output swing that facilitates high speed.

The block diagram of the frequency divider is shown in figure 4-1(b). This divider implemented a cascade of 2 divider by 2 circuits.

The conventions schematic of source-coupled latch is shown in figure 4-9. It consists of a differential amplifier (M3, M4) and a regenerator (M5, M6) . Two FETs are placed between the current source and differential/regenerator, they are acting switches controlled by the

CK

and

CK

signals. When the M2 is turn on by the clock activated, the function of differential amplifier is passing the input signal to the outputs. When the M1 is turn on by the clockbar activated, the regenerator lactching the outputs

Q

and

Q .

NMOS NMOS

Ibias

Ibias

VDD VDD

NMOS

NMOS PMOS

Vbias

D D

Q Q

CK CK

M1

M2

M5 M6

M3 M4

Figure 5-9 conventions schematic of source-coupled latch

The two latches achieved the unit stage of divider. Two latches can be connected as shown in figure 4-10. The output of one latch is fed to the input of the second, whose output is inverted and tied back to the inputs of the first latch. This results in an output signal, taken from the outputs of the second latch, that has half the frequency of the clock signal.

CK CK

Q

Q D

D CK CK

Q

Q D

D

Master Slave

CK CK

f

out

f

out

out

2 f = CK

Figure 4-10 unit stage of divider

The design considerations of the basic latch are as follows:

1、 The FETs are biasing in the active region , they will allow for fast operation of the FETs. The proper overdrive voltages and sizeing of the FETs can cerated by the proper biasing of the gate voltage.

2、 The regenerator FETs have a large enough gm can overcome the pull up resistors . This is keep the outputs

Q

and

Q latched to VDD and id*R.

4-2-1 Simulation result of a 5GHz frequency divider

In this case, the 5GHz frequency divider design was achieved by the Hspice and Laker software. Figure 4-11 presents the block diagram of the divider and the schematic of divider is shown figure 4-12. The post simulation result as show in Figure 4-13.

Figure 4-14 and table 4-2 are shown the divider layout and VCO specifications.

CK

1

CK

1

Q

₁

Q

1

Divider 1

C1

C2

R2 R1

CK CK f

in

2 f

in

4 f

in

Vbias2 Vbias1

CK

2

CK

2

Q

₁

Q

1

Divider 2

Figure 4-11 Frequency divider block diagram

VDD

MN1

MN2

MN5 MN9 MN10 MN6

VDD

R3

VDD

MN3

MN4

MN7 MN11 MN12 MN8

VDD

VDD

MN15

MN16

MN19 MN23 MN24 MN20

VDD

Device MP1,MP2 MN1,MN3 MN2,MN4 MN5,MN6 MN7,MN8 MN9,MN10 L/W 0.24u / 35u 0.24u / 40u 0.24u / 80u 0.24u / 80u 0.24u / 80u 0.24u / 40u Device MN11,MN12 MN13,MN14 MN15,MN16 MN17,MN18 MN19,MN20 MN21,MN22

L/W 0.24u / 40u 0.24u / 10u 0.24u / 40u 0.24u / 40u 0.24u / 40u 0.24u / 40u Device MN23,MN24 MN25,MN26 MN27,MN28 MN29 MP3

L/W 0.24u / 40u 0.24u / 40u 0.24u / 160u 0.24u / 10u 0.24u / 35u

Device C1,C2 R1,R2 R3

L/W 30u / 30u 1.6k 0.2k

(c)

Figure 4-12 Frequency divider schematic (a) divider1 schematic (b) divider2 schematic (c)CMOS size

Figure 5-13 CMOS frequency divider simulation result Figure 4-13 the post simulation result

Item

Voltage Supply 2.5V

Input Frequency range 5.3GHz to 5.7GHz Output Frequency range 1.325Ghz to 1.425GHz

Input Swing Amplitude 0.6 V

p-p

Output Swing Amplitude 1V

_p-p

Power Consumption < 80 mW

Table 4-2 divider specification

Chapter 5 Conclusion

In this thesis, the basic principles of phase-locked loop, automatic gain control loop and CMOS integrated circuit are explored. Special attentions have been directed to the performance of power level control and frequency control.

In the Ku-band frequency synthesizer, this new structure is realized by inserting AGC loop behind the phase-locked loop. The power level and frequency can be controlled. The frequency change and output power level of synthesizer will be compensated or set by the computer. In the thesis, we show the measurement data of AGC loop function. It can reduce VTDRO output power flatness from +3dB to +0.6dB and the output power of synthesizer can be set from +4dBm to –15dBm. Unfortunately, we found some problem of synthesizer. The output power flatness had varied +0.7dB by the AGC loop steady-state error. That is from device nonlinear characteristic. Other problem of synthesizer, the divider of PLL controller degrades phase noise at 10KHz offset. We will cope with problems in the future. For application, this synthesizer connects with mixer or frequency multiplier generator and adjusting the synthesizer output power and frequency for the optimum performance.

In the CMOS integrated circuit, the conventional analysis of mentioned briefly.

The analysis method gives designers a clear insight so the high performance voltage-controlled oscillator and frequency divider can be obtained. The circuit design process, simulation and layout are shown in the thesis.

Reference

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nd

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2002.

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IEEE 1993.

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Hochschule Zürich , 2002.

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Jason R. Anderson “Design of a Low-Voltage 5 to 6 GHz Voltage-Controlled Oscillator for 802.11 Applications “ Plexus Technology Group , 2001.

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Appendix A

In this chapter, we will discuss the design and analysis of active loop filter. There are also op-amp based loop filter topologies as shown in the figure A-1.

R2

From (2-15), we can find the relationships of Phase margin, Damping factor and Natural frequency. The table A-1 is show the relationships.

Phase margin , ψ Phase margin ,

ξ

Natural frequency ,

ω _n

The term of loop filter shown in as follows:

(1)

f _Range

– Frequency range of synthesizer.

(1)

f _step

– Maximum frequency change during a step or hop, from one frequency to

another.

(3)

f _CH

– Channel spacing.

(2)

t – The desired time for the carrier to step to a new frequency. _s

(3)

f – The frequency of the carrier, within the desired time (ts), after a step or _a

1 2

10

C

=

C

(A-4)

3 2

R

=

R

(A-5)

2

3 10

C

=

C

(A-6)

2 ( 1 4 2 f n

Loop Bandwidth

π ζ )

+ ζ

=

(A-7)

Appendix B

In this chapter, we will discuss PLL and D/A converter code generator. This program is designed to run LMX1600 and LTC1448. The code generator is base on LabVIEW. The LMX1600 is integrated dual frequency PLL and the IF band was disabled by program code. The LMX1600 data registersand a sample setting is shown as Figure B-1. The R counter determines the channel bans width. The N counter determined the output frequency. Figure B-2 shows the LMX1600 registers structure. In the table B-1, for each register the MSB and is loaded first.

For the LTC1448, The data is loaded as one 24-bit word where the first 12 bits are for DAC A channel and the second 12 are for DAC B channel. For each register the MSB and is loaded first . The data structure is shown as figure B-3.

The series data was generator by the LabVIEW and program signals from the parallel port of the computer.When the load command is used, all data in all registers is sent . The LabVIEW control plane and program process are shown as figure B-4 and figure B-5. Figure B-6 show the time chart.

Ref.

20MHz

R Counter R=32

Prescaler Divide-by-16

VTDRO 11.22GHz to 11.28GHz Divide-by-8

N Counter N= 2244 to 2256

Charge Pump

Loop Filter Phase

Detector

LMX1600

Figure B-1 LMX1600 data registers

Figure B-2 LMX1600 data registers structure

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DAC A Input DAC B Input

MSB LSB

Figure B-3 LTC1448 data registers structure

Figure B-4 LabVIEW control plane

Figure B-5 LabVIEW program process

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

2 3 4 5 6

CLOCK

PLL DATA(LMX2330 DATA) PLL LE(LMX2330 LE) D/A DATA (TLC1448 DATA) D/A LE (TLC1448 LE) PLL DATA

D/A DATA 2

3

4

5

6

Parallel Port

Figure B-6 Time chart

在文檔中 KU-Band 頻率合成器設計 (頁 74-0)