KU-Band frequency control loop measurement

Figure 2-37 shows the KU-Band frequency control loop measurement setup diagram. This is the software that can be used to program a PLL via the parallel port of a computer. The software introduction is shown in Appendix B.

Parallel Port

Spectrum analyser

NoteBook

DUT

Data , Clock and LE Control lines

out

out

f P .

Dir Coupler

. ( 8) Freq Divider

÷

PLL Circuit Loop Filter

f

ref

VTDRO

. RF AMP

Figure 2-37 KU-Band frequency control loop measurement setup diagram

Figure 2-38 is the lock-in time measurement of frequency control loop. Figure2-39 shows the spurious of the reference frequency leakage. The spur due to reference leakage is about 66.8 dBc. Figure 2-40 is the phase noise measurement of Ku-band frequency control loop. The value of phase noise is 97.17 dBc/Hz at 100KHz offset.

Figure 2-38 Lock-in time measurement of frequency control loop (11.225GHz jump to 11.275GHz)

Figure 2-39 Spurious of the reference frequency leakage

Figure 2-40 phase noise measurement of Ku-band frequency control loop at 100KHz offset

Chapter 3

RF Power Control Loop

In this chapter, we will discussed theory and design of the RF power automatic gain control (AGC) loop. The block diagram is shown as figure 3-1.

.

DC Level Sh ift Low Pass Filter

Figure 3-1 RF Power Control Loop block diagram

The function of RF control loop discussed as follow:

1、The input signal passes through the VCA to produce the output level to be stabilized.

The D/A converter was set by the computer and produces a reference DC voltage (AGC Set voltage).

2、The directional coupler tap the output power and feed it to RF detector and produces

a DC voltage proportional to the RF output power.

3、The DC amplifier provides a DC gain and produce detector’s output voltage.

4、The detector’s output voltage is compared against a AGC Set voltage to produce an

error signal, which is then integrated to produce a control positive voltage.

5、The DC level shift circuit transforms the control positive voltage into negative voltage for the VCA and adjusts RF output power.

3-1 Outline of Power Control Loop 3-1-1 Outline of AGC [5][6][19]

Many attempts have been made to fully describe an AGC system in terms of control system theory, from pseudo linear approximations to multivariable systems. Each model has its advantages and disadvantages, first order models are easy to analyze and understand but sometimes the final results show a high degree of inaccuracy when they are compared with practical results. On the other hand, non-linear and multivariable systems show a relative high degree of accuracy but the

theory and physical implementation of the system can become really tedious.

The basic block of automatic gain control loop show in figure 3-2. The input signal is amplified by a variable gain block (VGB) whose gain is controlled by a control

voltage . A cascade amplifier to generate and adequate level of can amplify the output from the VGB. The power detector senses the output level, any undesired component is filtered out and the remaining signal is compared with a reference signal V

R

. The result of the comparison is used to generate the and adjust the gain of the VGB.

Figure 3-2 basic block of automatic gain control loop

From figure 3-2, the AGC block diagram is essentially a negative feedback system and the system can be described in terms of its transfer function.

The idealization of AGC transfers function show in figure 3-3. For low input level the AGC is disabled and the output is a linear function of the input, when the output reaches a threshold value, , the AGC becomes operative and maintains a constant output level until it reaches a second threshold value ( ). At point of , the AGC becomes inoperative again; this is usually done in order to prevent stability problems at high levels of gain.

1

V i

2

V i V _i

₂

V o

V i 2

V i 1

V i V

o

∆

Ideal Curve Real Curve

Figure 3-3 the idealization of transfer function for an AGC system

Unfortunately, the AGC system is considered a nonlinear systems and it is very hard to find solutions for the nonlinear analysis.

However, there is a linear model that describes the AGC loop function with a good degree of accuracy and are relatively easy to implement when the small signal transfer equations of the main blocks are known. The block diagram for this model is show in figure 3-2. The variable gain block has the following transfer function and it expression is by

1

V

2

aV

c

P

=

K e

⁺ (3-1) and

1

aV

c

o i

V

=

V K e

⁺ (3-2)

Where

V

i

andV

O

are the input and output level.

K

1

is a constant and a is a constant factor of the VGB.

The logarithmic amplifier gain can be defined as follow

2 ln 1 ln 2

_o

V

=

V

=

K

(3-3) Where

K

represents the gain of the envelope detector.

In order to simplify, we assume that the output of the envelope detector is always positive. The control voltage becomes:

( )( 2) ( )( ln )

c R R

V

=

F s V

−

V

=

F s V

−

K V

₂

_o

i

2

R

1 2

(3-4)

where

F(s) represents the filter transfer function.

By expending (3-2), the

V _c

can be written as:

ln ln 1

c o

aV

=

V

−

K V

(3-5)

From (3-4) and (3-5), we get :

ln

V _o

[1+

aF s

( )]=ln

V _i

+

aF s V

( )

_R

+ln

K

1−

aF s V

( ) ln

K

(3-6)

Since we are only interested in the output-input relationship, let and be equal to one. Thus, the above equation becomes:

K K

ln

V _o

[1+

aF s

( )]=ln

V _i

+

aF s V

( )

_R

V o

(3-7) If

V _o

and

V _i

are expressed in decibels, we can use the following equivalence

ln

V _o

=2.3log (3-8)

ln

V _o

= 2.3

V _odB

=0.115

V _odB

20 (3-9)

Finally, the equation (3-7) that relates input and output can be rewritten as

8.7 ( )

1 ( ) 1 ( )

idB R

odB

V aF s V

V

=

aF s

+

aF s

+ + (3-10)

The equation (3-10) shows a linear relationship as long as input and output quantities are expressed in decibels and it is easy to see that the function of the system is determined by the filter F(s) and the a factor of the VGB. F(s) is usually a low pass filter, since the bandwidth of the loop must be limited to avoid stability problems and to ensure that the AGC does not respond to any amplitude modulation that could be present in the input signal.

In any control system, an important parameter is the steady-state error that is defined

Applying the definition given above to the AGC loop we find that the position error constant is given by:

1

Thus, in order to maintain the steady state error as small as possible the DC gain of the F(s) block must be as large as possible .The F(s) block that can be used in the loop is a first order low pass filter whose transfer function is defined as follows:

( )

where

K is the DC gain of the filter.

B is the bandwidth.

Using this expression in the equation of the steady state error we find that:

1

e ss

=

1 aK+ (3-14)

The total DC output of the AGC loop is given by:

IDC

8.7

R

oDC

V aKV

V

= +

1+

aK

1+

aK

R

i

(3-15)

It can be seen that if the gain loop K is much greater than 1, the output is almost equal to 8.7

V

and the steady state change in the input is greatly reduced. AGC loop that include a reference voltage inside the control loop are referred as delayed AGC.

Since we are interested in the change in the output voltage due to a change in the input voltage we can take the derivative of with respect to . From (3-1) and (3-2), the output voltage becomes:

V o V _i

V o

=

PV

(3-16) therefore

( )

dV

, we can be further developed applying the chain rule and using the equation for the control voltage, thus:

c c o o

(

i c i c o i c i o

dV dV dV dV

dP dP dP dP F

dV

=

dV dV

=

dV dV dV

=

dV dV

−

V

) (3-18)

Therefore, the equation (3-17) can be rewritten as:

[1 ]

From (3-20), It is clear that the loop gain is a function of the input signal. That translates into a relative degree of non-linearity and complicates the analysis of the transient response of the system.

However, it is possible to numerically evaluate the characteristic parameters of the loop if the function is know and a set of initial conditions is taken as a starting point.

( )

_c

P V

3-1-2 Outline of VCA

In the microwave circuit, attenuators are useful in reducing the power level of RF signals by a specific amount. The basic structure is shown as figure 3-4.

R b R ^b

R a

RF in

(a)

R

2

R

1

R

₁

RF out

RF in

(b)

Figure 3-4 Basic structure of attenuator (a)π type (b) T type

In the application, the fixed attenuators and variable attenuators are two general configurations. The fixed attenuators allow one or more discrete levels of attenuation.

The variable attenuators allow a specific value of attenuation to be selected from an analog control voltage.

The PIN diode and the FET are commonly used in variable attenuators. In this case, we discuss the FET voltage variable attenuator of the T type. Figure 3-5 shows the T type resistance attenuator and equivalent circuit of FET.

R

2

R

1

R

₁

RF out

RF in

(a)

D

S

D S S

RF in RF _out

V

1

V

2

(b)

Figure 3-5 The T type resistance attenuator (a) resistance attenuator (b) equivalent circuit of FET

In generally, the attenuator of FET requires two bias voltages, one applied to the series FETs (

V

₁) and one applied to the shunt FETs (

V

₂).As voltages

V

₁ and

V

₂are

varied between V

c1

and V

c2

the FETs “on” resistance changes. At V

c1

control, the FET is turned fully “on” resulting in a low resistance state. At V

c2

control, the FET is in a fully “pinchedoff” state resulting in a high resistance state. When the control voltages are between V

c1

and V

c2

, the FETs are neither fully “on” nor fully “off” but are in a variable resistance state that is a function of control voltage.

The control voltage vs. attenuation curve is shown in Figure 3-6 and is typical for the AT006N3-01 of Alpha Industries, Inc. We can find the curves are not a linear function. This occurs because the FET’s resistance is a non-linear relationship with respect to control voltage and increases very quickly as the control voltage approaches

“pinch-off”.

Figure 3-6 Typical for the AT006N3-01 of Alpha Industries, Inc

3-2 Power Control Loop Design

3-2-1 Ku-band Power Detector Design

Figure 3-7 shows the basic construction of the RF detector[1]. The matching network is necessary so the maximum power can reach the diode and the conversion from RF to DC can take place efficiently.

Matching Network

RF Signal Input DC Output

MA4E2054 Schottky Diode

10K 100nF

Figure 3-7 Basic construction of the RF detector

The RF power from amplifier and feeds it to a Schottky diode detector. It produces a DC voltage proportional to the output, which is then fed back to the AGC controller.

The linear equivalent circuit can provide insight into the performance of the Schottky diode (see figure 3-8). Lp and Cp are package parasitics. A three eelement equivalent circuit can represent the diode chip itself, including Rs (parasitic series resistance), Cj (parasitic junction capacitance) and Rj (the junction resistance). Figure 3-10 shows the RF imputer power versus output dc voltage.

11 ohm

D iode linear equivalent circuit

D iode w ith Package M odel

Figure 3-8 equivalent circuit of Schottky diode

RF Detector Performance

Figure 3-10 RF imputer power versus output dc voltage

3-2-2 Ku-band VCA Design

The GaAs MESFETs at zero drain bias have been used as variable resistors to construct a new module of T-type attenuator. The S parameter of new module must reconstruction. In this case, the NE32584c can provided

R by the _ds V . The test setup _gs

is shown figure 3-11.

D

S

D S S

VC

1

− 0.5V

R C

100K

0.1uF

Network Analyser

Port 1 (S11) Port 2 (S22)

DUT

100pF

L1 L2

L1 , L2 =>1/4λTransmission Line @11.25GHz

Figure 3-11 T-type attenuator module of NE32584c

In second step, input and output the simulation software designed match circuits.

The final circuit and simulation result are shown as figure 3-12 and figure 3-13. It can provide 18 dB dynamic range by the

VC

and 3 dB insertion loss. The network analyzer and spectrum analyzer measured the characteristic of VCA. The measurement data are shown as figure 3-14 and figure 3-15.

1

Figure 3-12 VCA final circuit

Spectrum analyser

Control Voltage

SG Signal input VCA Signal outputput

SG output power = 0 dBm

(a)

(b)

(c)

Figure 3-14 VCA measurement (a) measurement setup (b)insertion loss measure(c) attenuation performance at 0V control voltage

VCA Attenuation Performance @ 11.25GHz

-25 -20 -15 -10 -5 0

0 -0 .1 5

-0 .2 75

-0. 35

-0. 42 5

-0. 5

-0. 65 -0 .8

-0 .95

VCA Control Voltage (V)

Attenuation Power (dBm)

Figure 3-15 VCA attenuation performance

3-2-3 AGC Loop Design

The AGC loop controller block diagram and schematic are shown figure 3-16. The LT1112 is dual op amps and achieve DC amplifier, Integrator and DC level shift circuits. The LTC1448 is a dual rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC). It includes rail-to-rail output buffer amplifiers and an easy-to-use 3-wire serial interface.

+ C

12 bit D / A C onverter

RF Signal Set DC Amp .

DC Level Sh ift Low Pass Filter

To VCA Control Voltage

Form RF Detector

OP AMP DC power supplely : +/ 5V 100Hz active LPF 2.5V

(b)

Figure 3-16 AGC loop structure (a) block diagram (b) schematic

3-3 Power Control Loop Measurements

Finally, we should measure the power control loop performance. The test setup is shown as figure 3-17.

.

DC Level Sh ift Low Pass Filter

Figure 3-17 Power control loop measurement setup (a) block diagram (b) measurement etup

The dynamic range of control loop measurement is shown figure 3-18. The range adjust from 4 dB to -15 dB and the flatness of output measurement is shown figure 3-19.

(a)

(b)

Figure 3-18 Dynamic range measurement

Figure 3-19 synthesizer output flatness

The synthesizer phase noise measure is shown figure 3-20. The power control loop not degrades phase noise performance.

(a)

Figure 3-20 synthesizer phase noise at 100 KHz offset

Figure 3-19 presents the measured frequency tune range. The output power of synthesizer was kept by the power control loop and adjustment output power. The table 3-1 shows the synthesizer specifications.

Frequency Range 11.23GHz to 11.85GHz Output Power +4 dBm to –15dBm Phase noise 97.83 dBc @ 100KHz DC power supply +15V ; -5V

Table 3-1 The synthesizer specifications.

Chapter 4

CMOS LC Oscillator and Frequency Divider Design

In this chapter, we present a method for design of CMOS Voltage controlled oscillator (VCO) and frequency divider. They are fully integrated in bulk CMOS technology operating at 5GHz. Figure 4-1 is shown the block diagram.

VCO V ct

2

Div Div 2

f in

2 f in

4

in out

f = f ( ) a

( ) b

f out

Figure 4-1 CMOS simulation block diagram (a) CMOS VCO simulation block diagram (b) frequency divider simulation block diagram

4-1 CMOS Voltage controlled oscillator (VCO) Design

For fully integrated CMOS oscillator, two common approaches are ring oscillators and LC oscillators (see figure 4-2). The advantage of ring oscillators is without any passive element such as inductors and capacitors. Because of there is no filtering action shaping the phase noise of the output signal, the ring oscillators generally show a very poor phase noise performance compared to LC oscillators [32].

VDD

NMOS NMOS

1

V out V _{out 2}

VDD

Ibias

( ) b ( ) a +

+

V in V _out

Figure 4-2 CMOS common approaches oscillator (a)Three-stage ring oscillators (b) LC oscillators

A LC oscillator consists of a parallel LC tank and active circuit that compensated for the losses in the passive elements. The LC tank resonates at the

frequency

0

1

ω

=

LC

(4-1) In the RF CMOS design, the lack of high-quality on-chip inductors is one of the major drawbacks. The most common topology of on-chip inductors is the square spiral and circular spiral inductors.

In the VCO, the oscillators frequency must be tunable by the varactor element .The capacitance of a varactor can be controlled between C1 and C2 by a control voltage. For ideal VCO, it is a linear function of the control voltage .The function and block of VCO are shown in figure 4-3.

VCO

ω

out

V

ct

ω

out

V

ct

V

2

V

1

ω

2

ω

1

0

out

K

VCO

V

ct

ω = ω + ( ) a

( ) b

Figure 4-3 VCO function and block diagram (a) VCO diagram (b) VCO function

4-1-1 Topology of an NMOS-PMOS LC oscillator

In this case, the conventions NMOS-PMOS cross-coupled oscillator (see figure 4-4) is used as the design for several reasons. The differential operation mitigates undesirable common-mode effects such as DC supply noise and extrinsic substrate. For the same bias circuit, the oscillation amplitude of this configuration is a factor of two large than that of the NMOS-only structure. The rise and fall time symmetry of oscillation waveform reduces the up-conversion of the transistor noise.

VDD

Ibias

PMOS PMOS

L

Varactor

NMOS NMOS

1

V out V _out

₂

2

C load

1

C load

Figure 4-4 NMOS-PMOS cross-coupled oscillator schematic

The small-signal equivalent model of NMOS-PMOS cross-coupled oscillator is shown in figure 4-5. The equivalent capacitance of a NMOS-pair and a PMOS-pair between the two nodes are thus

[33]

:

Figure 4-5 Small-signal equivalent circuit of the VCO core

The small-signal transconductance of a single NFET and PFET were defined and . In the NMOS-PMOS LC VCO, the output signal is the differential voltage

. From figure 4-4, the

tan tan tan

lim

for current limited regime for voltage limited regime

bias

The design process can be summed up in following steps:

1、 Set

g _mn

=

g _mp

to improved the 1 3

f

corner of phase noise.

2、The tail current is set depending on the power consumption limit .

3、 The conductance is calculated keeping in mind the voltage swing specification

tan

out bias k

V

≤

I R

(4-3) 4、 To ensure start-up the gm of cross-couple devices are set 4 time more than

g

_{tan k}

tan

4

k

gm

g

≥ (4-4) 5 、The maximum and minimum capacitance value needed for the required tuning range

of frequency is calculated as

min

f

region can be predicted using Leeson’s equation [][]:

F =Oscillator frequency

0

Q =Loaded resonator quality

∆ =Frequency offset with respect to the carrier

f

F =Flicker noise cutoff frequency of the transistor amplifier c

F

T

=Noise factor of the transistor amplifier

k

=Boltzmann’s constant

=Temperature in Kelvin

P =Output power of the oscillator

0

4-1-2 Simulation result of a 5GHz NMOS-PMOS LC VCO

In this case, the Hspice and Laker software achieved the 5GHz NMOS-PMOS LC VCO design. Figure 4-6 presents the schematic of the VCO. The post simulation result is show in Figure 4-7. Figure 4-8 and table 4-1 are shown the VCO layout and VCO specifications.

L VC1

MN1 MN2

1

V out V _out

₂

2

C load

1

C load

VDD VDD

R

VC2

C1 C2

MP1 MP2

MP3 MP4

VDD VDD

Vct

(a)

Device MP1 MP2 MP3,MP4 MN1,MN2 C1,C2 R

L/W 0.24u / 50u 0.24u / 140u 0.24u / 120u 0.24u / 40u NC 2.7K

Device L

C load

1,

C _load

₂ VC1, VC2

2nH 0.4pF 0.5pF

(b)

Figure 4-6 VCO schematic (a) schematic (b) CMOS size

(a)

(c)

(d)

Figure 4-7 CMOS VCO simulation result (a) VCO start up (b) phase noise (c) VCO tuning range

Item

Voltage Supply 2.5V

Frequency Tuning range 5.3GHz to 5.7GHz

Output Load 0.4pF

Output Swing Amplitude 1.3 V

_p-p

Power Consumption < 20 mW

Table 4-1 VCO specification

4-2 Frequency divider design

In the 5GHz frequency synthesizer, the frequency divider is important circuit . It is to be used in a phase locked loop to step down the frequency of VCO. The circuit most difficult to design is the first stage of diver, which should operated at 5GHz .In the case, the source-coupled latch has a reduced output swing that facilitates high speed.

The block diagram of the frequency divider is shown in figure 4-1(b). This divider implemented a cascade of 2 divider by 2 circuits.

The conventions schematic of source-coupled latch is shown in figure 4-9. It consists of a differential amplifier (M3, M4) and a regenerator (M5, M6) . Two FETs are placed between the current source and differential/regenerator, they are acting switches controlled by the

CK

and

CK

signals. When the M2 is turn on by the clock activated, the function of differential amplifier is passing the input signal to the outputs. When the M1 is turn on by the clockbar activated, the regenerator lactching the outputs

Q

and

Q .

NMOS NMOS

Ibias

Ibias

VDD VDD

NMOS

NMOS PMOS

Vbias

D D

Q Q

CK CK

M1

M2

M5 M6

M3 M4

Figure 5-9 conventions schematic of source-coupled latch

The two latches achieved the unit stage of divider. Two latches can be connected as shown in figure 4-10. The output of one latch is fed to the input of the second, whose output is inverted and tied back to the inputs of the first latch. This results in an output signal, taken from the outputs of the second latch, that has half the frequency of the clock signal.

CK CK

Q

Q D

D CK CK

Q

Q D

D

Master Slave

CK CK

f

out

f

out

out

2 f = CK

Figure 4-10 unit stage of divider

The design considerations of the basic latch are as follows:

1、 The FETs are biasing in the active region , they will allow for fast operation of the FETs. The proper overdrive voltages and sizeing of the FETs can cerated by the proper biasing of the gate voltage.

2、 The regenerator FETs have a large enough gm can overcome the pull up resistors . This is keep the outputs

Q

and

Q latched to VDD and id*R.

4-2-1 Simulation result of a 5GHz frequency divider

In this case, the 5GHz frequency divider design was achieved by the Hspice and Laker software. Figure 4-11 presents the block diagram of the divider and the schematic of divider is shown figure 4-12. The post simulation result as show in Figure 4-13.

Figure 4-14 and table 4-2 are shown the divider layout and VCO specifications.

CK

1

CK

1

Q

₁

Q

1

Divider 1

C1

C2

R2 R1

CK CK f

in

2 f

in

4 f

in

Vbias2 Vbias1

CK

2

CK

2

Q

₁

Q

1

Divider 2

Figure 4-11 Frequency divider block diagram

VDD

MN1

MN2

MN5 MN9 MN10 MN6

VDD

R3

VDD

MN3

MN4

MN7 MN11 MN12 MN8

VDD

VDD

MN15

MN16

MN19 MN23 MN24 MN20

VDD

Device MP1,MP2 MN1,MN3 MN2,MN4 MN5,MN6 MN7,MN8 MN9,MN10 L/W 0.24u / 35u 0.24u / 40u 0.24u / 80u 0.24u / 80u 0.24u / 80u 0.24u / 40u Device MN11,MN12 MN13,MN14 MN15,MN16 MN17,MN18 MN19,MN20 MN21,MN22

L/W 0.24u / 40u 0.24u / 10u 0.24u / 40u 0.24u / 40u 0.24u / 40u 0.24u / 40u Device MN23,MN24 MN25,MN26 MN27,MN28 MN29 MP3

L/W 0.24u / 40u 0.24u / 40u 0.24u / 160u 0.24u / 10u 0.24u / 35u

Device C1,C2 R1,R2 R3

L/W 30u / 30u 1.6k 0.2k

(c)

Figure 4-12 Frequency divider schematic (a) divider1 schematic (b) divider2 schematic (c)CMOS size

Figure 5-13 CMOS frequency divider simulation result Figure 4-13 the post simulation result

Item

Voltage Supply 2.5V

Input Frequency range 5.3GHz to 5.7GHz Output Frequency range 1.325Ghz to 1.425GHz

Input Swing Amplitude 0.6 V

p-p

Output Swing Amplitude 1V

_p-p

Power Consumption < 80 mW

Table 4-2 divider specification

Chapter 5 Conclusion

In this thesis, the basic principles of phase-locked loop, automatic gain control loop and CMOS integrated circuit are explored. Special attentions have been directed to the performance of power level control and frequency control.

In the Ku-band frequency synthesizer, this new structure is realized by inserting AGC loop behind the phase-locked loop. The power level and frequency can be

In the Ku-band frequency synthesizer, this new structure is realized by inserting AGC loop behind the phase-locked loop. The power level and frequency can be

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