Simulation result of a 5GHz frequency divider

In this case, the 5GHz frequency divider design was achieved by the Hspice and Laker software. Figure 4-11 presents the block diagram of the divider and the schematic of divider is shown figure 4-12. The post simulation result as show in Figure 4-13.

Figure 4-14 and table 4-2 are shown the divider layout and VCO specifications.

CK

1

CK

1

Q

₁

Q

1

Divider 1

C1

C2

R2 R1

CK CK f

in

2 f

in

4 f

in

Vbias2 Vbias1

CK

2

CK

2

Q

₁

Q

1

Divider 2

Figure 4-11 Frequency divider block diagram

VDD

MN1

MN2

MN5 MN9 MN10 MN6

VDD

R3

VDD

MN3

MN4

MN7 MN11 MN12 MN8

VDD

VDD

MN15

MN16

MN19 MN23 MN24 MN20

VDD

Device MP1,MP2 MN1,MN3 MN2,MN4 MN5,MN6 MN7,MN8 MN9,MN10 L/W 0.24u / 35u 0.24u / 40u 0.24u / 80u 0.24u / 80u 0.24u / 80u 0.24u / 40u Device MN11,MN12 MN13,MN14 MN15,MN16 MN17,MN18 MN19,MN20 MN21,MN22

L/W 0.24u / 40u 0.24u / 10u 0.24u / 40u 0.24u / 40u 0.24u / 40u 0.24u / 40u Device MN23,MN24 MN25,MN26 MN27,MN28 MN29 MP3

L/W 0.24u / 40u 0.24u / 40u 0.24u / 160u 0.24u / 10u 0.24u / 35u

Device C1,C2 R1,R2 R3

L/W 30u / 30u 1.6k 0.2k

(c)

Figure 4-12 Frequency divider schematic (a) divider1 schematic (b) divider2 schematic (c)CMOS size

Figure 5-13 CMOS frequency divider simulation result Figure 4-13 the post simulation result

Item

Voltage Supply 2.5V

Input Frequency range 5.3GHz to 5.7GHz Output Frequency range 1.325Ghz to 1.425GHz

Input Swing Amplitude 0.6 V

p-p

Output Swing Amplitude 1V

_p-p

Power Consumption < 80 mW

Table 4-2 divider specification

Chapter 5 Conclusion

In this thesis, the basic principles of phase-locked loop, automatic gain control loop and CMOS integrated circuit are explored. Special attentions have been directed to the performance of power level control and frequency control.

In the Ku-band frequency synthesizer, this new structure is realized by inserting AGC loop behind the phase-locked loop. The power level and frequency can be controlled. The frequency change and output power level of synthesizer will be compensated or set by the computer. In the thesis, we show the measurement data of AGC loop function. It can reduce VTDRO output power flatness from +3dB to +0.6dB and the output power of synthesizer can be set from +4dBm to –15dBm. Unfortunately, we found some problem of synthesizer. The output power flatness had varied +0.7dB by the AGC loop steady-state error. That is from device nonlinear characteristic. Other problem of synthesizer, the divider of PLL controller degrades phase noise at 10KHz offset. We will cope with problems in the future. For application, this synthesizer connects with mixer or frequency multiplier generator and adjusting the synthesizer output power and frequency for the optimum performance.

In the CMOS integrated circuit, the conventional analysis of mentioned briefly.

The analysis method gives designers a clear insight so the high performance voltage-controlled oscillator and frequency divider can be obtained. The circuit design process, simulation and layout are shown in the thesis.

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Appendix A

In this chapter, we will discuss the design and analysis of active loop filter. There are also op-amp based loop filter topologies as shown in the figure A-1.

R2

From (2-15), we can find the relationships of Phase margin, Damping factor and Natural frequency. The table A-1 is show the relationships.

Phase margin , ψ Phase margin ,

ξ

Natural frequency ,

ω _n

The term of loop filter shown in as follows:

(1)

f _Range

– Frequency range of synthesizer.

(1)

f _step

– Maximum frequency change during a step or hop, from one frequency to

another.

(3)

f _CH

– Channel spacing.

(2)

t – The desired time for the carrier to step to a new frequency. _s

(3)

f – The frequency of the carrier, within the desired time (ts), after a step or _a

1 2

10

C

=

C

(A-4)

3 2

R

=

R

(A-5)

2

3 10

C

=

C

(A-6)

2 ( 1 4 2 f n

Loop Bandwidth

π ζ )

+ ζ

=

(A-7)

Appendix B

In this chapter, we will discuss PLL and D/A converter code generator. This program is designed to run LMX1600 and LTC1448. The code generator is base on LabVIEW. The LMX1600 is integrated dual frequency PLL and the IF band was disabled by program code. The LMX1600 data registersand a sample setting is shown as Figure B-1. The R counter determines the channel bans width. The N counter determined the output frequency. Figure B-2 shows the LMX1600 registers structure. In the table B-1, for each register the MSB and is loaded first.

For the LTC1448, The data is loaded as one 24-bit word where the first 12 bits are for DAC A channel and the second 12 are for DAC B channel. For each register the MSB and is loaded first . The data structure is shown as figure B-3.

The series data was generator by the LabVIEW and program signals from the parallel port of the computer.When the load command is used, all data in all registers is sent . The LabVIEW control plane and program process are shown as figure B-4 and figure B-5. Figure B-6 show the time chart.

Ref.

20MHz

R Counter R=32

Prescaler Divide-by-16

VTDRO 11.22GHz to 11.28GHz Divide-by-8

N Counter N= 2244 to 2256

Charge Pump

Loop Filter Phase

Detector

LMX1600

Figure B-1 LMX1600 data registers

Figure B-2 LMX1600 data registers structure

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DAC A Input DAC B Input

MSB LSB

Figure B-3 LTC1448 data registers structure

Figure B-4 LabVIEW control plane

Figure B-5 LabVIEW program process

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

2 3 4 5 6

CLOCK

PLL DATA(LMX2330 DATA) PLL LE(LMX2330 LE) D/A DATA (TLC1448 DATA) D/A LE (TLC1448 LE) PLL DATA

D/A DATA 2

3

4

5

6

Parallel Port

Figure B-6 Time chart

在文檔中 KU-Band 頻率合成器設計 (頁 91-0)