CHAPTER 2 CIRCUIT ARCHITECTURE AND SIMULATION
2.3 CIRCUIT DESIGN
2.3.3 Quadrature mixer
This section discussed the principle and design methodology of the
downconverter mixer. Consider the Fig. 2.22, refer the drain current of basic unit PMOS cell. By means of the PMOS drain current operating equation in saturation, the mixer can achieve the mixing operation.
PMOS is a basic unit cell in this mixer design. First, we can observe that the PMOS current is the function of gate to drain voltage in saturation region.
)2
In order to simplify the following analysis and to make it clearly, replace the gate and drain terminal to ‘Va’ and ‘Vb’ respectively. The drain current of the PMOS device can be written as
( )
]Thus, the voltage of Vmx1 shown in Fig. 2.22 will become (Vt is replaced by constant value C )
Fig. 2.22 Basic PMOS unit cell of mixer
Va
Fig. 2.23 Mix Va and Vb operation constructed by two basic PMOS device
Illustrate in Fig. 2.23, merge two basic PMOS unit cells as and summation the Id current flow through the ZL. The Id current can be deriving as.
( )
Fig. 2.24 double-balanced mixer structureThe Fig. 2.24 shows the double-balanced mixer structure.
Vb
To replace the sign of equations. It can be Va=LOIP, -Va=LOIN, Vb=MXIP, -Vb=MXIN
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
VBMXIF
MP5 MP7 MP6 MP8
MP1 MP3 MP2 MP4
MXIP
MXIP
MXIN MXIN MXIP MXIN
VBMXRF
LOIP LOIN LOQP LOQN
1k 1k
MN2 MN3 MN4 MN5
MN1
XC2
XC1
XC4
XC3 IFIP
IFIN IFQP
IFQN
Fig. 2.25 Quadrature downconversion mixer schematic
Device Name W/L(um/um) MP1,MP2,MP3,MP4,
MP5,MP6,MP7,MP8
5/0.3 MN1,MN2,MN3,MN4 10/0.24 XC1,XC2,XC3,XC4 0.9p
Table 2.3 Mixer device parameter
2.3.4 Active polyphase filter
The polyphase filter and output buffer are the last stage of receiver front-end system. The polyphase filter stage that follows the mixer and selected the desired signal to output. The polyphase filter is used to reject image interference in a receiver front-end system. It must have the features with high image rejection ratio, low sensitivity to mismatching components, sufficient linearity, and low power consumption in the design of integrated RF front-end receiver. When the input signal is clockwise or positive frequency, the RF signal down converted IF signal passes to output. Contrary, the signal is anti-clockwise or negative frequency; the
filter should reject the image IF signal. In the application of monolithic integration, the polyphase filter design must be easily integrated in a receiver chip.
The polyphase filter is a complex filter; most of popular of polyphase filter is RC sequence network. It is comprise of two passive components, which are resistor and capacitance to do the filter operation. The center frequency of one-stage RC polyphase filter can be determined byω =1/RC for narrow band design.
The amplitude of the output will be equal only at the input frequency. The transfer function of RC network depends on phase order of the input sequence. In order to prevent process variation and increase variation guard band, a multi-stage RC network can be used to achieve a broadband design. M-stage network can be constructed by cascading M-stage to expand the bandwidth of the filter. The 4-stage RC polyphase filter network is shown in fig. 2.26.
Fig. 2.26 4-stages RC network polyphase filter
The main disadvantage of the multi-stage RC polyphase filter is its signal loose. This will cause received signal decay and decrease the noise figure (NF) performance of the receiver system.
In this thesis, we use an active polyphase filter for the Low-IF receiver application. The advantages of the active polyphase filter are its high input impendence in each stage and provide enough gain to amplify the IF desired signal. It prevent the degradation of the gain lose. Besides, it eliminates the extra
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
power dissipation. Simultaneously, the high gain is assigned to the first stage to improve the better noise performance.
The main consideration of polyphase filter is its image rejection ratio (IRR), tolerance in process variation, bandwidth, linearity and power consumption.
As the transfer function of complex filter, this is similar to RC network polyphase filter to perform the positive or negative frequency filter. The filter must distinguish positive frequency and negative frequency. In the point of view in filter transfer function, it is combination of 1st order low-pass and high pass transfer function. The transfer function of a complex filter can be represented as.
) rewritten as
))
The block diagram of simple complex filter was presented in Fig. 2.27.
)
Fig. 2.27 The principle of complex filter
To expand the equation to first order high pass and low pass filter with single pole. The transfer function
H
(s)can be represented as follow.⎟⎟
Where A is the gain of the transfer function and
ω
pis the position of single pole. and are the first order low pass and high pass equation. The image signal can be rejected by this equation at the frequency)
1(s
H H2(s)
ω
p. A 1-stage polyphase filter can be implemented by combination of first order low-pass and high-pass filter circuit.H1(ω)
-Fig. 2.28 Using real filter realize complex filter
In order to increase the tolerance of process variation, the bandwidth of filter must be expanded. Wide bandwidth can be achieved by cascade multi-stage.
HP1
-Fig. 2.29 The four-stage polyphase filter
This design implements a four-stage polyphase filter to expand the
bandwidth and enhance the tolerances of process variation. Fig. 2.29 illustrates the four-stage polyphase filter design in this chip. The poles of each stage are
difference to fine-tune the bandwidth and operating frequency. The poles are determined by changing CH for each one-stage polyphase filter.
The polyphase filter also provides enough gain to amplify the IF signal and prevent the best performance of linearity.
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
p MHz k
fp RC 2.76
6 . 3 6 . 3 2
1 2
1 =
⋅
= ⋅
= π π
Fig. 2.30 Polyphase filter input bias.
Fig. 2.31 1-stage polyphase filter
Fig. 2.32 4-stage polyphase filter
Fig. 2.33 output buffer
Type Passive
Polyphase filter
Active
Polyphase filter pole
Decided by
RC
(W/L)mp3=(W/L)mp4=α (W/L)mp1
Device RC MOS, C
Area Large area Small area
Input impedance Low input impedance High input impedance
Gain Lossy Provide gain
Extra amplifier Additional buffer no need of extra amplifier Power More power for buffer Smaller than passive filter Table 2.4 Compare with passive and active polyphase filter.
The mirrored current I3 is then divided into IL and IH by a diode-connected transistor MI, and a capacitor, CH, respectively. IL and IH can be derived as.
)
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
) ( 1
1
Ch s gm
s gm r
Vp Voh
+
⋅
⋅
= ⋅α
(27)
Whereα is the value of (W/L)3/(W/L)1, and gml and gmh are the transcoductances of Ml and ML, respectively.
(W/L)mp3=(W/L)mp4=α (W/L)mp1
The bias voltage of each stage must adjust to gain a best performance of receiver. It is observed the positive frequency gain loss in lower frequency. It is because of the input stage HP filter. It is shown in Fig.2.30. The pole of the HP filter is about 2.76MHz. Lower pole frequency is best but it is trade-off between area and low pole. The Fig. 2.31 presents the circuit of 1-stage polyphase filter.
Fig. 2.32 presents the circuit of 4-stage polyphase filter. The output buffer is shown in Fig.2.33.
Table 2.4 shows the comparison between passive and active polyphase filter.
The main disadvantage of the multi-stage passive polyphse filter is that it is lossy, and thus received signal decays and the overall noise figure (NF) of the receiver is degraded. Additional buffer should be inserted among stage to overcome this drawback. However, additional buffer means it consumes extra power.
Furthermore, a larger area is required to implementation numbers of passive resistors and capacitors in the RC polyphase filter.
2.4 RECEIVER REALIZATION
The designed receiver has been implemented on a single testchip; it
comprises a body-biased LNA, a quadrature VCO, a quadrature mixer, polyphase filter and an output buffer. 1-V power supply design is a challenge on TSMC 0.25-um technology in many conventional circuit structure. The body bias VBLNA for LNA to gain the headroom of LNA.
All inductors employed are spiral inductors made of top thick metal;
varactors are N-well structure; resistors are polysilicon with P-type implant. To avoid the body-effect, all N-mos device contain deep N-well for equal voltage between VBS. The model including spiral inductor, MIM capacitor, varactor and deep NWELL NMOS devices is supported by TSMC. The design is checked by LPE parasitic RC extraction based on TSMC’s spice model document to evaluate the simulation results.
In order To avoid body effect of NMOS, all NMOS devices contain deep N-WELL to make VSB voltage is zero. All spiral inductors made of top thick metal;
Varactors are N-WELL structure; resistors are made of polysilicon with p-type implant.
The buffer circuit as output stage follows the polyphase filter for
measurement. The circuit comprises four common-source stage, following the four terminals of the polyphase filter respectively. The Fig.2.30 in next page presents the complete schematic of proposed Low-IF receiver.
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
LNAOPLNAON
12.4N0.2p0.2p12.4N VBMXIF MP5MP7MP6MP8MP1MP3MP2MP4MXIP
MXIPMXINMXIN MXIN
MXIP VBMXRF LOIPLOINLOQPLOQN
1k1k
MN8MN7MN6MN2 MP5MP6MP2
XC4
XC1 QONIONVP
MN5MN4MN3MN1 MP3MP4MP1
XC3QOP
IOPVN
MN8MN7MN6MN2 MP5MP6MP2
XC4
MN8MN7MN6MN2 MP5MP6MP2
XC4
MN8MN7MN6MN2 MP5MP6MP2
XC4
MN8MN7MN6MN2 MP5MP6MP2
XC4
MN8MN7MN6MN2 MP5MP6MP2
XC4
XC1
LNA MIXER QVCO
4-STAGE POLYPHASE FILTER
BUFFER
Fig. 2.34 whole chip of receiver schematic
2.5 SIMULATION RESULT
The receiver chip is simulated by HSPICE. Post-simulation is completed by HSPICE with spice model of TSMC .25-um 1P5M process. This section presents the post-simulation results of all circuit constructing the receiver.
A. Low noise amplifier
LNA is the first stage of the receiver; it provides input matching, voltage gain and low noise contribution for the receiver. Fig. 2.31 and Fig. 2.32 show the simulated input matching (S11) lower than –20dB and voltage gain higher than 20dB, respectively.
Frequency (Herz)
Gain (dB)
FF FS TT SF SS
Frequency (Herz)
Gain (dB)
FF FS TT SF SS
Fig. 2.35 simulated voltage gain of the LNA
This fig.2.35 shows the dependence of gain due to process variation. The gain is about 12dB in worst case SS corner simulation. The gain of LNA can guarantee at least larger than 10dB for five corner simulation and meet the specification.
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
Fig. 2.36 The simulated input matching (S11) of the receiver
The Fig.2.36 shows the body bias sweep from 0.3V to 0.6V, the input matching (S11) of LNA can guarantee smaller than -12-dB.
(a)
Fig. 2.37 (a) LNA P-1dB HSPICE simulation result.
(b) redesign the LNA gain to 6dB, P-1dB can be improved to -5.5dBm
-10dBm
body bias and linearity
-14
body bias (V)
linearity (dBm)
P1dB@VBLNA=0.5V
Fig. 2.38 LNA noise figure SpectreRF simulation [email protected]
This work
Simulation results
Reference paper Experimental results with body bias w/o bulk bias
(same device size*)
Active body type LNA[11]
Body effect feedback[14]
Technology 0.25um bulk 0.25um bulk 0.35um SOI 0.18 bulk
Frequency 2.4GHz 2.4GHz 1.9GHz 1.65~2.5GHz
Bulk voltage 0.5V VBS=0V 0.5V 0.6V
Supply Voltage 1V 1V 1V 0.9V
Power
Consumption 3.17mA 3.5mA 5mA 2.5mA
S11 -20dB -20dB - -
Gain 20.2dB 16dB 7dB 10dB
NF 2.02dB 3dB 5.6dB 1.34dB
P-1dB -10dBm -13dBm -4.5dBm -16dBm
Table 2.5 The comparison between w/o body bias, w/i body bias.and reference paper
The comparison between w/o body bias, w/i body bias.and reference paper is listed in table 2.5. The main advantages of body biased LNA are gain and linearity for low power supply design [11].
1. Gain improvement
2. 1-dB compression point improvement
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
The body of the transistor is connected to its gate. The threshold voltage of the transistor becomes smaller due to body effect so that a large drain current is obtained which keeps the gain high even at a low supply voltage. An added feature of connection between the body and the gate is the high 1-dB compression point. This is because the transistor can drive large load
capacitance with a larger RFsignal input due to the active threshold voltage of the body control.
B. Quadrature Voltage control oscillator
The tuning range of VCO is shown in Fig. 2.33. The quadrature VCO oscillates 2376MHz~2639MHz by control voltage (VCOBIAS) from 0V to 1V
Fig. 2.39 The simulated tuning range of VCO
B. Quadrature downconverter mixer
The RF input, LNA output, quadrature VCO output , mixer I/Q IF output waveform are shown in Fig. 2.34. Low noise amplifier amplifies the input signal to the receiver. The voltage gain of LNA is about 20-dB. The simulated waveform is shown in Fig. 2.34(a). The quadrature voltage-controlled oscillator provides I/Q signal and mixes with LNA output. The quadrature VCO I/Q signal is shown in Fig. 2.34(b). The quadrature downconverter mixer down converts the RF signal to I/Q IF signal. The terminal of mixer output is IP, IN, QP, QN, separately.
Fig. 2.40 Mixer noise figure SpectreRF simulation NF=8dB@10MHz
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
Fig. 2.41 The transient analysis of downconverter (a) input and output of LNA (b) I/Q signal of quadrature VCO (c) output waveform of downconverter
C. Active polyphase filter
The polyphase filter is used to buffer the desired signal and reject the image signal. The simulated frequency response of polyphase filter is shown in Fig. 2.35.
The image rejection ratio is greater than 60-dB. In order to expand the frequency band, the four-stage polyphase filter is used. The required band is about
5MHz~10MHz. For 1-stage polyphase filter, the ideal equation are
o
Four poles is located at 13.26MHz, 10.62MHz, 8.85MHz, 7.07MHz. To map the ideal transfer curve and simulation results.
Fig. 2.42 The frequency response of polyphase filter
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
The frequency response of polyphase filter can be shown in Fig. 2.42.
p MHz k
fp RC 2.76
6 . 3 6 . 3 2
1 2
1 =
⋅
= ⋅
= π π
Fig. 2.43 The input stage HP filter
Technology 0.25um Power supply 1V
Gain in Bandwidth 6dB (5MHz~13MHz) THD -40dB IRR >60dB Power consumption 1.6344mW
Table 2.6 The performance summary of polyphse filter
Fig. 2.42 illustrates the input bias stage. It becomes a HP filter in each stage input. The gain degrade can be observed in Fig.2.42 at low frequency.
Table 2.6 summarizes the results of the simulation results of the polyphase filter. The image rejection exceeds 60dB over the range 5MHz to 13MHz. The THD (Total harmonic distortion) is -40dB when 10MHz, 100mV signal is applied.
The power consumption of polyphase filter is 1.6344mW.
C. The receiver analysis
The bluetooth required the gain greater than 10-dB in this receiver front-end.
The design of receiver must assigned to get enough noise figure and gain. Table 2.7 listed the gain and noise figure assignments in this receiver front-end system.
The spectrum of receiver is shown in Fig. 2.36. The following example is a 2.4-GHz input and 10-MHz output frequency spectrum. The output is split to two signals I/Q with 90-degree difference phase.
Stage LNA Mixer Polyphase filter Output buffer all
Gain 18dB -4dB 6dB -6dB 12dB
NF 2.03dB 8dB 8dB 6dB 8.2dB
Table 2.7 The gain and noise figure assignment
Fig. 2.44 The spectrum analysis of receiver
The noise figure of receiver is simulated by SpectreRF and shown in Fig.
2.45. The NF is equal to 8.8dB at 10MHz IF freqneycy.
Fig. 2.45 Output noise spectral density for receiver NF=8.2dB@10MHz
QVCO output(dB)
2410-MHz Homonic
Mixe output(dB)
10-MHz
CHPATER 3 EXPERIMENTAL RESULTS
CHAPTER 3
EXPERIMENT RESULTS
This chapter presents the chip layout, testing environment setting and experimental results. It also discussed and compared with post-simulation results regarding the measurement results
3.1 Layout Description
This receiver testchip can be divided in four parts. They are a Low-Noise amplifier, a quadrature VCO, a quadrature mixer, a polyphase filter with output buffer. The receiver layout and chip floorplan is shown in Fig. 3.1. The die photograph is shown in Fig. 3.2.
All the NMOS devices are placed on deep N-WELL (DNW), which is called R-WELL (RW) supported by TSMC 0.25-um technology. The external DNW drawing layer and mask must be used in this layout to define the RW region. The deep N-WELL isolates the NMOS to other device within the R-WELL. It can reduce the NMOS body-effect. For body-bias LNA, the NMOS bulk terminal can be biased to an independent power.
The guard ring surrounds each MOS device to avoid the substrate noise and signal couple. It also used to prevent the latch-up issue caused by parasitic SCR circuit for large MOS devices. The dummy POLY and dummy OD is usually inserted to reduce the side effect of process etching. The dummy metal is added in the top of layout, the dummy metal occupies large area. It is used to improve the metal density and to overcome the DRC density violation. To improve the metal
CMP process window, it must fill the dummy metal uniformly even if the originally drawn has already met the density rule. The dummy metal can be also worked as power line simultaneously.
The widely used on-chip inductor is spiral inductor. All spiral inductor must keep proper distance with the others and core circuit to prevent mutual inductance and disturbance on circuit. The source of spiral inductor layout cell is from
TSMC’s RF design library. The cell library is silicon proven and the measurement data is collected in SPICE model document for our reference.
The input resistance is an important key to contribute for noise figure. In order to reduce the input resistance, the LNA block is close to RF input to minimize input resistance. The LNA circuit is fully differential configuration, four-inductor belong to LNA are located surround with the NMOS devices and made them symmetrically as far as possible. Dummy gate and dummy resistors are equipped with every MOS device and resistor respectively to cope with process variation. The body of LNA NMOS input stage is connected to a bias voltage used to control its body bias voltage.
The chip floorplan must consider the optimum signal flow path. It should be as short as possible in metal routing and alleviate transmission line effect
especially for high frequency. The mixer places on the middle of the receiver chip.
It accepts LO signal from left side and LNA amplified RF signal from the bottom side of the chip. The mixer output transfer to right side and input into polyphase filter then to the output buffer. It can be observed that MIM capacitances occupy large area in polyphase region.
The fully receiver chip layout is shown in Fig 3.1 in the next page.
CHPATER 3 EXPERIMENTAL RESULTS
Fig. 3.1 The receiver chip layout
3.2 Testing Description
The receiver chip is a bare dies and needs to bond on a bonding board because it is more complicated for parasitic RC and inductance to place the chip on package. The purpose of testing board is to route the die pad to the testing equipments. The routing must be as short as possible to eliminate the parasitic RLC effect. The photograph of receiver chip and the bonding boards are shown in Fig. 3.2 and Fig. 3.3.
The input and output terminal are differential so that it needs external components like as balun and transformers for RF input and IF output in the
The input and output terminal are differential so that it needs external components like as balun and transformers for RF input and IF output in the