Experimental results

The receiver testchip has several components totally consumes about 18.575-mW DC power. The measurement data is slightly greater than the post-simulation results. The root cause is inferred that process corner variation. The supply voltage is 1-V to affect an inaccurate power consumption simulation results. The device current and power consumption can be evaluated by corner simulation.

The measurement DC bias condition is adjusted and it does the effort to get the best performance for the receiver testchip. After adjusts the bias DC operation point, the performance of receiver can be further close to the target of

specification. The DC bias conditions are listed in table 3.1.

Receiver Chip

RF input IF output

External matchi ng compensation

RF input IF output

External matchi ng compensation

DC Block

Fig. 3.7 bias conditions

BIAS CONDITION DESCRIPTION Volt

RFBIAS

RF input bias 0.6

VBLNA

LNA body-bias 0.4

VBMXRF

MIXER input bias 0.6

VBVCO

VCO frequency control bias 0~1

VBFT

Polyphase filter input bias 0.6

Table 3.1 DC bias tables

CHPATER 3 EXPERIMENTAL RESULTS

The input terminal parallels 1pF capacitance and adjusted the transmission line to compensate the performance of input matching (S11). The bond-wire inductance is estimated to have approximately maximum 3.2-nH variation. The input matching is compensated with 2.7-GHz, because the VCO frequency is shift up to 2.7-GHz. The input measurement of receiver input matching results is shown in Fig. 3.8. The receiver performs S11 better than –20-dB in band.

Fig. 3.8 The input matching (S11) of receiver

Fig. 3.9 The receiver output spectrum

The measurement of output spectrum is shown in Fig. 3.9, Markers 1~3 denote RF feedthrough, LO leakage and desired IF signal. The frequency of desired signal is 9.93-MHz. It is downconverted by mixing RF input and LO I/Q signal. RF feedthrough is about –55-dBm appears due to mixer mismatch and substrate couple. It cannot be simulated and is not predictable from an exact consideration by HSPICE simulation. LO leakage appears causes from similarly with RF feedthrough. The measured quantity of spurious emission such as RF feedthrough and LO leakage must satisfy the bluetooth specification.

To consider the loss of the external components and buffer loss, the gain of receiver must be compensated back and it performs over 7-dB gain in band.

CHPATER 3 EXPERIMENTAL RESULTS

Center 11.39468139 MHz 1.704099837 MHz/ Span 17.04099837 MHz RBW 500 kHz

Fig. 3.10 Output spectrum of IF signal

Ref Lvl

Center 2.7 GHz 32.95702379 MHz/ Span 329.5702379 MHz

-110

Fig. 3.11 The spectrum of LO leakage

VCO tunning range

2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20

0 0.2 0.4 0.6 0.8 1 1.2

VBVCO

frequency

VDDVCO=1V VDDVCO=1.2V VDDVCO=1.5V simulation

Fig. 3.12 The tuning range of VCO

Fig.3.10 shows the output spectrums of IF signal. The signal is in 10MHz IF band. The input power is -45-dBm. We can get the output power is -47.36dBm and IF frequency is 9.96-MHz. To compensate with 1.5-dB balun loss, 0.5-dB transformer loss and 8-dB PC board loss, and 6-dB output buffer loss. The receiver performs over 15-dB gain in band.

VCO tuning range can be analyzed by LO leakage observed on spectrum.

Fig.3.11 shows the LO leakage spectrum in output terminal. The Fig.3.12 shows the plot of VCO tuning range. The oscillation frequency can be tuned from 2.74~2.93 GHz under tuning voltage 0V ~ 1V. The VCO gain is 190MHz/V. The Smaller capacitance of MOS varactor estimate in model causes the measured frequency shift up about 300MHz with the post-simulation result.

CHPATER 3 EXPERIMENTAL RESULTS

Fig. 3.13 Output spectrum of two-tone test.

-80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00

-40 -35 -30 -25 -20 -15 -10

Input Power (dBm)

Output Power (dBm)

Measurement:1st order Measurement: 3rd order post-sim:1st order post-sim: 3rd order

-80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00

-40 -35 -30 -25 -20 -15 -10

Input Power (dBm)

Output Power (dBm)

Measurement:1st order Measurement: 3rd order post-sim:1st order post-sim: 3rd order

Fig. 3.14 Two-tone-test plot for IIP3

Fig 3.13 shows an output spectrum of two-tone test, where 1^st-order and 3^rd -order intermodulation signals are obvious. Fig 3.14 plots output-to-input power

relations. Compensate back with loss of external components. The measured receiver performs linearity of -15-dBm IIP3.

Noise figure is an indirect specification to adjust if a receiver contributes sufficiently low noise. Bluetooth requires SNR(signal to noise ration) higher than 12-dB to archive 0.1% BER(bit error rate). Noise figure is defined as ration of input SNR to output SNR. Minimum input SNR can be calculated as

Bluetooth requires SNR higher than 12-dB to achive 0.1% BER SNRinput.miin(dB)=sensitivity - channel bandwidth - Noise Floor =(-70) - 10log(10^6) - (-174) = 44dB

Nfmax(dB)=SNRinpu.min - SNRoutput.min = 44-12=32dB

Noise performance of the tested receiver is 15-dB. It is satisfies the

bluetooth requirement. HSPICE cannot simulate noise figure if a circuit involves frequency conversion so simulated noise figure is absent in this paper. But the LNA dominates total noise performance. A receiver can perform satisfied noise figure with a well designed LNA.

CHPATER 3 EXPERIMENTAL RESULTS

Fig. 3.15 The receiver gain with difference body-bias

receiver gain vs body bias

10 10.5 11 11.5 12 12.5 13 13.5

0 0.1 0.2 0.3 0.4 0.5 0.6

Body bias (V)

Gain (dB)

post-sim measurement

To fine-tune the body-biased LNA can adjust the gain of receiver. Fig.3.15 shows the receiver gain with difference body-bias. The measurement result shows the body-bias method improved about 2-dB gain. If the body-bias voltage rises over 0.6V, the forward PN junction current is turned on and the bias supply current injection into the bulk. It is observed the gain of receiver is degraded.

Fig. 3.16 and Fig.3.17 shows the receiver gain and its image rejection capability. The IF frequency is about 10-MHz. the receiver has 15-dB conversion gain. It compensate with the balun, transformer and output buffer loss, similarly.

The operating band is 9-MHz~11-MHz. The can get 41-dB image rejection ratio at 10-MHz. The minimum IRR is 36.8-dB in IF band. It is also meet the bluetooth requirement.

conversion gain

-35.00 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 5.00 10.00 15.00

0 5 10 15 20 25

frequency(MHz)

conversion gain(dB)

desired sim desired meas

Fig. 3.16 The performance of receiver gain.

convers ion gain

-40.00 -30.00 -20.00 -10.00 0.00 10.00 20.00 30.00

0 5 10 15 20 25

IF f requency(MHz)

Conversion gain(dB)

desired sim img sim desired meas img meas IRR=38dB IRR=36.5dB

Fig. 3.17 The performance of image rejection

CHPATER 3 EXPERIMENTAL RESULTS

Table 3.2 lists the summary of the tested receiver, it comparison between post-simulation and measurement results. The gain in measurement is

compensated with 1.5-dB balun loss, 0.5-dB transformer loss and 6-dB buffer loss.

The measured gain and IIP3 after from the post-simulation due to the

experimental biases and power consumption not identical with the post-simulation

ITEM Post-simulation Measurement

Technology TSMC 0.25-um 1P5M

Chip area 2452umx1112um

Power Supply 1V

RF frequency 2.4-GHz

IF frequency 10MHz

S11 -20dB -19dB

Conversion gain 18dB 15dB

Noise Figure 8.2dB 17dB

VCO tuning range 2.38~2.60 GHz 2.74~2.93 GHz

VCO gain 220MHz/V 190MHz/V

Image rejection ratio 47dB 41dB

IIP3 -13dBm -15dBm

Power consumption VDD@1V

LNA 3.17mW 3.9mW

QVCO 9.76mW 11.175mW

QMIXER 0.9mW 0.9mW

PF & BUFFER 1.6344mW 2.6mW

OVERALL 14.56mW 18.575mW

Table 3.2 Final summaries of measurement results

Table 3.3 lists a performance comparison between measured results and bluetooth specifications.

Table 3.4 compares the designed receiver with a similar art [12]. The paper consumed most of power due to its passive RC polyphase filter network.

Measurement Requrement

Noise Figure 17dB <32dB

Image rejection ratio 41dB >20dB

IIP3 -15dBm >-16.5dBm

LO leakage -60dBm -47dBm

Table 3.3 Measured performances compared with Bluetooth specifications

This receiver Ref.[12]

Technology 0.25um 0.25um

Power supply 1V 1.5V

RF frequency 2.4GHz 1.8GHz

S11 -19dB -11.5dB

Noise Figure 17dB 8.2dB

Image rejection ratio 41dB 32.2dB

LO leakage -60dBm -83dBm

Power consumption 18.575mW 113mW

Table 3.4 Receiver comparisons with another quadrature-designed receiver

CHPATER 4 CONCLUSIONS AND FUTURE WORKS

CHAPTER 4

CONCLUSIONS AND FUTURE WORKS

4.1 CONCLUSIONS

The Low-IF receiver front-end with body-biased low-noise amplifier and integrated polyphase filter is designed, fabricated and measured. The receiver testchip comprises low-noise amplifier with body-bias, quadrature VCO, quadrature mixer, polyphase filter and an output buffer. The receiver testchip is fabricated by TSMC 0.25-um process and measurement results have been presented in this thesis. The receiver testchip occupy 2.7mm² area.

A new proposed LNA with body-bias voltage has been implemented in this design. The body-bias decreases the threshold voltage to improve the operating headroom. The body-bias applies to LNA input cascode stage and gains the best performance of gain and linearity.

The VCO's frequency is about higher than simulation results due to the parasitic capacitance not accurate to be modeled. The active polyphase filter has implemented in last stage. Its image rejection is perform to reject image about 30-dB. An active polyphase filter is also design in this testchip. To compare with RC network polyphase filter, the active polyphase filer transfer the desired signal without loss, occupy small area and lower power consumption.

The overall receiver chip with low-IF architecture is proven working well at 1-V supply, 27-dB noise figure, -27-dBm IIP3 ,lower than -55dBm LO leakage and 22mW power consumption.

4.2 FUTURE WORKS

A 1-V 2.4-GHz Low-IF receiver is successfully fabricated with several important key components. They are a LNA, a quadrature VCO and a quadrature mixer and a low-voltage active polyphase filter. A robust and compensation circuit should be used to reduce the affection by process and power and temperature variation.

A LNA circuit is implemented with body-bias scheme to improve its

performance. It is silicon prove by this testchip. Besides, it can be researched that the other key components can also implement by body-bias to further improve the performance of low-voltage design.

A low-voltage active polyphase filter is implement in this receiver; The stable and accurate bias is needed. The designed polyphase filter is very sensitive to power supply, process and temperature variation so that the image rejection ratio may fall in a large range. The gm-bias can be considered to overcome process variation.

The LO frequency decide the frequency band of the receiver. As the measurement results, the measured quadrature VCO frequency is higher than simulation frequency. It can be fine tuned by flexible varactor switch or metal option. The parasitic resistance and capacitor should be further considered.

REFERENCES

REFERENCES

[1] Bluetooth Specification Version 1.0B

[2] Behzad Razavi, RF Microelectronics. Prentice Hall

[3] Derek K. Shaeffer and Thomas H. Lee, “The Design and Implementation of

Low-Power CMOS Radio Receivers”, Kluwer Academic Publishers.

[4] Chung-Yun Chou and Chung-Yu Wu, “The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications”,

The 2002 Asia-Pacific Conference on Circuits and Systems, Vol. 1, pp.241-244,

Oct. 2002.

[5] Chung-Yu Wu and Chung-Yun Chou, ”A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator”, IEEE Journal of

Solid-State Circuits, Vol. 39, Issue3, pp.519-521, March 2004

[6] E. Zencir, N.S. Dogan, E. Arvas, ”A low-power CMOS mixer for low-IF receivers”, The 2002 IEEE Radio and Wireless Conference, pp.157-160, Aug.

2002.

[7] F. Beffa, R. Vogt, W. Bachtold, E. Zellweger, U. Lott, “A 6.5-mW receiver front-end for Bluetooth in 0.18-µm CMOS”, IEEE Radio Frequency Integrated

Circuits RFIC Symposium, pp.391-394, June 2002

[8] Chung-Yu Wu and Hong-Sing Kao, ”A 1.8 GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure”, Proceedings of the 1998 IEEE International Symposium on Circuits

and Systems, Vol. 4, pp.378-381, June 1998

[9]A.N.L. Chan, K.W.H. Ng, J.M.C. Wong, H.C. Luong, “A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application”, IEEE International Symposium on

Circuits and Systems, Vol. 4, pp.454-457, May 2001

[10] H. Darabi, S. Khorram, Hung-Ming Chien, Meng-An Pan, S.Wu, S. Moloudi, J.C.

Leete, J.J. Rael, M. Syed, R. Lee, B. Ibrahim, M. Rofougaran, A. Rofougaran, “A 2.4-GHz CMOS transceiver for Bluetooth”, IEEE Journal of Solid-State Circuits, Vol.36, Issue 12, pp.2016-2024, Dec. 2001

[11] H. Komurasaki, H. Sato, N. Sasaki, K.Ueda, S. Maeda, Y. Yamaguchi, T. Miki,

“A sub 1-V SOI CMOS low noise amplifier for L-band applications”, Radio

Frequency Integrated Circuits (RFIC) Symposium, pp.153-156, June 1998

[12] M. S. J. Steyaert, B. De Muer, P. Leroux, M. Borremans and K. Mertens,

“Low-voltage low-power CMOS-RF transceiver design”, IEEE Transactions on Microwave Theory and Techniques, Vol.50, Issue.1, pp.281-287, Jan. 2002.

[13] Chung-Yu Wu and Hong-Shin Kao, “A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications ”, IEEE Transactions on

Circuits and Systems, Vol. 49, Issue 2, pp.123-134, Feb. 2002.

[14] T. Taris, J.B. Begueret, H. LapuyadeH, Y. Deval, “A 0.9V body effect feedback 2 GHz low noise amplifier “, Conference on European Solid-State Circuits, pp.659- 662. 2003.

[15] Bo-shih Huang, “A 1-V 2.4-GHz CMOS RF Receiver Front-End with Double-Quadrature Architecture “, The thesis of institute and Department of electro

physics in National Chiao Tung University, 2002.

REFERENCES

自 傳

吳瑞仁於西元 1972 年 9 月 21 日在台北縣出生。父吳榮武，母吳蕭秀鳯，

家有一個姊姊及一個哥哥，妻黃玉萍，育有一女吳予薰。

西元 1996 年畢業於國立雲林技術學院電子工程技術系，獲學士學位。西 元 2004 年畢業於國立交通大學電機資訊學院電子與光電學程碩士班，獲碩士學 位。

研究所修習課程

類比積體電路(I)(II) 吳重雨 教授

高等超大型積體電路設計 李鎮宜 教授

行動與室內無線通訊 黃家齊 教授

數位訊號處理 張文鐘 教授

數位積體電路 吳錦川 教授

個人通訊 林一平 教授

記憶體積體電路設計 吳錦川 教授

在文檔中 具有基體偏壓之低雜訊放大器及整合型多相位濾波器之1-V 2.4-GHz低中頻架構前端接收器電路設計 (頁 76-0)