CHAPTER 2 CIRCUIT ARCHITECTURE AND SIMULATION
2.5 SIMULATION RESULT
The receiver chip is simulated by HSPICE. Post-simulation is completed by HSPICE with spice model of TSMC .25-um 1P5M process. This section presents the post-simulation results of all circuit constructing the receiver.
A. Low noise amplifier
LNA is the first stage of the receiver; it provides input matching, voltage gain and low noise contribution for the receiver. Fig. 2.31 and Fig. 2.32 show the simulated input matching (S11) lower than –20dB and voltage gain higher than 20dB, respectively.
Frequency (Herz)
Gain (dB)
FF FS TT SF SS
Frequency (Herz)
Gain (dB)
FF FS TT SF SS
Fig. 2.35 simulated voltage gain of the LNA
This fig.2.35 shows the dependence of gain due to process variation. The gain is about 12dB in worst case SS corner simulation. The gain of LNA can guarantee at least larger than 10dB for five corner simulation and meet the specification.
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
Fig. 2.36 The simulated input matching (S11) of the receiver
The Fig.2.36 shows the body bias sweep from 0.3V to 0.6V, the input matching (S11) of LNA can guarantee smaller than -12-dB.
(a)
Fig. 2.37 (a) LNA P-1dB HSPICE simulation result.
(b) redesign the LNA gain to 6dB, P-1dB can be improved to -5.5dBm
-10dBm
body bias and linearity
-14
body bias (V)
linearity (dBm)
P1dB@VBLNA=0.5V
Fig. 2.38 LNA noise figure SpectreRF simulation [email protected]
This work
Simulation results
Reference paper Experimental results with body bias w/o bulk bias
(same device size*)
Active body type LNA[11]
Body effect feedback[14]
Technology 0.25um bulk 0.25um bulk 0.35um SOI 0.18 bulk
Frequency 2.4GHz 2.4GHz 1.9GHz 1.65~2.5GHz
Bulk voltage 0.5V VBS=0V 0.5V 0.6V
Supply Voltage 1V 1V 1V 0.9V
Power
Consumption 3.17mA 3.5mA 5mA 2.5mA
S11 -20dB -20dB - -
Gain 20.2dB 16dB 7dB 10dB
NF 2.02dB 3dB 5.6dB 1.34dB
P-1dB -10dBm -13dBm -4.5dBm -16dBm
Table 2.5 The comparison between w/o body bias, w/i body bias.and reference paper
The comparison between w/o body bias, w/i body bias.and reference paper is listed in table 2.5. The main advantages of body biased LNA are gain and linearity for low power supply design [11].
1. Gain improvement
2. 1-dB compression point improvement
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
The body of the transistor is connected to its gate. The threshold voltage of the transistor becomes smaller due to body effect so that a large drain current is obtained which keeps the gain high even at a low supply voltage. An added feature of connection between the body and the gate is the high 1-dB compression point. This is because the transistor can drive large load
capacitance with a larger RFsignal input due to the active threshold voltage of the body control.
B. Quadrature Voltage control oscillator
The tuning range of VCO is shown in Fig. 2.33. The quadrature VCO oscillates 2376MHz~2639MHz by control voltage (VCOBIAS) from 0V to 1V
Fig. 2.39 The simulated tuning range of VCO
B. Quadrature downconverter mixer
The RF input, LNA output, quadrature VCO output , mixer I/Q IF output waveform are shown in Fig. 2.34. Low noise amplifier amplifies the input signal to the receiver. The voltage gain of LNA is about 20-dB. The simulated waveform is shown in Fig. 2.34(a). The quadrature voltage-controlled oscillator provides I/Q signal and mixes with LNA output. The quadrature VCO I/Q signal is shown in Fig. 2.34(b). The quadrature downconverter mixer down converts the RF signal to I/Q IF signal. The terminal of mixer output is IP, IN, QP, QN, separately.
Fig. 2.40 Mixer noise figure SpectreRF simulation NF=8dB@10MHz
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
Fig. 2.41 The transient analysis of downconverter (a) input and output of LNA (b) I/Q signal of quadrature VCO (c) output waveform of downconverter
C. Active polyphase filter
The polyphase filter is used to buffer the desired signal and reject the image signal. The simulated frequency response of polyphase filter is shown in Fig. 2.35.
The image rejection ratio is greater than 60-dB. In order to expand the frequency band, the four-stage polyphase filter is used. The required band is about
5MHz~10MHz. For 1-stage polyphase filter, the ideal equation are
o
Four poles is located at 13.26MHz, 10.62MHz, 8.85MHz, 7.07MHz. To map the ideal transfer curve and simulation results.
Fig. 2.42 The frequency response of polyphase filter
CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS
The frequency response of polyphase filter can be shown in Fig. 2.42.
p MHz k
fp RC 2.76
6 . 3 6 . 3 2
1 2
1 =
⋅
= ⋅
= π π
Fig. 2.43 The input stage HP filter
Technology 0.25um Power supply 1V
Gain in Bandwidth 6dB (5MHz~13MHz) THD -40dB IRR >60dB Power consumption 1.6344mW
Table 2.6 The performance summary of polyphse filter
Fig. 2.42 illustrates the input bias stage. It becomes a HP filter in each stage input. The gain degrade can be observed in Fig.2.42 at low frequency.
Table 2.6 summarizes the results of the simulation results of the polyphase filter. The image rejection exceeds 60dB over the range 5MHz to 13MHz. The THD (Total harmonic distortion) is -40dB when 10MHz, 100mV signal is applied.
The power consumption of polyphase filter is 1.6344mW.
C. The receiver analysis
The bluetooth required the gain greater than 10-dB in this receiver front-end.
The design of receiver must assigned to get enough noise figure and gain. Table 2.7 listed the gain and noise figure assignments in this receiver front-end system.
The spectrum of receiver is shown in Fig. 2.36. The following example is a 2.4-GHz input and 10-MHz output frequency spectrum. The output is split to two signals I/Q with 90-degree difference phase.
Stage LNA Mixer Polyphase filter Output buffer all
Gain 18dB -4dB 6dB -6dB 12dB
NF 2.03dB 8dB 8dB 6dB 8.2dB
Table 2.7 The gain and noise figure assignment
Fig. 2.44 The spectrum analysis of receiver
The noise figure of receiver is simulated by SpectreRF and shown in Fig.
2.45. The NF is equal to 8.8dB at 10MHz IF freqneycy.
Fig. 2.45 Output noise spectral density for receiver NF=8.2dB@10MHz
QVCO output(dB)
2410-MHz Homonic
Mixe output(dB)
10-MHz
CHPATER 3 EXPERIMENTAL RESULTS
CHAPTER 3
EXPERIMENT RESULTS
This chapter presents the chip layout, testing environment setting and experimental results. It also discussed and compared with post-simulation results regarding the measurement results
3.1 Layout Description
This receiver testchip can be divided in four parts. They are a Low-Noise amplifier, a quadrature VCO, a quadrature mixer, a polyphase filter with output buffer. The receiver layout and chip floorplan is shown in Fig. 3.1. The die photograph is shown in Fig. 3.2.
All the NMOS devices are placed on deep N-WELL (DNW), which is called R-WELL (RW) supported by TSMC 0.25-um technology. The external DNW drawing layer and mask must be used in this layout to define the RW region. The deep N-WELL isolates the NMOS to other device within the R-WELL. It can reduce the NMOS body-effect. For body-bias LNA, the NMOS bulk terminal can be biased to an independent power.
The guard ring surrounds each MOS device to avoid the substrate noise and signal couple. It also used to prevent the latch-up issue caused by parasitic SCR circuit for large MOS devices. The dummy POLY and dummy OD is usually inserted to reduce the side effect of process etching. The dummy metal is added in the top of layout, the dummy metal occupies large area. It is used to improve the metal density and to overcome the DRC density violation. To improve the metal
CMP process window, it must fill the dummy metal uniformly even if the originally drawn has already met the density rule. The dummy metal can be also worked as power line simultaneously.
The widely used on-chip inductor is spiral inductor. All spiral inductor must keep proper distance with the others and core circuit to prevent mutual inductance and disturbance on circuit. The source of spiral inductor layout cell is from
TSMC’s RF design library. The cell library is silicon proven and the measurement data is collected in SPICE model document for our reference.
The input resistance is an important key to contribute for noise figure. In order to reduce the input resistance, the LNA block is close to RF input to minimize input resistance. The LNA circuit is fully differential configuration, four-inductor belong to LNA are located surround with the NMOS devices and made them symmetrically as far as possible. Dummy gate and dummy resistors are equipped with every MOS device and resistor respectively to cope with process variation. The body of LNA NMOS input stage is connected to a bias voltage used to control its body bias voltage.
The chip floorplan must consider the optimum signal flow path. It should be as short as possible in metal routing and alleviate transmission line effect
especially for high frequency. The mixer places on the middle of the receiver chip.
It accepts LO signal from left side and LNA amplified RF signal from the bottom side of the chip. The mixer output transfer to right side and input into polyphase filter then to the output buffer. It can be observed that MIM capacitances occupy large area in polyphase region.
The fully receiver chip layout is shown in Fig 3.1 in the next page.
CHPATER 3 EXPERIMENTAL RESULTS
Fig. 3.1 The receiver chip layout
3.2 Testing Description
The receiver chip is a bare dies and needs to bond on a bonding board because it is more complicated for parasitic RC and inductance to place the chip on package. The purpose of testing board is to route the die pad to the testing equipments. The routing must be as short as possible to eliminate the parasitic RLC effect. The photograph of receiver chip and the bonding boards are shown in Fig. 3.2 and Fig. 3.3.
The input and output terminal are differential so that it needs external components like as balun and transformers for RF input and IF output in the measurement. The RF input signal flows into a balun and split the single-end RF signal to differential RF signal into receiver testchip. The receiver IF outputs are IP, IN, QP, QN, separately. Their DC signal is blocked by a 3uf block capacitance and drive to output by transformer.
The baluns with part number BL2012-10B2450 are made by Advanced Ceramic X Corporation. The transformers with module number ADT2-1T are made by Minicircuits. Signal attenuation caused by the baluns and transformers are measured for compensating back to relative apparent performance.The signal attenuation caused by transmission line should be considered and need to
compensate back according to the measurement results.
The inductance variation of bond-wire and parasitic capacitance may affect the performance of input matching (S11). It is compensated by an off-chip parallel capacitance and fine-tunes the transmission line inductance. The bias voltage is fed by an external pin and can be flexible adjustment.
CHPATER 3 EXPERIMENTAL RESULTS
Fig. 3.2. Die photograph and receiver chip floorplan
Fig. 3.3 Bonding board for the receiver
CHPATER 3 EXPERIMENTAL RESULTS
3.3 Measurement Setup
As shown in Fig. 3.4, the testing board is integrated in an individual DC boards for the testchip measurement. All the supply and bias voltage should parallel a large capacitor to provide a stable power voltage.
The test platform for receiver is shown in Fig. 3.4. The bonding board plugs in the DC board for testing. The DC board drag out pin of bonding board and it connect to power supply and bias voltage.
The standard measurement setup of receiver chip is shown in Fig. 3.5. A signal generator generates RF input to the balun, which split the RF single-end input to differential input to receiver chip of LNA. There are many power bias can be applied to the receiver chip. The power bias fed to the receiver chip and can be adjusted according to circuit’s operating point. The input bias of balun can set the input DC bias to bias the LNA input stage. The terminal of LNA input parallels a 1pf capacitance to fine-tune the performance of input matching.
The testing items need various instruments for measurement, for example, S-parameter analysis requires a network analyzer, spectrum analysis requires a signal generator and spectrum analyzer; noise analysis requires a noise source and a noise analyzer; linearity analysis (two-tone test) require two signal generator, a power splitter, a spectrum analyzer, and a waveform analysis, etc. This section introduces the measurement setup and the methodology.
Fig. 3.4 test platform for receiver
cm
CHPATER 3 EXPERIMENTAL RESULTS
A measurement environments setup of receiver chip is shown in Fig. 3.5.
The signal generator provides the desired signal input to the receiver. The spectrum analyzer used to measure down converted IF spectrum to analyze the performance of conversion gains and the potential regarding the internal leakage.
The linearity of a receiver system is a important parameter. The linearity analysis (two tone test) measurement setup is shown in Fig. 3.6. Two signal generators applied to generate two signals with different frequency to input into power splitter. The power splitter combines two tones and transfers into the
receiver chip. The receiver down converts and generate first and third order output spectrum to be measured.
frequency level
Fig. 3.5 The measurement setup of receiver chip
Receiver Chip
Fig. 3.6 IIP3 and conversion gain measurement setup
3.4 Experimental results
The receiver testchip has several components totally consumes about 18.575-mW DC power. The measurement data is slightly greater than the post-simulation results. The root cause is inferred that process corner variation. The supply voltage is 1-V to affect an inaccurate power consumption simulation results. The device current and power consumption can be evaluated by corner simulation.
The measurement DC bias condition is adjusted and it does the effort to get the best performance for the receiver testchip. After adjusts the bias DC operation point, the performance of receiver can be further close to the target of
specification. The DC bias conditions are listed in table 3.1.
Receiver Chip
RF input IF output
External matchi ng compensation
RF input IF output
External matchi ng compensation
DC Block
Fig. 3.7 bias conditions
BIAS CONDITION DESCRIPTION Volt
RFBIAS
RF input bias 0.6VBLNA
LNA body-bias 0.4VBMXRF
MIXER input bias 0.6VBVCO
VCO frequency control bias 0~1VBFT
Polyphase filter input bias 0.6Table 3.1 DC bias tables
CHPATER 3 EXPERIMENTAL RESULTS
The input terminal parallels 1pF capacitance and adjusted the transmission line to compensate the performance of input matching (S11). The bond-wire inductance is estimated to have approximately maximum 3.2-nH variation. The input matching is compensated with 2.7-GHz, because the VCO frequency is shift up to 2.7-GHz. The input measurement of receiver input matching results is shown in Fig. 3.8. The receiver performs S11 better than –20-dB in band.
Fig. 3.8 The input matching (S11) of receiver
Fig. 3.9 The receiver output spectrum
The measurement of output spectrum is shown in Fig. 3.9, Markers 1~3 denote RF feedthrough, LO leakage and desired IF signal. The frequency of desired signal is 9.93-MHz. It is downconverted by mixing RF input and LO I/Q signal. RF feedthrough is about –55-dBm appears due to mixer mismatch and substrate couple. It cannot be simulated and is not predictable from an exact consideration by HSPICE simulation. LO leakage appears causes from similarly with RF feedthrough. The measured quantity of spurious emission such as RF feedthrough and LO leakage must satisfy the bluetooth specification.
To consider the loss of the external components and buffer loss, the gain of receiver must be compensated back and it performs over 7-dB gain in band.
CHPATER 3 EXPERIMENTAL RESULTS
Center 11.39468139 MHz 1.704099837 MHz/ Span 17.04099837 MHz RBW 500 kHz
Fig. 3.10 Output spectrum of IF signal
Ref Lvl
Center 2.7 GHz 32.95702379 MHz/ Span 329.5702379 MHz
-110
Fig. 3.11 The spectrum of LO leakage
VCO tunning range
2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20
0 0.2 0.4 0.6 0.8 1 1.2
VBVCO
frequency
VDDVCO=1V VDDVCO=1.2V VDDVCO=1.5V simulation
Fig. 3.12 The tuning range of VCO
Fig.3.10 shows the output spectrums of IF signal. The signal is in 10MHz IF band. The input power is -45-dBm. We can get the output power is -47.36dBm and IF frequency is 9.96-MHz. To compensate with 1.5-dB balun loss, 0.5-dB transformer loss and 8-dB PC board loss, and 6-dB output buffer loss. The receiver performs over 15-dB gain in band.
VCO tuning range can be analyzed by LO leakage observed on spectrum.
Fig.3.11 shows the LO leakage spectrum in output terminal. The Fig.3.12 shows the plot of VCO tuning range. The oscillation frequency can be tuned from 2.74~2.93 GHz under tuning voltage 0V ~ 1V. The VCO gain is 190MHz/V. The Smaller capacitance of MOS varactor estimate in model causes the measured frequency shift up about 300MHz with the post-simulation result.
CHPATER 3 EXPERIMENTAL RESULTS
Fig. 3.13 Output spectrum of two-tone test.
-80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00
-40 -35 -30 -25 -20 -15 -10
Input Power (dBm)
Output Power (dBm)
Measurement:1st order Measurement: 3rd order post-sim:1st order post-sim: 3rd order
-80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00
-40 -35 -30 -25 -20 -15 -10
Input Power (dBm)
Output Power (dBm)
Measurement:1st order Measurement: 3rd order post-sim:1st order post-sim: 3rd order
Fig. 3.14 Two-tone-test plot for IIP3
Fig 3.13 shows an output spectrum of two-tone test, where 1st-order and 3rd -order intermodulation signals are obvious. Fig 3.14 plots output-to-input power
relations. Compensate back with loss of external components. The measured receiver performs linearity of -15-dBm IIP3.
Noise figure is an indirect specification to adjust if a receiver contributes sufficiently low noise. Bluetooth requires SNR(signal to noise ration) higher than 12-dB to archive 0.1% BER(bit error rate). Noise figure is defined as ration of input SNR to output SNR. Minimum input SNR can be calculated as
Bluetooth requires SNR higher than 12-dB to achive 0.1% BER SNRinput.miin(dB)=sensitivity - channel bandwidth - Noise Floor =(-70) - 10log(10^6) - (-174) = 44dB
Nfmax(dB)=SNRinpu.min - SNRoutput.min = 44-12=32dB
Noise performance of the tested receiver is 15-dB. It is satisfies the
bluetooth requirement. HSPICE cannot simulate noise figure if a circuit involves frequency conversion so simulated noise figure is absent in this paper. But the LNA dominates total noise performance. A receiver can perform satisfied noise figure with a well designed LNA.
CHPATER 3 EXPERIMENTAL RESULTS
Fig. 3.15 The receiver gain with difference body-bias
receiver gain vs body bias
10 10.5 11 11.5 12 12.5 13 13.5
0 0.1 0.2 0.3 0.4 0.5 0.6
Body bias (V)
Gain (dB)
post-sim measurement
To fine-tune the body-biased LNA can adjust the gain of receiver. Fig.3.15 shows the receiver gain with difference body-bias. The measurement result shows the body-bias method improved about 2-dB gain. If the body-bias voltage rises over 0.6V, the forward PN junction current is turned on and the bias supply current injection into the bulk. It is observed the gain of receiver is degraded.
Fig. 3.16 and Fig.3.17 shows the receiver gain and its image rejection capability. The IF frequency is about 10-MHz. the receiver has 15-dB conversion gain. It compensate with the balun, transformer and output buffer loss, similarly.
The operating band is 9-MHz~11-MHz. The can get 41-dB image rejection ratio at 10-MHz. The minimum IRR is 36.8-dB in IF band. It is also meet the bluetooth requirement.
conversion gain
-35.00 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 5.00 10.00 15.00
0 5 10 15 20 25
frequency(MHz)
conversion gain(dB)
desired sim desired meas
Fig. 3.16 The performance of receiver gain.
convers ion gain
-40.00 -30.00 -20.00 -10.00 0.00 10.00 20.00 30.00
0 5 10 15 20 25
IF f requency(MHz)
Conversion gain(dB)
desired sim img sim desired meas img meas IRR=38dB IRR=36.5dB
Fig. 3.17 The performance of image rejection
CHPATER 3 EXPERIMENTAL RESULTS
Table 3.2 lists the summary of the tested receiver, it comparison between post-simulation and measurement results. The gain in measurement is
compensated with 1.5-dB balun loss, 0.5-dB transformer loss and 6-dB buffer loss.
The measured gain and IIP3 after from the post-simulation due to the
The measured gain and IIP3 after from the post-simulation due to the