Thesis organization

In this chapter, the thesis discussed about the principle of different receiver architecture and their advantages and disadvantages. In the next chapter, chapter 2, it presents the design of receiver components in detail and their design

considerations. Each component is divided to several sub sections and discussed the features and design considerations separately. The algorithm of image-reject process is also analyzed in this chapter. The implementation method and post-simulation results is completed. Chapter 3 contains experimental results and discussions. The measurement setup and environment is also introduced. Finally, conclusions and future works are described in chapter 4.

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

CHAPTER 2

CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

2.1 SYSTEM ARCHITECTURE

Quadrature VCO

POLYPHASE FILTER OUTPUT BUFFER

LNA

IOP ION

QOP QON LNAIP

LNAIN

t cosω_LO

t sinω_LO

I

Q

Fig. 2.1 System architecture

The block diagram of Low-IF receiver system architecture is shown in Fig.

2.1. The receiver architecture includes a low noise amplifier, quadrature VCO, quadrature mixer, polyphase filter, and an output buffer in the last stage.

LNA provides a high gain but low noise figure to amplify the RF signal. It amplifies the desired signal and suppresses noise interference. LNA also provides a 50Ω input matching for antenna and transmission line. The LNA is the frist stage of receiver system. It plays an important role on noise figure for whole receiver system. The LNA output transfers RF signal to next stage. The quadratuere mixer used to down-converts the RF signal to IF signal.

A quadrature VCO generates LO signals with 90-phase difference. As shown in Fig. 2.2, the quadrature LO signal is used to mixes with RF signal to generate IF I/Q signal.

The quadrature mixer stage follows the LNA. The quadrature mixer mixes RF signal and quadrature LO signals. The quadrature mixer is used to down-converts RF band to IF band and splits the IF band to I/Q phase difference. The mismatch of VCO and mixer can degrade the image rejection ratio.

Polyphase filter and output buffer is a complex filter in the last stage, which follows the RF mixer, used to suppress the image signal and employ a common source buffer to transfer the desired signal in IF band. The desired and image signals can be distinguished in phase relation and double-ended spectrum. The polyphase filter generally can be easily realized by passive R-C polyphase network. The main disadvantage is the signal loose. The receiver in this design used an active polyphase filter to solve the image signal and improve the linearity.

The common source output buffer must consider the linearity and used to drive the output load. It provides enough output power to drive the output capacitance and eliminate output loss as far as possible.

Layout and design strategies are considered to achieve high performance and image rejection ratio in this architecture. The whole chip floorplan, mismatch, The symmetry of differential circuit, robust power line, and signal transmission line are the key points to eliminate the ill effect in layout.

2.2 OPERATIONAL PRINCIPLE

This section describes the principle of the receiver, it presents how the receiver down-converts RF band signal to IF band signal. It also shows the image cancellation methodology.

The typical function of downcoversion is to do a multiplication operation. It assumes the RF signal is and the LO signal is . To multiply these two signal and input to an analog multiplier. Then the mixer generates an IF frequency

t j _RF

e^ω e^jωLOt

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

LO

RF

ω

ω

− . i.e.

ω

_IF =

ω

_RF −

ω

_LO. The following are the mathematical

representations with an assumption of

ω

_RF >

ω

_LO, to multiply the RF and LO signal with exponential equation (1).

t

It is an easy way to expand the equation by Eulers’s formula, exponential function and Euler’s formula act as an important role on the discussion of complex signal. After the Eulers’s formula transformation, the operation of mixer operation can be rewritten as follow.

( ) ( )

From the equation (2), Quadrature RF signal is multiplied with quadrature LO signal. The procedure generates quadrature IF signal on the output terminal of I-channel and Q-channel. I-channel corresponds to the real part of complex signal and Q-channel corresponds to the imaginary one. I-channel and Q-channel are always with 90-degree phase difference in an identical frequency.

The operation of signal multiplication in frequency domain depicts on Fig.

2.2. The equation (1) and (2) can be described and signify in block function diagram, which is shown in Fig. 2.3.

Fig. 2.2 Operation of downconversion

90

^o

LO I

Q RF

Fig. 2.3 IF quadrature I/Q signal generator

It presented how the equation (2) to be implemented in frequency domain.

The quadrature VCO applies I/Q quadrature LO signal with 90-degree phase difference and multiplied with RF input signal. The LO quadrature signal can be denoted to cos

ω

_LO

t

and sin

ω

_LO

t

. The operation of Low-IF block diagram is shown in Fig. 2.4.

Quadrature LNA VCO

LNAIP LNAIN

t cos ω

_LO

t sin ω

_LO

I

Q Fig. 2.4 Low-IF quadrature downconverter

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

Image-reject process.

If there exist an image signal , the image frequency has the same frequency. After down-conversion processing, it can be denoted by

t frequency. The below mathematical equation representations the image signal mixes the LO signal with an assumption of

ω

_IM <

ω

_LO,

By Euler’s formula, the down-conversion procedure can be rewritten as.

( ) ( )

The signal mixing procedure generates quadrature IF signal on the output terminal of I-channel and Q-channel. The output IF frequency is

ω

_IF. The frequency is similar to

ω

_RF signal mixes with LO signal, which is represented in previous equation (2). Image IF signal contains negative sine function on Q-channel. It should be known that a quadrature image rejection filter must distinguish the desired signal

ω

_RF and undesired image signal

ω

_IM by complex filter. The polyphase filter is usually implement to act as the complex filter to reject the image signal.

2.3 CIRCUIT DESIGN

2.3.1 Body-biased low noise amplifier (LNA)

Low noise amplifier (LNA) is the first stage of the receiver system. The architecture of LNA proposed in this thesis is inductive source degeneration with body-bias scheme. In order to operate at 1-V power supply, the body-bias is applied in cascode input stage. The body-bias is used to improve the voltage headroom, linearity and noise factor.

The performance of the LNA is optimized by properly choosing the size of the input and cascade transistors. This strategy can also minimizes noise as possible as for the system.

There are several common goals in design of LNA. These include input impedance matching, higher power gain, minimizing the noise figure, sufficient linearity, and small power consumption. Otherwise, it also provides 50Ω input matching for antenna input.

A. Body-biased design

In order to decrease the threshold voltage of cascade input devices and improve the operation headroom, body-bias voltage is implemented in the LNA design. The body-bias must be supplied in terminal of NMOS bulk that is

separated from other NMOS devices. TSMC 0.25um provides an effective method to separate the NMOS substrate that is deep N-well process. The P-well in DEEP NWELL is called RW. It isolates the P-well from other NMOS devices. That not only cancels the NMOS body effect but also the body-bias supplied to the terminal of NMOS bulk independently. The Fig. 2.11 illustrates how the single end cascode NMOS place on deep N-well with body-bias circuit. Fig. 2.5 illustrates the cross section of the LNA input cascade stage. The junction model of MOS device is not

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

well defined. We must pay attention to the design guard band and sensitive to process variation.

Ls MN1 LNAIN

MN2

VBLNA Ld

Deep NWELL

Fig. 2.5 Single end cascode NMOS place on Deep N-well with body-bias

N-well N-well

Deep N-well

N+ N+ N+ N+

P+ P+ P+

LNAIP VBLNA

RW Positive bias

P-sub

Fig. 2.6 Cross section of cascode NMOS place on deep N-well

Shown in Fig. 2.6, it provides a positive body-bias (VBLNA) voltage to the terminal of NMOS bulk. Then a forward parasitic PN junction will be created. It generates a forward current when the body-bias (VBLNA) greater than the PN junction on voltage. A forward current induced into source or drain of the NMOS.

This causes the NMOS input stage operation point shift. For this reason, the gain of LNA will be degraded. The top curve of Fig. 2.7 shows the threshold voltage

decrease if VBLNA increase. The bottom curve of Fig. 2.7 shows the IBS forward current is created if the forward VBS voltage VBLNA greater than about 0.7V.

Fig. 2.7 The deviation of threshold voltage and forward current

I

B(uA) Forward current

Vblna=0.7V

vblna vblna

Forward current Vblna=0.7V

I

B(uA)

Threshold Voltage(V) Threshold Voltage(V)

The drain current of MOSFET is where K and Vth ater the gain factor and the threshold voltage, respectively. In order to obtain a large gain, the current increased. However, the supply voltage is lowered, the drain current is limited. The body of the transistor is connected to the bias voltage.

The Vth of the transistor is

Id

Id =K(V_GS −Vth)²

[

F

V

BS F

]

Vtho

Vth

= +

γ

2

φ

− − 2

φ

, where Vtho is

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

the threshold voltage for body-source voltage, VBS=0V, γ is body-effect coefficient,

φ

_F is the bulk potential. As the gate-source voltage (VGS) must be not less than 0V. The threshold voltage becomes smaller due to the body biased effect and this leads to a larger drain current. The transconductance factor (gm) of the body-biased LNA is larger than conventional LNA. The ratio of the gm to gm0, which is the transconductance factor when the body biased at the source, is

[ ]

B) Too large forward

bias

VBLNA (body bias: V)

Fig. 2.8 body-bias voltage vs. LNA gain

Fig. 2.8 shows the gain of LNA increase if VBLNA increase. The junction forward current destroys the DC operating point of input stage devices and it further decrease the gain of LNA. From the transfer curve of LNA gain with sweep the bias voltage, the best body-bias (VBLNA) is about the range from 0.4V to 0.6V. If The VBLNA greater than 0.6-V will cause the gain of LNA decrease.

Fig. 2.9 illustrates the frequency response of LNA with difference body-bias voltage.

VBLNA 0.6V 0.4V 0.2V 0V

LNA Gain

Fig. 2.9 LNA gain with difference body-bias

Frequency

B. Input matching

There are four kinds of common architectures used in input matching of LNA. Fig.2.2 illustrates four kinds of input matching circuit. They are resistive termination, 1/gm termination, shunt-series feedback and inductive degeneration.

Illustrate in Fig. 2.10(a), The resistance termination shunt with input port to provide a 50Ω resistance. The use of real resistor has a poor noise figure. The resistor in this fashion has a deleterious effect on LNA’s noise figure. A second The NF of 1/gm termination is usually larger than 3dB. Shunt-series feedback needs on-chip resistors of reasonable quality. It also often has higher power to provide high gain. The shunt-series feedback approach is not suitable for this work.

The inductive degeneration usually has best quality and small noise in this LNA design.

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

Zin

Zin

Zin Zin

(a) (b) (d) (e)

Fig. 2.10 (a) Resistive termination (b) 1/gm termination (c) shunt-series feedback (d) inductive degeneration

Fig. 2.11 is the input stage equivalent circuit of source degeneration cascode low noise amplifier.

Ls

Fig. 2.11 The small signal model of Input impendence matching

To simplify the analysis, we consider the device model that expands to the equivalent circuit of small signal. It is illustrated in right side of the fig. 2.2. It can be show that the input impedance of the circuit is shown as follow:

G

At the resonate frequency, that is Zin(i)=0 then

1 0

Alternately,

Cgs Lg Ls f_o

o ( )

2 1

= +

=

π

ω

₍₇₎

From this equation, to evaluate can get the Lg value.

in the real part of Zin, Zin(r)=50Ω

Ω

=

=

⎟⎟⋅

⎠

⎜⎜ ⎞

⎝

=⎛ Ls Ls 50

Cgs

Zin gm ω_t (8)

Ls value can be evaluated from this equation.

Replace the gm/Cgs with mos cut-off frequency, i.e.

Cgs ft

=

gm

W K

Cgs

= ′⋅ (9)

From this equation, we can see the Zin=50 are related to the mos cut-off frequency.

The parasitic of a output pad and bond-wire loading are modeled by a

resistance series an inductor and parallel a PAD capacitance; the PAD capacitance is connected to substrate. This model is illustrated in Fig. 2.12. The bond-wire impendence also compensates the input impedance to fit the 50Ω matching. After adjust the bond-wire inductance and capacitance, The low-noise amplifier has best S11 performance.

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

Rbw Lbw

Cpad

Subtrate

=

Fig. 2.12 Parasitic circuit model of a pad capacitance and bond-wire

C. Voltage gain and linearity

For LNA design, Linearity and gain are usually tradeoffs in general condition. The gain generally designed in appropriate range of 15~20dB in a conventional LNA for wireless communication. Fig 2.13 shows the model of LNA small signal analysis equivalent circuit.

Rg Lg

Ls

Cgs gmVgs Io

Fig. 2.13 LNA Gmeff small signal analysis equivalent circuit

[ ]

At the resonate frequency, we can get the effect transconductance in equ. (11)

D. Noise Optimization.

This subsection describes noise performance on the inductor-degeneration configuration and designing an optimal dimension of the MOS devices for minimal noise contribution. Noise figure is an important specification in LNA design. In the cascade network of multi-stage, first stage plays an important role to reduce the total noise figure of the receiver system. The LNA is the first stage of the receiver system. In general, LNA noise figure determine the receiver

sensitivity.

+

Fig. 2.14 small signal noise model of MOS device

Fig. 2.14 shows a small signal noise model of the input stage, Rg is gate resistance and Rs is voltage source resistance; Rg can be minimized by good layout. Where Vg²and

id are induced by Rs and channel resistance respectively.

² Thermal noise and gate current noise are main source in LNA design. Especially the channel thermal noise is dominant. The equation

id is listed in (9).

²

0 2 4

kTB g

_d

id

=

γ

(12)

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

Fig. 2.15 Equivalent gate circuit

A equivalent gate circuit model is shown in Fig.2.15. A shunt noise current ig2and a shunt conductance have been added. At resonance frequency, the small signal revised noise model is shown in Fig. 2.16.

g

g

Fig. 2.16 Revised Noise model

2

A common form of the noise factor is listed in equ. (13). It is re-arranged to equ. (14). It is observed that It can further decrease noise factor by to reduce . To achieve low noise factor involves linearity tradeoff. Besides, the technology scaling is a key.

E. Low-Noise Amplifier Circuit Implementation

The new LNA with body-bias circuit is proposed in this thesis. The LNA uses common-source degeneration cascode with fully differential configuration.

Shown in Fig. 2.17, its device size is listed in table I. MN1, MN2 provide the enough gain and noise optimization. MN1, MN2, LS1 and LS2 are designed to optimize the input matching. MN3, MN4 isolate the input RF signal input and LNA output. LD1, LD2 and CC1, CC2 provides impedance for voltage gain in resonate frequency.

The body-bias is applied for MN1, MN2, MN3 and MN4. For this reason, these devices are placed in a deep-NWELL structure to isolate with other NMOS P-substrate. The body-bias scheme can further decrease the threshold voltage and improve the gain and linearity.

All inductors are spiral inductor supplied by TSMC 0.25-um technology. A sub-circuit in HSPICE simulation models the behavior of inductor, MIM

capacitance.

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

Fig. 2.17 LNA circuit

Device Name W/L(um/um) MN1,MN2 120/0.24 MN3,MN4 10/0.24 XLS1,XLS2 2.5n XLD1,XLD2 4.7n CC1,CC2 0.1p

Table 2.1 LNA device parameter

2.3.2 Quadrature voltage control oscillator

This receiver involves the design of circuit to generate a quadrature LO signal with 90-phase difference. The most popular method is to use a voltage-controlled oscillator (VCO), which is usually in the form of the LC-tank. High frequency oscillator usually comprises a resonator, which includes inductor, capacitor, and negative resistor. Fig. 2.18 illustrates the standard circuit of typical resonator. In order to generate quadrature LO signal, a structure of VCO based on even-stage ring oscillator usually be used.

-R L C

Fig. 2.18 Typical RLC tank

Fig. 2.9 is the conceptual block diagram of the quadrature VCO. This structure is like as a two-stage ring oscillator. INV1 and INV2 are identical fully differential inverter. The ring oscillator was combined with two fully differential inverters. Finally, The inverters connect to LC-tank load and a negative resistor respectively.

Fig. 2.19 further depicts the fully differential inverter with LC-tank and negative resistor. MN5 and MN6 act as the negative resistor to cancel the parasitic resistor. Two spiral inductor and varactor decide the frequency of oscillator. MN1 and MN2 act as fully differential inverter. The inverter output terminal is VO1 and VO2. Two identical inverters are combined together for two-stage ring-oscillator.

To observe the output DC level can bias at VDD.

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

+ - +

-INV1

+ - +

-INV2

LOIP LOIN LOQP LOQN

-R₁ L₁ C₁

-R₂ L₂ C₂

Fig. 2.19 Conceptual block diagram of the quadrature VCO

The fully circuit of quadrature voltage-controlled oscillator in this thesis is shown in Fig. 2.21. The output terminal of VCO connected to next stage(mixer) directly.

VCOVB

N5 N6

N1 N2

V1 V2

VO1 VO2

Fig. 2.20 Fully differential inverter with LC-tuned in the quadrature VCO

N=8 N=8 VCOVB

MN5 MN6

MN1 MN2 MN3 MN4

XL1 XL2 XL3 XL4

N=8 N=8

MN7 MN8

VCOVB XC1

XC2

XC3

LOIN XC4

LOIP

LOQP LOQN

Fig. 2.21 The whole circuit of quadeature voltage-controlled oscillator circuit

Device Name W/L(um/um) MN1,MN2,MN3,MN4 10/0.36 MN5,MN6,MN7,MN8 40/0.24 XL1,XL2,XL3,XL4 2.5n

XLD1,XLD2 1.05n

XC1,XC2,XC3,XC4 0.049p

Table 2.2 QVCO device parameter

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

2.3.3 Quadrature mixer

This section discussed the principle and design methodology of the

downconverter mixer. Consider the Fig. 2.22, refer the drain current of basic unit PMOS cell. By means of the PMOS drain current operating equation in saturation, the mixer can achieve the mixing operation.

PMOS is a basic unit cell in this mixer design. First, we can observe that the PMOS current is the function of gate to drain voltage in saturation region.

)2

In order to simplify the following analysis and to make it clearly, replace the gate and drain terminal to ‘Va’ and ‘Vb’ respectively. The drain current of the PMOS device can be written as

( )

]

Thus, the voltage of Vmx1 shown in Fig. 2.22 will become (Vt is replaced by constant value C )

Fig. 2.22 Basic PMOS unit cell of mixer

Va

Fig. 2.23 Mix Va and Vb operation constructed by two basic PMOS device

Illustrate in Fig. 2.23, merge two basic PMOS unit cells as and summation the Id current flow through the Z_L. The Id current can be deriving as.

( )

Fig. 2.24 double-balanced mixer structure

The Fig. 2.24 shows the double-balanced mixer structure.

Vb

To replace the sign of equations. It can be Va=LOIP, -Va=LOIN, Vb=MXIP, -Vb=MXIN

CHPATER 2 CIRCUIT ARCHITECTURE AND SIMULATION RESULTS

VBMXIF

MP5 MP7 MP6 MP8

MP1 MP3 MP2 MP4

MXIP

MXIP

MXIN MXIN MXIP MXIN

VBMXRF

LOIP LOIN LOQP LOQN

1k 1k

MN2 MN3 MN4 MN5

MN1

XC2

XC1

XC4

XC3 IFIP

IFIN IFQP

IFQN

Fig. 2.25 Quadrature downconversion mixer schematic

Device Name W/L(um/um) MP1,MP2,MP3,MP4,

MP5,MP6,MP7,MP8

5/0.3 MN1,MN2,MN3,MN4 10/0.24 XC1,XC2,XC3,XC4 0.9p

Table 2.3 Mixer device parameter

2.3.4 Active polyphase filter

The polyphase filter and output buffer are the last stage of receiver front-end system. The polyphase filter stage that follows the mixer and selected the desired signal to output. The polyphase filter is used to reject image interference in a receiver front-end system. It must have the features with high image rejection ratio, low sensitivity to mismatching components, sufficient linearity, and low power

The polyphase filter and output buffer are the last stage of receiver front-end system. The polyphase filter stage that follows the mixer and selected the desired signal to output. The polyphase filter is used to reject image interference in a receiver front-end system. It must have the features with high image rejection ratio, low sensitivity to mismatching components, sufficient linearity, and low power

在文檔中 具有基體偏壓之低雜訊放大器及整合型多相位濾波器之1-V 2.4-GHz低中頻架構前端接收器電路設計 (頁 26-0)