Receiver Architectures

As RF receiver is evolving continuously, several architectures in recent years can be generalized. The-well-know architectures are heterodyne receiver, homodyne receiver and low-IF/ image-reject receiver [4].

A. Heterodyne receiver

Heterodyne receiver downconverts the received RF signal to interested intermediate frequency (IF), which is usually much lower than the initially received frequency band. The heterodyne receiver is illustrated in Fig. 2.

L NA Im age Reject

Fig. 2 Architecture of heterodyne receiver

This topology leads to the severe tradeoff between sensitivity and selectivity [4]. A high IF increases the difference frequency between image and desired signal and gets a better image-rejection performance, but this need a channel-selection filter with very high Q-factor.It is difficult to design a filter of sufficiently high Q-factor on chip. Even

if integrated image-reject filter is realized in practice [6]. This is not suitable for low power design. If the IF is low, the channel-selection filter has a more relaxed requirement, but proper image suppression becomes harder to achieve. To relax the trade-off, dual-IF topology is applied [7], but it has power-consumption issue due to more circuit stage for multi-downconversion procedure.

Compared to other topologies, heterodyne receiver can achieve better performance;

but it is more complexity, difficult integration and not appropriate to different wireless standards and modes.

B. Homodyne receiver

The homodyne receiver also called zero-IF or direct-conversion which avoids the disadvantages of the heterodyne architecture by converting the RF signal directly to baseband. It translates the channel of interest directly to zero frequency in one step by mixing with an LO output of the same frequency. A low-pass filter that is used to suppress nearby interferers filters the resulting baseband signal. The homodyne receiver is illustrated in Fig. 3.

L N A D o w nco nv erter C ha nnel-Select

Fig. 3 Architecture of homodyne receiver

The main advantage of homodyne receiver is the high integration, simplicity of structure, cost and power reduction. It avoids the need for an off-chip IF filter and requires only one single frequency synthesizer. The problem of the image is minimized, as the incoming RF signal is down-converted directly to zero, if the quadrature down-converter is used [8]. As result, no image-reject filter is required. The possibility of changing the bandwidth of the integrated low-pass filters (and thus, changing the

receiver bandwidth) is the other advantage if multimode and multi-band applications are of concern [9]. The homodyne receiver also allow analog-to-digital converter (ADC) and digital signal processing (DSP) circuits to perform demodulation and other ancillary functions, relaxes the selectivity requirements if highly integrated, low-cost and low-power realization [5].

Homodyne receivers suffer impairment of DC offset, flicker noise, I/Q mismatch and even-order distortion. The effects of even-order distortions can generally be made sufficiently by negligible with good circuit techniques and I/Q mismatch is the biggest challenge in the implementation of CMOS frequency synthesizer. However, DC offset and flicker noise problems are generally considered much more serious and challenging to the designers.

C. Low-IF/Image-reject receiver

The low-IF topology starts from combined the advantages of both receiver types introduced above. The low-IF receiver is no DC offset problem but have image problems. The most common techniques to remove the image are to use IR architecture [10] or polyphase filter [11]. Furthermore, the signal bandwidth in low-IF conversion is twice that in direct conversion, therefore requires doubling the analog-to-digital conversion sampling rate, and results in higher power consumption. Finally, the double signal bandwidth in low-IF conversion mandates to double the baseband filter bandwidth, which further increases design complexity and power consumption [12].

One type of image-reject receiver is the Hartley architecture [13]. The main drawback of this architecture is that the receiver is very sensitive to mismatches due to phase and gain imbalance of the local oscillator signals, which causes incomplete image cancellation. Also, the loss and noise of the shift-by-90° stage and the linearity of the adder are critical parameters. Another type of image-reject receiver is the Weaver architecture [14]. Similar to the Hartley receiver, the image can no longer be cancelled

completely if the two local oscillator signals are not perfect 90°. However, the Weaver architecture is also sensitive to mismatches, but it avoids the use of RC-CR network, thereby achieving greater image rejection despite process and temperature variation [2].

1.2.2 Issues of Direction-Conversion

The direction-conversion receiver entails a number of issues that consulted previously need to conquer in favor of full integration.

A. DC offset

The major disadvantage is that severe DC offset can be generated at the output of the mixer.DC offset in a homodyne receiver are illustrated in Fig. 4. The DC offset can be generated by self-mixing of the LO leakage signal with the LO signal [Fig. 4 (a)] or self-mixing of a strong interferer due to leakage from the LNA [Fig. 4 (b)]. The LO and interferer leakage arise from capacitive and substrate coupling. If self-mixing varies with time, it leads DC offset issue to be exacerbated. Undesired DC offset corrupts the baseband signal and saturate the following gain stages. Also, DC offset in I/Q signal paths shifts the baseband signal constellation, causing potential signal saturation, as well as degrading the bit error rate (BER) performance [15]. Moreover, the transistor mismatch in the signal path and demodulation of large amplitude modulated signal via second-order nonlinearity of the mixer that also generates DC offset.

LNA Downconverter Fig. 4 Self-mixing of LO leakage and interferer leakage

A solution for DC offset removal is to employ ac-coupling, i.e. high–pass filtering, in the down-converted signal path. Unfortunately, this solution removes the DC energy

of desire signal. It requires prohibitively large capacitors or resistors and accompanies unavoidable in-band loss. A low corner frequency in the HPF may lead to temporary loss of data in the presence of wrong initial conditions, and result in long transient settling during gain changes or Tx-to-Rx switching [16]. There is similar way to withstand DC offset by ac-coupling and unity gain amplifier, but it must face the linearity issue simultaneously [17].

The dc-coupled with feedback configuration, using negative feedback around the baseband amplifier, is another topology to suppress the DC offset. It circumvents the disadvantages in the ac-coupling method. However, the gain of baseband amplifier is large and has a number of stages. It makes the feedback path with very large capacitance or the extremely small transconductance. Additionally, It is also constraint on stability in the circuit design [18][19][20].

Also, in the multi-phase reduced frequency conversion receiver architecture, the VCO frequency is reduced and deviated from the carrier frequency and the DC offset can be drastically reduced [21]. But it brings about complexities and symmetrization on circuit design, consumes extra power due to using multi-phase mixer and VCO.

The architecture of balanced harmonic mixer can alleviate offset extremely, it uses second harmonic of the LO signal that takes part in the mixing process. As a result, the LO leakage generates no DC component but an output which is still situated at the LO frequency and can be easily filtered out [22][23]. The main issues of this architecture are its weakness on linearity and require higher LO strength due to use of second harmonic signal.

Dynamic calibration and DSP techniques are other popular techniques employed to minimize signal degradation [12][24]. It uses DACs and lookup table (LUT) to calibrate static dc periodically and compensate for temperate fading. However, this requires extra DACs and LUT circuit. The operation and algorithm are complicated, the calibration is

executed only in idle mode and no signal detected.

An offset cancellation mixer can cancel offset by dynamically varying the bias on the loads, which are designed to provide constant impedance independent of the load cancellation current [25]. Nevertheless, the circuit needs extra two digital filter (ex: IIR) to detect dynamic offset. It also requires DACs and common-mode feedback (CMFB) circuits. This would consume more power and pay more attention to circuit stability.

The comparison on DC offset removal methods are listed in Table 1-1. Generally, the offset cancellation circuit in a receiver should be simplification, power saving and erode performance few as far as it can.

Table 1-1 Comparison on DC offset removal methods

Reference [17] [19] [21] [23] [12] [25]

Large C or R ˇ ˇ

Long settling time and in-band loss ˇ Constraint on stability ˇ

Weakness on linearity ˇ

Required CMFB ˇ

Sensitive to layout ˇ

Architecture complexities ˇ ˇ

Require DACs ˇ ˇ

Consume extra power ˇ ˇ ˇ ˇ ˇ ˇ

B. Flicker noise

The flicker noise, also knows as 1/ƒ noise, is an intrinsic noise phenomenon found in semiconductor devices, especially in CMOS implementations. Flicker-noise property of a device is semiconductor dependent, and the corner frequency is typically in the vicinity of 1MHz for MOSFET devices [15]. Since the mixer output is down-converted

to a baseband signal, it is quite sensitive to noise and easily be corrupted by the large flicker noise of the mixer.

The flicker-noise effect can be minimized by proper selection of semiconductor processes with low corner frequency and providing adequate gain in the front end to improve relative signal-to-noise ratio (SNR) at the down-converter output. It also can incorporate very large device to minimize the magnitude of the flicker noise [4]. A two-stage mixer where the V/I converter and the switching quad biasing current can be independently optimized that achieves lower noise figure while maintaining the same conversion gain [26]. Since holes are less likely to be trapped, pMOSFETs have less flicker noise than nMOSFETS.

C. I/Q mismatch

I/Q mismatch, or phase and gain mismatch, introduced by the mixer is another critical issue for homodyne receiver topology. Gain error simply appears as a non-unity scale factor in the amplitude. Phase imbalance, on the other hand, corrupts each channel by a fraction of the data pulses in the other channel; in essence degrading the signal-noise ratio if the I and Q data streams are uncorrelated. Any mismatch distorts the constellation diagram of the baseband signal, resulting in an enhanced BER [4].

Tolerable gain and phase imbalance depends on modulations techniques employed in a system. For example, the use of 64-QAM modulations require a SNR of 30 dB, which is substantially greater than required by the FSK modulation in Bluetooth and the QPSK modulation in 802.11b. This high SNR translates to stringent phase noise requirements and tight I/Q matching constraints [27].

The problem of I/Q mismatches needs to conquer and to make it less sensitive to process variation and temperature. For instance, a self-calibrated circuit with ring oscillator [28] or an LC oscillator with a poly-phase filter [29] can get over it very well.

However, they come up against large power consumption.

A quadrature LC-VCO can easily generates I/Q signals at the cost of twice power consumption and twice area [30]. An advantage of this architecture is its large signal swing that enables the VCO to drive mixer or prescaler directly. If LC-VCO is well designed, twice power consumption of two VCOs is not an obstacle compared to the power-consuming buffer or ring oscillator. There is still a problem that device variation can induce I/Q mismatch. It is possible to compensate the effect by self-calibrated the VCOs tail current [31].

D. Even-order distortion

Two high-frequency strong interferers close to the channel of interest experience a nonlinearity circuit, such as LNA, those interferers generate a low-frequency beat in the presence of even-order distortion. In the presence of mismatches and asymmetry of the RF path, except for odd-order intermodulation effects, even-order distortion can also becomes problematic in direct-conversion [4].

Even-order effect can be reduced by adopting differential circuits or by HPF filtering the beats. Differential LNAs and double-balanced mixers are less susceptible to distortion because of the inherent cancellation of even-order products. However, the phenomenon is critical for balanced topologies as well due to unavoidable asymmetry between the differential signal paths and cost twice of the single-sided half circuit [32].

1.2.3 Low-Voltage Receivers

There is a receiver realized for 5-GHz wireless application [33]. It use homodyne architecture, implement in 0.25- μ m CMOS technology and operated at 3-V. It comprising a differential LNA, an active mixer, a VCO buffer and a quadrature voltage-controlled oscillator exhibits low noise figure. But it consumes higher power dissipation and no DC offset cancellation design in the circuit.

The key for such a RF receiver design is how to reduce power consumption and cost. Circuit operation at reduced supply voltage is a common practice adopted to

reduce power consumption. However, the circuit performance degrades and one gets low circuit bandwidth and voltage swing at low voltage. Scaling down the threshold voltage of MOSFETs compensates for this performance loss to some degree, but this result in increased static power dissipation [34].

There are two receiver realized with low voltage supply for 5-GHz wireless application [35][36]. One comprising a differential LNA, an active mixer, and a quadrature voltage-controlled oscillator exhibits high linearity. The other comprising a differential LNA, a Gilbert mixer, integer-N frequency synthesizer, AGC loop, and low-pass channel-select filter performs low-power consumption.

1.3 MOTIVATION

In IEEE 802.11a, the center sub-channel is unused, providing an empty spectrum of +/- 156.25 kHz after translation to the baseband. It is very favorable for direct-conversion architecture. Base on this reason, the design of this thesis is to realize a 1-V 5-GHz direct-conversion front-end receiver based on IEEE 802.11a specification and integrated with LNA, quadrature VCO and downconverter for low-power wireless system applications by TSMC 0.18μm technology. The standard specifies an operating frequency range 5.15 ~ 5.35 GHz with 8 channels of 20 MHz bandwidth per-channel.

This thesis is proposed a new offset compensation circuit with band-pass filter as the downconverter loads to suppress extraneous offset voltages corrupt the signal and saturate the following stages. Based on low-power consumption, this trend dictates that the RF front-end receiver will have to operation with low supply voltage.

The receiver adopts differential circuits to reduce the even-order distortion effect, selected PMOS and provided adequate gain to minimize the flicker noise. Quadrature LC-VCO architecture is to make it less sensitive to I/Q mismatches. Fig 5 shows the receiver architecture in this thesis.

1.4 THESIS ORGANIZATION

Chapter 2 proposes a downconverter comprising DC offset compensation circuit with design considerations, post-simulation results on downconverter. The down converter is also applied in a proposed RF receiver front-end. Chapter 3 illustrates IEEE 802.11a PHY standard and link budget of circuit block. The low-voltage RF receiver front-end comprises a differential LNA, two downconverters and a quadrature voltage-controlled oscillator. The implementation and post-simulation results is completed. Chapter 4 contains experimental results and discussions. Finally, conclusions and future works are described in Chapter 5.

LNA

Downconverter _I path

IF Output Q_path

Quadrature VCO

Downconverter _Q path

IF Output I_path CosW_LOQ t SinW_LOI t

RF

Fig. 5. Receiver architecture in this thesis

CHAPTER 2

DOWNCONVERTER WITH DC OFFSET COMPENSATION

In the radio frequency transceiver operated in the gigahertz range, the quadrature modulator/de-modulator is one of the key components, which has significant effects in the quality of converted signals. The direct-conversion quadrature downconverter can effectively reduce cost, power dissipation, and chip area compared to the heterodyne quadrature modulator. It also has good performance in image rejection and LO leakage.

2.1 OPERATIONAL PRINCIPLE

Downconverters are commonly used to multiply signals of different frequencies in an effort to achieve frequency translation. Clearly a linear system cannot achieve such a task, and it need to select a nonlinear device such as a diode, BJT, or FET that can generate multiple harmonics. Consider an N-MOS device operating in saturation region.

The drain current is function of the gate and source voltages, ideally written as iD = K [(vG - vS) - VT]²

= K [v_G² – 2v_Gv_S + v_S² – 2(v_G - v_S) + V_T²] (1) , Where

L C W

K _{0 OX}

2 1µ

= and V_T are assumed to be constants. Suppose a basic cell is designed to have an input/output relation similar to (1), shown in Fig. 6. It depicts the basic system arrangement of a mixer connected to an RF signal, a₁, and local oscillator signal, b1, which is also known as the pump signal. The function is supposed to be

X

Next step, include another basic cell X to construct a differential-input one, basic cell Y, illustrated in Fig. 7.

Fig. 7. Basic cell Y constructed by two basic cells X

The second basic cell X is fed by –a1 and –b1, then input/output relation of basic cell Y

In this thesis, the downconverter is used the double-balanced structure and if substitution of parameters is introduced as

t

a₁ =cosω_RF , b₁ =cosω_LOt , the input/output relation becomes

t t

d₃ =8cosω_RF⋅ ×cosω_LO⋅

The result can corresponds to the I-channel of quadrature IF output. By the same way,

the Q-channel IF output is obtained if

Fig. 8. Double-balanced structure

2.2 DESIGN CONSIDERATION

2.2.1 DC Offset Compensation

As previously chapter mention, the DC offset is generated by self-mixing effect.

Generally, the total gain from the RF antenna to the ADC is typically around 100 dB so as to amplify the microvolt input signal to a level that can be digitized by a low cost, low power ADC. Of this gain, typically around 25 dB is contributed by the LNA/mixer combination and residue is provided by the automatic gain control (AGC). If an offset is obtained resulting from self-mixing and produces at the output of the downconverter is on the order of tens-milli volt. Thus, it directly amplified by the AGC; the offset voltage saturates the following circuit or downconverter itself, thereby prohibiting the amplification of the desired signal [15].

When the self-mixing is occurred, it may treat a current appearing at the output of the downconverter. These current flows into the downconverter load and bring an extra

voltage on the load. Fig. 9 shows a simple example for DC offset observation.

Assuming the P-MOS acts as a downconverter and the RF signal and local oscillator signal have the same frequency, this plays similarly a self-mixing situation. Supposing the extra voltage at the output of downconverter is positive.

LO

Fig. 9. Simple example for dc offset observation

In the Fig. 9 (a), the RF signal and LO signal will downconvert to DC and a DC current flows into the resistor, therefore a extra voltage build on the output of initial bias point. Fig. 9 (b) is a P-MOS mixer with a constant biasing load, N-MOS. After mixing signal, an additional current appear and flow into N-MOS. If the N-MOS device is in saturation region and channel-length modulation is considered, the drain current is written as: , where λ is channel-length modulation parameter. The V_DS voltage will vary with the ID proportionally when the voltage of VGS is constant. It means that the output voltage vary with the strength of injecting power. Larger injecting power for self-mixing process will produce more unwanted current to flow into the load, further DC offset

(a) (b)

voltage appear on the output node of downconverter. It influences the downconverter itself and following stage severely.

Because of substrate coupling effects are always existent: coupling of the LO to the LNA and RF port of the downconverter cause static offset or LO couples to the antenna, radiates and then reflects off moving objects back to the antenna, a time varying offset

Because of substrate coupling effects are always existent: coupling of the LO to the LNA and RF port of the downconverter cause static offset or LO couples to the antenna, radiates and then reflects off moving objects back to the antenna, a time varying offset