T HESIS O RGANIZATION - 低電壓５-GHz互補式金氧半電晶體直接降頻式射頻前端接收器

CHAPTER 1 INTRODUCTION

1.4 T HESIS O RGANIZATION

Chapter 2 proposes a downconverter comprising DC offset compensation circuit with design considerations, post-simulation results on downconverter. The down converter is also applied in a proposed RF receiver front-end. Chapter 3 illustrates IEEE 802.11a PHY standard and link budget of circuit block. The low-voltage RF receiver front-end comprises a differential LNA, two downconverters and a quadrature voltage-controlled oscillator. The implementation and post-simulation results is completed. Chapter 4 contains experimental results and discussions. Finally, conclusions and future works are described in Chapter 5.

LNA

Downconverter _I path

IF Output Q_path

Quadrature VCO

Downconverter _Q path

IF Output I_path CosW_LOQt SinW_LOIt

Fig. 5. Receiver architecture in this thesis

CHAPTER 2 DOWNCONVERTER WITH DC OFFSET COMPENSATION

In the radio frequency transceiver operated in the gigahertz range, the quadrature modulator/de-modulator is one of the key components, which has significant effects in the quality of converted signals. The direct-conversion quadrature downconverter can effectively reduce cost, power dissipation, and chip area compared to the heterodyne quadrature modulator. It also has good performance in image rejection and LO leakage.

2.1 OPERATIONAL PRINCIPLE

Downconverters are commonly used to multiply signals of different frequencies in an effort to achieve frequency translation. Clearly a linear system cannot achieve such a task, and it need to select a nonlinear device such as a diode, BJT, or FET that can generate multiple harmonics. Consider an N-MOS device operating in saturation region.

The drain current is function of the gate and source voltages, ideally written as iD = K [(vG - vS) - VT]²

= K [v_G² – 2v_Gv_S + v_S² – 2(v_G- v_S) + V_T²] (1) , Where

L C W

K ₀ _OX

2 1µ

= and V_T are assumed to be constants. Suppose a basic cell is designed to have an input/output relation similar to (1), shown in Fig. 6. It depicts the basic system arrangement of a mixer connected to an RF signal, a₁, and local oscillator signal, b1, which is also known as the pump signal. The function is supposed to be

X

Next step, include another basic cell X to construct a differential-input one, basic cell Y, illustrated in Fig. 7.

Fig. 7. Basic cell Y constructed by two basic cells X

The second basic cell X is fed by –a1 and –b1, then input/output relation of basic cell Y

In this thesis, the downconverter is used the double-balanced structure and if substitution of parameters is introduced as

a₁ =cosω_RF , b₁ =cosω_LOt , the input/output relation becomes

t t

d₃ =8cosω_RF⋅ ×cosω_LO⋅

The result can corresponds to the I-channel of quadrature IF output. By the same way,

the Q-channel IF output is obtained if

Fig. 8. Double-balanced structure

2.2 DESIGN CONSIDERATION

2.2.1 DC Offset Compensation

As previously chapter mention, the DC offset is generated by self-mixing effect.

Generally, the total gain from the RF antenna to the ADC is typically around 100 dB so as to amplify the microvolt input signal to a level that can be digitized by a low cost, low power ADC. Of this gain, typically around 25 dB is contributed by the LNA/mixer combination and residue is provided by the automatic gain control (AGC). If an offset is obtained resulting from self-mixing and produces at the output of the downconverter is on the order of tens-milli volt. Thus, it directly amplified by the AGC; the offset voltage saturates the following circuit or downconverter itself, thereby prohibiting the amplification of the desired signal [15].

When the self-mixing is occurred, it may treat a current appearing at the output of the downconverter. These current flows into the downconverter load and bring an extra

voltage on the load. Fig. 9 shows a simple example for DC offset observation.

Assuming the P-MOS acts as a downconverter and the RF signal and local oscillator signal have the same frequency, this plays similarly a self-mixing situation. Supposing the extra voltage at the output of downconverter is positive.

LO

Fig. 9. Simple example for dc offset observation

In the Fig. 9 (a), the RF signal and LO signal will downconvert to DC and a DC current flows into the resistor, therefore a extra voltage build on the output of initial bias point. Fig. 9 (b) is a P-MOS mixer with a constant biasing load, N-MOS. After mixing signal, an additional current appear and flow into N-MOS. If the N-MOS device is in saturation region and channel-length modulation is considered, the drain current is written as: , where λ is channel-length modulation parameter. The V_DS voltage will vary with the ID proportionally when the voltage of VGS is constant. It means that the output voltage vary with the strength of injecting power. Larger injecting power for self-mixing process will produce more unwanted current to flow into the load, further DC offset

(a) (b)

voltage appear on the output node of downconverter. It influences the downconverter itself and following stage severely.

Because of substrate coupling effects are always existent: coupling of the LO to the LNA and RF port of the downconverter cause static offset or LO couples to the antenna, radiates and then reflects off moving objects back to the antenna, a time varying offset is created. The undesired reaction won’t disappear and need to handle appropriately.

A new method to compensate the DC offset is proposed in this thesis. As show in Fig. 10, the P-MOS also acts as the downconverter and the output voltage is feedback to bias the N-MOS load by a large feedback resistor, instead of the constant bias, Vb.

When an additional current appear by self-mixing and flow into N-MOS, the V_GS=V_DS as the IG is zero, the equation (3) can be re-written as:

) 1

( )

( _DS _t ² _DS

D K V V V

I = − ⋅ +λ (4) With the same amount of offset current, the V_DS are suppressed in square degree. The tens-milli volt order of voltage mention previously by self-mixing at the output of the downconverter can be reduced to few milli volts. The offset suppressed ability of this circuit is proportional to the transconductance of the N-MOS load.

L O

RF

O utput

Rm

Fig. 10 DC offset compensation circuit

2.2.2 Band-Pass Filter

In the conventional receiver, the downconverter always connect to a channel select filter that can filter out the unwanted band, such as harmonic signal and any interferers outside the interesting band. Since offset removal circuit would entail channel select filter filtering the baseband signal, it is important to examine the consequences of such an operation for the modulation schemes of interest. In IEEE 802.11a specification, the center subcarrier is unused, providing an empty spectrum of ± 156.25 kHz after translation to the baseband. Thus, if the lower corner frequency of the band-pass filters, fL, fall below this value, then the spectrum of the subcarriers carrying information remains intact. Consequently, a lower corner frequency of 150 kHz and bandwidth of 10 MHz band-pass filters are required.

A second-order LC high-pass filter with low corner frequency (about 150 kHz) is required a very high Q value, a value difficult to achieve. It is important to note that typical filters exhibit a trade-off between the loss and the Q value. In order to significantly relax the linearity and Q value requirement of the baseband stage, the front-end receiver chain further contains a band-pass filter to provide partial channel selection.

L O

\ C n Rm

Fig. 11. A band-pass filter as downconverter load

The downconverter contains a band-pass filter showing in Fig. 11. The P-MOS also acts the downconverter and the Cm is connected at gate of the N-MOS to form a simple partial channel selection filter. Because of the N-MOS is worked in the saturation inevitably, using the small-signal model of the N-MOS device, hybrid-π model, and the output impedance looking from Z of Fig. 11 can be written as:

( )

, where the C_gs is lumped with Cm. r_o is the MOS small-signal output resistance and gm is top-gate transconductance. From the equation (5), the output impedance Z very with frequency and it has two corner frequencies, f_L and f_H. The f_L is mainly decided by the Cm and Rm. The fH is dominated by the Cn. Proper choosing the passive elements can get the required frequency spectrum as showing in Fig 12, if the output impedance of downconverter is greater than the load Z. Using this kind of impedance treat as downconverter load and the IF output is accomplished a simply channel selection.

A new DC offset compensation circuit with band-pass filter is proposed. Without DACs or complex multi-phase architecture, this circuit uses a few passive components to achieve offset compensation and filtering and it is effective in that it does not incur any in-band loss. The proposed circuit doesn’t increase numerous power dissipations and a benefit for low-voltage and low-power design.

Fig. 12. Band-pass impedance frequency spectrum

2.2.3 Voltage Conversion

This subsection describes how circuit devices construct the function block and the voltage conversion in preceding discussion. Referring to Fig. 13, basic cell X in Fig. 6 is realized by a PMOS device. By the similar way, implementation of basic cell Y is presented in Fig. 14. To realize the output result in equation (2), Fig 14 is developed to Fig. 15. The equation (2) can be modified to equation (6), a more realistic function, by the circuit implementation in Fig. 15.

S G

LK V V

d₃ = 8 ⋅ ⋅ (6)

~

^V^S

~

^V^G

Z_L i_D

Fig. 13. Realizations of basic cell X

~

^V^S

~

^-V^S

~

^V^G

~

^-V^G

Z_L i_D

Fig. 14. Realizations of basic cell Y

~

^V^S

~

^-V^S

~

^V^G

~

^-V^G

Z_L

+

~

^V^S

~

^-V^S

~

^-V^G

~

^V^G

Z_L -d₃

-Fig. 15. Realizations of double-balanced combiner

All developments for the downconverter are originally based on equation (1), ideal square- law. Because of channel pinched-off, a MOS device works in saturation region.

If a short-channel device is employed in circuit implementation, another mechanism causing saturation is involved [37]. In a short-channel device, velocity saturation occurs before pinched-off. Taking velocity saturation and mobility degradation into consideration, equation (7) presents an advanced formula modified from the ideal

square-law, where vsat denotes saturated velocity and θ is a fitting parameter approximately equaling to ¹

10⁻7 ₋

According to equation (7), equation (6) is modified to equation (8)

(

_GS _T

)

_G _S

The result indicates that the designed downconverter performs expected function on condition that MOS devices work in saturation region with sufficiently small overdrives.

For circuit implementation, the VG would be the RF signal and VS is LO signal.

Generally, the load and LO signal, Z_Land V_S, influences the d3, output voltage amplitude directly.

2.2.4 Noise and Linearity

The single-balanced configuration exhibits less input-referred noise for a given power dissipation than the double-balanced counterpart. However, the circuit is more susceptible to noise in the LO signal. It is more intensified by the high noise floor of typical oscillators. In both mixer topologies, a differential output provides much more immunity than single-ended output to feedthrough of the RF signal to the IF output. By contrast, if the output is sensed differentially, the effect of direct feedthrough is much less significant. It implies that the differential output have better noise figure than single-ended IF output. Accordingly, a differential band-pass filter is needed; the differential output of the downconverter can directly drive the filter [4].

After downconverter, the downconverter spectrum is around zero frequency, flicker

noise of devices has profound effect on the signal. Therefore the downconverter is the most critical stage in the receiver chain in combating the flicker noise. In most cases, the magnitude of the input-referred flicker noise component is approximately independent of bias current and voltage and is inversely proportional to the active gate area of the transistor. The latter occurs because as the transistor is made larger, a larger number of surface states are present under the gate, so that an averaging effect occurs that reduces the overall noise. It is also observed that the input-referred flicker noise is an inverse function of the gate-oxide capacitance per unit area. For a MOS transistor, the equivalent input-referred voltage noise can be written as [38]

It is also interesting to note that while all of downconverter are no, the MOS switches injecting noise to the output. Employing large LO swings or decreasing the drain bias current of the MOS switch can minimize the contribution of the thermal and channel thermal noise. The trade-offs described above require a careful choice of device size and bias currents so as to minimize the overall noise figure. Since holes are less likely to be trapped, P-MOS has less flicker noise than N-MOS.

In order to reduce the noise figure, the downconverter should have moderate NF and adequate conversion gain to minimize the noise. This can obtain by increased the downconverter load, as designated last subsection Z_L,to increasing conversion gain.

With the constant bias current, the larger load impedance causes the larger voltage drop on it, thus decreases the voltage headroom of the remaining MOSFETs and degrades the linearity of the downconverter, especially for the low-voltage design. This is a trade-offs between noise and linearity. By the way, for the intrinsic nonlinearity of the transistors,

it is important to notice that the distortion in inversely proportional to the gate length and this effect will become even more important when going to deeper sub-micrometer technologies [39].

2.3 CIRCUIT REALIZATION

Based on the considerations in the previous section, a downconverter with DC offset compensation circuit is designed. Fig. 16 presents downconverter divided into I/Q-channel paths and lists the relative parameter information in Table2-1. The downconverter is double-balanced counterpart and fully differential configuration. In the aspect of low-voltage design, the downconverter doesn’t use the conventional Gilbert cell. The V/I converter of Gilbert cell is removed and direct connects to designed VCO output in order to save the voltage headroom. It needs no re-bias on the source terminals. To realize the direct connection and flicker noise consideration, P-MOS devices are employed as the downconverter. Furthermore the load of downconverter is implemented with N-MOS device. Total DC-drop from sum of sufficient drain-source voltage is merely about 0.4 V by TSMC 0.18-μm technology. In the condition, downconverter function is achievable at 1-V supply voltage.

Because of the corner frequency, f_L as shown in Fig.12, is obtained by the Rm and Cm product approximately, Cm will occupy a large area when the resister value smaller, vice versa. In order to save the chip area, the Cm is replaced by Cmi1 and Mmi12, for example, in the Fig. 16 (a). It uses the Miller effect to multiply Cmi1. With the proper design, the Cmi1 can be multiplied about 16, saving a lot chip area. The Rm is used high resister type such as the HRI P-poly resister without silicide. The Rri1 or Rrq1 is used to make the load of downconverter more flatness in the interesting band. The differential circuit is very sensitive to device symmetrization. Using Mmq7 and Mmq8, or Mmi7 and Mmi8, with off-chip bias, the adjustable bias, VMi# and VMq#, can

cancel the offset voltage brought by the device mismatch. It is also option to compensate the DC offset using varying bias controlled by the DACs, such as in [25], but this will make circuit more complexity.

M m i2 M m i3 M m i4

Fig. 16. (a) I-channel and (b) Q-channel of double-balanced downconverter with DC offset compensation circuit

Table 2-1 Parameter information of Fig. 16

Mmi1 ~ Mmi4 and Mmq1 ~ Mmq4 45μm/0.25μm Mmi5 ~ Mmi6 and Mmq5 ~ Mmq6 60μm/0.5μm Mmi7 ~ Mmi8 and Mmq7 ~ Mmq8 10μm/0.5μm Mmi9 ~ Mmi11 and Mmq9 ~ Mmq11 15μm/0.18μm Mmi12 ~ Mmi13 and Mmq12 ~ Mmq13 12.5μm/0.18μm

Rri1 and Rrq1 2k Ω

Rri2 and Rrq2 800 Ω

Rmi1 ~ Rmi2 and Rmq1 ~ Rmq2 152 kΩ Cmi1 ~ Cmi2 and Cmq1 ~ Cmq2 6 pF

Cni1 ~ Cni2 and Cnq1 ~ Cnq2 5 pF

2.4 SIMULATION RESULTS ON DOWNCONVERTER

Post-simulation is completed by ADS simulator with process parameters of TSMC 0.18-μm mixed signal 1P6M RF SPICE models. Fig. 17 presents the simulated voltage conversion gain of the downconverter. The conversion gain is about 0 dB at the interesting band and the corner frequencies are at 150 KHz and 30 MHz respectively.

Fig. 17. Simulated voltage conversion gain of the downconverter

The Cmi#, for example, is enlarged by Miller’s amplifier, Mmi12 and Mmi13.

When the gain of the Miller’s amplifier is varied due to process variation, the corner frequency is influenced by the gain variation directly. While Miller’s amplifier is with +/- 6% dimension variations, Fig. 18 presents the each voltage gain versus frequency on gain variations and the relative corner frequency is listed in Table 2-2. The normal Miller’s gain is designed at 24.66 dB. If the dimension variation is set to +/- 3%, the fL is about 150 kHz +/- 30 kHz.

Fig 19 presents output noise voltage spectral density of downconverter. The noise bandwidth of this circuit is from 150 KHz to 10 MHz and the total noise figure of the downconverter is given approximately by

∫

_⋅

= ^M

KGain Nin F ¹⁰ Nout

150 (10)

Fig. 18 Voltage gain versus frequency on gain variations Table 2-2 Relative corner frequency of Fig.18

Miller’s gain fL fH

28.1 dB 0.11 MHz 27 MHz

24.66 dB 0.15 MHz 30 MHz

22.12 dB 0.19 MHz 32 MHz

Fig. 19. Output noise voltage spectral density of downconverter

, where the Nout is the output noise power, Nin is the input noise power and Gain is the voltage conversion gain of the downconverter. The noise figure of downconverter at the interesting band is 17.2dB.

Two-tone test is applied to simulate linearity of the downconverter circuit. This response was obtained by feeding two signals at 5.209-GHz and 5.211-GHz to the RF port. The combined two-tone RF signal was mixed with a 0-dBm LO signal at 5.21-GHz. This setup was used to extract the 1-dB compression point and the third- order intercept point (IP3) by sweeping the input power level. Fig. 20 plots output power of first and third order terms relative to input power. A high input intercept of approximately 10 dBm was extrapolated, and a 1-dB compression point was observed near –0.7 dBm.

Fig. 21 shows simulated results of the DC offset compensation. The RF port is fed one tone signal which frequency is same as LO frequency. After self-mixing, a signal current will appear at DC on the each output terminals of the downconverter and influence its bias level. This setup is used to estimate the circuit ability of withstand un-wanted signal leakage. By sweeping the input power level, the DC offset voltage at the differential output terminals will increase, as shown in Fig.21. The DC offset

Hz f V

Nout

voltage is about 3-mV at single output with injected power of –30-dBm and about 6-mV at differential output in same condition. The power consumption is about 1mW for the compensation circuit.

At the last of chapter 2, a post-simulation summary of the downconverter is listed in Table 2-3. The power consumption shown in the table is included two paths of downconverters. The downconverters is fed with 0-dBm LO signal at 5.25-GHz and the RF port is fed with –40-dBm RF signals at 5.26-GHz during simulation.

Fig. 20. Extrapolation of downconverter IIP3

Fig. 21. DC offset voltage caused by injected leakage powers

Table 2-3 Post-simulation summary of the downconverter Technology TSMC 0.18-μm 1P6M

Frequency 5.25 GHZ

Supply Voltage 1.0 V

Power Consumption 3.83 mW

Conversion Gain 0 dB

SSB NF 17.2 dB

P-1dB -0.7 dBm

IIP3 10 dBm

DC Offset (injected -30dBm at downconverter input)

6mV

CHAPTER 3 1-V 5-GHz DIRECT-CONVERSION FRONT-END RECEIVER

Direct-conversion receiver is mentioned in Chapter 1. In addition to a LNA and downconverters, the designed receiver requires a quadrature VCO. Fig. 22 gives an illustration with a block diagram. The downconverters are implemented to a double-balanced downconverter as chapter 2 mentioned. The LNA is fully differential with common-source-cascode architecture. The quadrature VCO generates quadrature LO signal and quadrature IF signal comes from downconverter of the RF and LO

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