CHAPTER 3 1-V 5-GHz DIRECT-CONVERSION
3.2.1 Differential Low Noise Amplifier
In RF system, the LNA, one of front-end circuits, locates on the receiving path of transceiver. The main functions are amplifying RF signal received from the antenna, providing input impedance matching and contributing as minimal noise as possible for the system working well.
Input matching is an important consideration for connection with external components. Described by microwave theoretic, signal is partially reflected if passing through the interface between two different mediums. The meaning in circuit design is unequal input/output impedances between two stages. To minimize the reflection, input
impedance of an LNA has to be designed to match 50-Ω characteristic impedance.
As passive device, an active device such as MOS or BJT contributes impedance. In the design with CMOS process, MOS device is applied with inductor in matching strategy. Fig. 24 helps the analysis by a simple small-signal model of MOS device.
Zin
I V
Cgs gmVgs
Ls Ls
Fig. 24. Input impedance matching According to Kirchhoff’s Voltage Law,
( )
As described in (1), the source inductor can be designed to eliminate the reactance; the transconductance gm, parasitical capacitance Cgs and source inductance LS can be designed to achieve 50-Ω resistance.Actually, input matching is also affected by other inevitable factors. There exists parasitical capacitance on input/output pads. If a chip under test is bonded on a board for measurement, bond-wires contribute parasitical inductance. The parasitic can be practically treated as a part of matching network so that the impedance, Zin in Fig. 24, cannot be designed to equal 50-Ω. Fig. 25 depicts a modified model with parasitic of a
pad and a bond-wire. Smith chart is useful for designing a proper value of Zin.
Fig. 26 is an impedance Smith chart and designed Zin locates on point 1. Cpad makes point 1 move to point 2 and Lbw makes point 2 move toward point 3. Zin’ of 50-Ω is available by this more practical method of matching design.
Many of modern technologies provide on-chip spiral inductors. The benefit makes it possible that input matching is achieved with fewer discrete components.
Zin
Cgs gmVgs
Ls Zin`
Lbw
Cpad
Fig. 25. Modified impedance model
Fig. 26. Impedance Smith chart
Next, Noise figure (NF) is a quantity generally used to estimate noise performance of an LNA. The noise performance on the inductor-degeneration configuration and designing an optimal dimension of the MOS devices will obtain the minimal noise contribution [42]. The following is a definition for noise figure, where SNR denotes signal to noise ratio.
Consider a MOS device on the inductor-degeneration configuration. Channel thermal noise and induced gate current noise are main sources in LNA design. The former occurs because of channel resistance. The later appears for the reason that channel charge fluctuates and then induces a physical current toward gate by capacitive coupling. A designer may not care about the later for general analog circuit design. In RF circuit, induced gate current noise, present as blue noise, becomes an inevitable noise contribution. Fig. 27 shows a noise model of the input stage, where VRg2 and
2
Fig. 27. Noise model of input stage
In the figure, RS and Rg are resistances of input terminal and gate; VRg2 and Ig2
correspond to two noise powers induced by RS and channel resistance, respectively.
Based on the model, theoretically minimal noise figure formulates as
, where γ is bias-dependent factor, L is channel length, vsat is saturation velocity, Vod
is overdrive voltage, εsat is velocity saturation field strength and Pc is power
consumption.
ε denotes ratio of two high-order polynomials. More details can be investigated in [41]. Channel width (W) is also an important parameter for the dimension decision and formulates as
( )
(14) with (15) reveals that channel width is an implicit function of NFmin.
For circuit designer, decidable parameters are Vdd, W, L and Pc. Minimal L is generally used for minimum NFmin. The designed LNA optimizes the noise performance by choice of W and Pc, since Vdd has been specified on 1 V. Fig. 28 plots NFmin curves based on analysis of [42].
Transconductance of input-stage MOS and load impedance dominate voltage gain in common-source-configuration amplifier. The transconductance is fixed while DC condition and dimension of the MOS has been decided for noise optimization and input matching. Sufficiently high load impedance or other advanced circuit structure with the identical input stage is then expected. In RF field, LC-tank is a proper choice for load impedance if fabrication technology is able to provide inductors with adequate Q-factors. Theoretically, the higher Q-factor load causes the higher gain. Common source cascode with LC-tank load is a popular structure in plenty of LNA designs. Not only Miller effect can be avoided but also reverse isolation is enhanced.
Fig. 28. NFmin curves to W and Pc
Although high-Q load increases gain effectively, linearity is contrarily degraded. In wireless communication, channel type is narrow band. An LNA operating with nonlinearity causes intermodulation while signals at various frequencies are received simultaneously [4]. The phenomenon produces other signals locating at frequencies close to those of received signals. There is an illustration in Fig. 29 for example. An LNA receives two signals of near frequencies ω1 andω2, and then outputs signals of ω1, ω2, 2ω1－ω2 and 2ω2－ω1. As the power of ω1 and ω2 increases, the power of 2ω1－ω2 and 2ω2－ω1 grows up in cube. The additional signals may fall on the adjacent channels and corrupt normal receiving.
w LNA
w
1w
2w
1w
2w
2w
1-w
22w
2-w
1Fig. 29. Intermodulation phenomenon
For acceptable linearity, extremely high voltage gain is not proposed. The gain is generally designed in an appropriate range of 15 ~ 25 dB in a conventional LNA for wireless communication.
RF receiver may easily suffer from noise coming from power supply because the input belongs to small signal. Differential circuit is a prevalent topology for the noise rejection. A differential amplifier is ideally designed to operate with differential signal.
The function is also simulated with pure differential signal. However, there exists common-mode issue in differential amplifier. Actually, a differential LNA may receive RF signal with a common-mode fraction. If one end of a differential pair does not perfectly match with the other, common-mode signal still appears on the single output terminal combined from the differential terminals. Too large common-mode signal corrupts desired signal or even saturates the amplifier. Even if the two ends match perfectly, large common-mode swing may saturate the circuit and then make the function inactive. Therefore, capability of common-mode rejection is considerable in differential amplifier design.
MOS device as current source is usually applied in analog integrated-circuit design.
The high drain-impedance providing source degeneration helps suppressing common- mode signal. However, the drain-impedance decreases to a very low value at a radio frequency. Common-mode feedback circuit may be another solution but consumes extra power. The design of LNA proposes applying LC-tank as source degenerator to suppress common-mode signal. LC-tank provides much higher impedance than a MOS device being current source in desired RF range. Besides, the LC-tank is appropriate in low-voltage low-power design.
Based on the considerations in the previous section, an LNA circuit is designed, shown in Fig. 30 with parameter information in Table 3-3. The LNA is common-source- cascode and fully differential configuration. Input matching and noise optimization are designed in Ll1, Ll2, Ml1 and Ml2. LC-tank constructed with Ll3, Ll4 and its total parasitical capacitanceprovides impedance for voltage gain. The other tank comprising Ll5 and its total parasitical capacitance works as a common-mode source degenerator. In
the aspect of low-voltage design, the output can swing over supply voltage because of the inductor character. Furthermore, the source degenerator hardly causes voltage drop.
Total DC-drop from sum of sufficient drain-source voltages is merely about 0.4 V by TSMC 0.18-μm technology. In the condition, LNA function is achievable at 1-V supply voltage. Most inductors applied are spiral inductors supported by TSMC 0.18-μ m technology. The 1.2-nH inductor is provided by National Chip Implementation Center (CIC). The equivalent circuit of spiral inductor is complicated due to obstacles in fabrication. There are also restrictions for usage, such as maximum operating frequency and various Q-factors at different frequencies.
M l1
Fig. 30. Designed LNA circuit
Table 3-3 Parameter information of Fig. 30
Ml1 and Ml2 50μm/0.18μm
Ml3 and Ml4 70μm/0.18μm
Ll1 ~ Ll4 2.4 nH
Ll5 1.2 nH
Rl1 5.4 kΩ
Rl2 and Rl3 33 kΩ
Cl1 and Cl2 0.55 pF