Structure of this Thesis

The devices which based on gate last fabrication process and the ones based on gate first were both measured in the experimental work. In chapter 2, how the instruments were used to accomplish the measured experiments is introduced. The comment about the basic concepts of the devices and measurement will also appear in this chapter.

In chapter 3, it is an introduction about the basic characteristics, and the results of the measured data are displayed. Eventually, there are discussion and summary with these results. There are the same procedures in chapter 4 like chapter 3, but the point is the reliability for the results with some stress measured experiments, and it is focused on the results of gate last process.

Finally, there are some conclusions about all these experiments in chapter 5, and some future work will also be referred to.

Several results of this study were also announced to SNDT 2011 (Symposium on Nano Device Technology) at NDL (National Nano Device Laboratories), Hsinchu,

Table 1.1 The comparison between HKMG and SiON for 28 nm process

from TSMC [1]

(a)

(b)

Figure 1.3 Simple structures both of GF and GL from IMEC [5]

Chapter 2

Experimental Methods and Basic Concepts

2.1 Experimental Methods

In this study, the instruments in the laboratory shown in Figure 2.1 were used to accomplish all the measured experiments. The devices which base on the 12 inch wafers shown in Figure 2.2 were used to do the measured work.

2.1.1 Preparative Work with the Instruments

In these measured experiments, at first, the probe station shown in Figure 2.3 was used to contact the wafer, and then there became a circuit between the devices and the probe station with four-point probe. In Figure 2.7, there is an E5250A (Low-leakage Switch Mainframe) which was used to connect the probe station and the other instruments. The E5250A was used to switch measured modes in these experiments.

Figure 2.4 shows the HP 4156A (Semiconductor Parameter Analyzer) which was used to measure I-V curve, as well as the HP 4284A (Precision LCR Meter) shown in Figure 2.5 for C-V curve measurement. In Figure 2.6, HP 81110A (165/330 MHz Pulse/Pattern Generator) was used to measure the data about Charge Pumping. These instruments are the main machines in the measured experiments.

2.1.2 Performance of the Experiments

As soon as all instruments were ready, measured work could be started with ICS (Interactive Characterization Software) shown in Figure 2.8. ICS was the software which was used to control HP 4156A, HP 4284A and HP 81110A for different measuring types. The details about setting parameters will be introduced later in chapter 3. In Figure 2.9, after measured work, the data were drawn with the software, which is named Origin. These results of I-V, C-V and Charge Pumping were used to analyze and

2.2 Basic Concepts of the Devices

In the experimental work, the characteristics of devices are affected by many factors. In order to research successfully, realization of some basic concepts is necessary.

The following paragraphs are some useful items.

2.2.1 SILC (Stress-Induced Leakage Current)

Stress-induced leakage current (SILC) is the current which occur in gate layer while the device is applied to the constant voltage or current stress. While the oxide thickness become thinner more and more, SILC is an important problem and the reliability of the device would be varied. Thus, SILC is used to characterize the degradation of ultra-thin gate oxides and to predict their breakdown and lifetime, as it is generally believed that SILC is induced by defects generated in gate oxides [6]. Figure 2.10 shows the diagram of SILC.

2.2.2 SCE (Short-Channel Effects)

The short-channel effects on threshold voltage become significant while the channel length becomes less than approximately 2 um.

As the channel length reduces, the charge in the channel region which controlled by the gate would decrease. While the drain voltage increases, the reverse-biased space charge region at the drain would extend into the channel area. Therefore, the bulk charge which controlled by the gate would decrease. These results induced the threshold voltage of the nMOSFET shifts in the negative direction [7]. In other word, SCE induced threshold voltage roll-off.

SCE would also cause DIBL, and higher leakage currents while the device cut-off.

Therefore, even the gate voltage is be grounded, there are leakage currents flow through the source and the drain [8].

2.2.3 DIBL (Drain-Induced Barrier Lowering)

voltage in the short-channel device. This phenomenon is called DIBL [7].

2.2.4 GIDL (Gate-Induced Drain Leakage)

While the gate terminal is provided an enough big voltage, the high electric field in depletion region would induce the band to band tunneling leakage in the drain region underneath the gate. That is called GIDL current. When a high electric field is applied to a p-n junction in the reverse direction, the valence electron could make a transition from the valence band to the conduction band. The process that the electron penetrate through the energy band-gap is called tunneling effect [7].

2.2.5 HCE (Hot-Carrier Effect)

Considering the tunneling effect, as the electric field in the drain junction space charge region increases, electron-hole pairs could be generated by impact ionization.

The generated electrons tend to be swept to the drain and generated holes swept into the substrate of the device. Some of the electrons generated in the space charge region are attracted to the oxide due to the electric field induced by a gate voltage. Figure 2.11 shows the diagram of HCE. HCE would induce the substrate currents increased, and the drain currents could not saturate in saturation region. The drain currents would increase when the drain voltage increase. As the serious condition, punch trough would occur with more leakage currents [8].

2.2.6 D

it

(Interface Trap Density)

Dit is the density of the interface. In addition, Nit is the interface trap numbers.

They mean the trapped charge condition in the interface layer. The traps would capture the carriers and thus affect the characteristics of the device. The Dit is calculated by Dit

= (ICP/qAfΔE), where ICP is the measured Charge Pumping currents, q is the fundamental electronic charge, A is the area, f is the frequency, and ΔE is the difference between the inversion Fermi level and the accumulation Fermi level [9].

2.3 Introduction of the Measured Modes

In order to perform the measured experiments successfully, not only the measured steps but also the principles of the measurement should be realized. That would be helpful in the study. The following are some items about that.

2.3.1 I-V Measurement

It is three types, IDVD, IDVG and IGVG, of I-V measurements. There are the figures of the I-V curves shown in Chapter 3 and Chapter 4. In IDVD measured work, ID versus VD curves could be extracted. That could be used to decide the characteristics while the device was operating.

For the drawing of IDVG and IGVG figures, the original data would be added modulus and then transferred into logarithm type. For IDVG curve, threshold voltage of the device could be extracted, and the sub-threshold swing (SS) could be determined.

For IGVG curve, leakage currents flowed through the gate layer could be observed.

These I-V curves composed to characteristics of the device.

2.3.2 C-V Measurement

As the C-V measured experiments, the results of C-V curves would include accumulation, depletion, weak inversion and strong inversion. During the accumulation region, the carriers would accumulate at the interface between Si and gate dielectric.

The capacitance value would be determined by almost only by the Cox since the CSD is very high. In accumulation region, the capacitance value would decrease while the carriers accumulate more and more.

When the gate voltage is higher than the flat-band voltage, the device would go into depletion and weak inversion region. At this time, the CSD would become smaller so that the capacitance value would be determined by both the Cox and the CSD. Therefore, the capacitance value would approach to a saturation state with the high frequency.

With the low frequency, when the gate voltage is higher than the threshold voltage, bigger voltage would lead to the holes at the gate layer go through interface and

In this study, the C-V measurement was provided with the voltage of substrate, not gate. Thus, The C-V data should be added a minus to the voltage value. There are the figures of the C-V curves shown in Chapter 3 and Chapter 4.

2.3.3 Principle of Charge Pumping

There is the typical Charge Pumping measured system chart shown in Figure 2.12.

As the figure showing, the source and drain (S/D) of the device are connected together with a variable voltage source. The channel would be conducted while the device is applied to a high voltage pulse and achieves inversion region. Therefore, the charges in the source and drain region could move through the channel, and they are liable to be captured by the traps in the surface.

The channel would return to depletion while the device is applied to a low voltage pulse, and the mobile charge would come back to the S/D terminals. The charges which are captured by the traps could not come back to the S/D region. They would have recombination with the majority carriers from the substrate and then increase the currents in substrate. This phenomenon is called Charge Pumping [10].

By exploring the currents (ICP) from Charge Pumping measurement, Dit and the defect of the device could be estimated.

Figure 2.1 The instruments in the laboratory

Figure 2.2 The 12 inch wafer for the measured experiments

Figure 2.3 Probe Station

Figure 2.4 Agilent HP 4156A (Semiconductor Parameter Analyzer)

Figure 2.5 Agilent HP 4284A (Precision LCR Meter)

Figure 2.6 Agilent HP 81110A (165/330 MHz Pulse/Pattern Generator)

Figure 2.7 Agilent E5250A (Low-leakage Switch Mainframe)

Figure 2.8 Agilent ICS (Interactive Characterization Software)

Figure 2.9 Origin

Figure 2.10 The diagram of SILC [6]

Figure 2.11 The diagram of HCE [8]

Figure 2.12 The typical Charge Pumping measured system chart [10]

Chapter 3

Basic Characteristics of High-k/Metal Gate Devices with Various Post Treatments

3.1 About the Experiments Working

As the beginning for the experiments, it is necessary to realize the composition of the devices. Various post treatments induced various structures and measured results for the devices. In order to work the experiments successfully, the setting for the software is very important. The following are comments about both devices forming and software setting.

3.1.1 The Wafers for the Measured Work

The devices which based on GL and GF process were both measured in the experimental work. For these 12 inch wafers, it were focused on results of the gate last process, and then compared to results of the gate first process.

For GL process, these 12 inch wafers were manufactured with various post metallization annealing (PMA) treatments. The PMA treatments were fabricated with oxygen or nitrogen, and the annealing temperatures were 400^oC or 450^oC, respectively.

These factors constituted various treatments of the PMA conditions. First, there was a wafer without any post metallization annealing. Second, there was a wafer with 400^oC annealing and oxygen post treatment, and another one with nitrogen post treatments at the same annealing temperature. Third, there was a wafer with 450^oC annealing and oxygen post treatment, and another one with nitrogen post treatment at the same temperature, respectively.

For GF process, those 12 inch wafers were manufactured with the capping layer of the lanthanum oxide (LaO) and aluminum oxide (AlO) for NMOS and PMOS, respectively. The various cycles of deposition would cause various thicknesses of the

would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. Titanium nitride (TiN) was used as the gate electrodes for both GL and GF process devices.

These various factors of the 12 inch wafers were listed in Table 3.1, and the simple structure both of the GL and GF devices were shown in Figure 3.1.

3.1.2 Setting for ICS

After the preparation for the instruments which were mentioned in chapter 2, ICS used to measure I-V, C-V, and Charge Pumping. For I-V measuring, the terminals of source and body would be grounded. Gate and drain would be provided with the voltage in sweep mode or step mode. The mode selecting depends on IDVG or IDVD measuring.

C-V and Charge Pumping settings were similar to I-V, and both of their VG range selecting depends on the curve shape. The frequency would also affect the curves.

To describe accurately, the detailed setting appeared in Table 3.2. It also shows the stress details for reliability which will be discussed in chapter 4.

3.2 Experimental Results and Discussion

It was found that the characteristics of nMOSFETs and pMOSFETs were not symmetrical. Figure 3.2 shows the IDVD curves both of GL and GF devices. No matter GL or GF devices, the currents of PMOS were smaller than NMOS ones. The key factor was that the carrier of NMOS devices was electron, and the carrier of PMOS was holes.

Their operational principles were different. Therefore, the results of NMOS and PMOS should be discussed respectively. The experimental results would be discussed later.

3.2.1 I-V

Currents versus voltage curves of the gate last NMOS devices were shown in Figure 3.3. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (V – V) at x-axis. The purpose was eliminating the effect of threshold

PMA condition would be highest than the others according to the figure of normalized IDVG curves. The leakage currents in gate layer would reveal the same trend according to the figure of IGVG curves. The gate leakage currents of the device without PMA condition would be also the highest one.

Figure 3.4 shows the I-V curves of the gate last PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NOMS. The drain currents at saturation region with various post treatments were almost the same. The gate leakage currents of the device without PMA condition would be the highest one. It was found that the gate leakage currents would be decreased by PMA post treatments.

The threshold voltages of the devices with various PMA conditions were different shown in Figure 3.5. It was related to the Dit and the oxygen vacancies in the gate dielectric. They would be discussed later in chapter 4.

I-V curves of the gate first NMOS devices were shown in Figure 3.6. For the normalized IDVD curves, VG was set as (Vt + 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. The purpose was eliminating the effect of threshold voltage. The IDVD curves with various thicknesses of capping layer were different. The differences of the drain currents at saturation region were under 0.1 mA, but the GF drive currents were smaller than GL ones. The GL drive currents were about 8 times of the GF ones, according to Figure 3.2. Therefore the differences of drive currents could not be ignored for GF devices. The leakage currents in gate layer of the device without LaO capping layer was the highest one, as well as the other ones decreased with capping layer increased due to the thicker dielectric thickness. Figure 3.7 shows the I-V curves of the gate first PMOS devices. For the normalized IDVD curves, VG was set as (Vt – 1), while the IDVG curves were normalized with (VG – Vt) at x-axis. They revealed the same trend to NMOS.

The threshold voltages of the devices with various thicknesses of capping layer were different which were shown in Figure 3.8. The oxygen in the gate dielectric would be pulled into the capping layer, which caused the more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the

3.2.2 C-V

Figure 3.9 shows the capacitance versus voltage curves of the GL devices. In order to eliminate the effect of flat-band voltage, the normalized C-V curves were shown in Figure 3.10. The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions.

Figure 3.11 shows the C-V curves of the GF devices, and the normalized C-V curves of the ones were shown in Figure 3.12. They almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different. All the C-V curves were measured with 1MHz frequency.

3.2.3 Charge Pumping

Figure 3.13 shows the charge pumping curves of the gate first devices. The Dit of the PMOS devices was higher than NMOS ones. Comparing to the normalized C-V curves shown in Figure 3.12, the slope of the accumulation region of the C-V curves would correspond to the Dit of the Charge Pumping.

The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric.

The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves shown in Figure 3.10.

3.3 Summary

For GL devices, the drive currents of the devices with various PMA conditions would not vary a lot. They were almost the same. The other side, the leakage currents and

For GF devices, the drive currents of the devices with various thicknesses of capping layer were different. The other side, the leakage currents would be decreased by the capping layer. The threshold voltages of the devices with various thicknesses of capping layer were related to the Dit and the oxygen vacancies in the gate dielectric. The thicker capping layer would induce much Dit in gate dielectric, thus there was the larger threshold voltage shift. With the deposition of the capping layer, the oxygen in the gate dielectric would be pulled into the capping layer, which caused more oxygen vacancies in the gate dielectric. Therefore, the threshold voltage would decrease while the thickness of the capping layer increased. That effect was obvious for the devices with the LaO deposition than the AlO ones.

The flat-band voltages both of the NMOS and PMOS devices without PMA condition were the smallest. The normalized C-V curves both of the NMOS and PMOS devices were almost overlapped, which means the Dit of the devices would not vary a lot with various PMA conditions. The C-V curves of the GF devices almost revealed the same trend to the GL devices, but the slopes of the curves in accumulation region were different.

The Dit of the GF devices would change with various deposition thicknesses. The thicker capping layer would induce much Dit in gate dielectric, because more cycles of deposition would induce more oxygen to release from high-k dielectric and thus result in more oxygen vacancies, which would cause flat-band voltage shift. Thus there was the larger threshold voltage shift with much Dit in gate dielectric. Besides, The Dit of the GL devices would not vary a lot according to the accumulation region of the C-V curves.

Table 3.1 Various factors of the 12 inch wafers

Various factors of the 12 inch wafers

Without Post Metallization Annealing Condition

With 400^oC Annealing and Oxygen Post Treatment

With 400^oC Annealing and Nitrogen Post Treatment

With 450^oC Annealing and Oxygen Post Treatment

Gate Last

With 450^oC Annealing and Nitrogen Post Treatment

Without Lanthanum Oxide Post Treatment

With Lanthanum Oxide 15C Post Treatment

LaO

With Lanthanum Oxide 30C Post Treatment

Without Aluminum Oxide Post Treatment

With Aluminum Oxide 6C Post Treatment

Gate First

AlO

With Aluminum Oxide 11C Post Treatment

Table 3.2 Experiment methods and parameters setup

Device

Characteristics

Measured Type

Parameter Setup

Vth, Sub-Threshold

Swing (SS), ID, Gm

ID-VG VG = -05 ~ 1.5 V (Sweeep Mode) VD = 0.05 ~ 1.5 V (Step Mode) VS = VB = 0 V (Common Mode) (For NMOS. Add minus if PMOS) Drive Current (ID) ID-VD VG = Vth + 1 V (Constant Mode) (For NMOS. Add minus if PMOS) Capacitance,

Equivalent Oxide Thickness (EOT)

C-V Frequency = 1 MHz

VG range depends on the curve shape (Sweeep Mode)

ICP, Interface Trap Pulse Period = 1μsec

Vbase range depends on the curve shape Reliability Constant

Voltage Stress

Room Temperature

VG = Vstress (Constant Mode)

VD = VS = VB = 0 V (Common Mode)

(a)

(b)

Figure 3.1 Structure of the (a) gate last and (b) gate first devices

Source Drain

Silicon Substrate IL

Two Metals HK Gate Oxide

Source Drain IL

HK Gate Oxide LaO or AlO

TiN

Silicon Substrate

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Without PMA

With 400^oC O₂ PMA With 400^oC N

2 PMA W = 10 um

L = 1 um

Both NMOS & PMOS

(a)

Without LaO LaO15C LaO30C Without AlO AlO6C AlO11C

W = 10 um L = 1 um

(b)

0.0 0.5 1.0 1.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

NMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A )

V

G

(V)

(c)

Figure 3.3 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last NMOS devices with various PMA conditions

-1.5 -1.0 -0.5 0.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 1E-15

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

PMOS W = 10 um L = 1 um

No PMA 400C O2 PMA 400C N2 PMA 450C O2 PMA 450C N2 PMA

I

G

(A)

V

G

(V)

(c)

Figure 3.4 (a) I

DVD (b) IDVG and (c) IGVG curves of the gate last PMOS devices with various PMA conditions

0.3

W=10um L=1um

W=10um L=1um

在文檔中 針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 (頁 13-0)